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MPC85xx: TQM8548_AG: add 1 GiB DDR2-SDRAM configuration

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This patch add support for the 1 GiB DDR2-SDRAM on the TQM8548_AG
module.

Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
This commit is contained in:
Wolfgang Grandegger 2009-02-11 18:38:24 +01:00 committed by Andy Fleming
parent 88b0e88d18
commit dc5f55d636
3 changed files with 26 additions and 4 deletions
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2
board/tqc/tqm85xx/law.c
View file

@ -66,7 +66,7 @@
#endif
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_2G, LAW_TRGT_IF_DDR),
SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),

9
board/tqc/tqm85xx/sdram.c
View file

@ -38,11 +38,20 @@ struct sdram_conf_s {
typedef struct sdram_conf_s sdram_conf_t;
#ifdef CONFIG_TQM8548
#ifdef CONFIG_TQM8548_AG
sdram_conf_t ddr_cs_conf[] = {
{(1024 << 20), 0x80044202, 0x0002D000}, /* 1024MB, 14x10(4) */
{ (512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
{ (256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
{ (128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
};
#else /* !CONFIG_TQM8548_AG */
sdram_conf_t ddr_cs_conf[] = {
{(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
{(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
{(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
};
#endif /* CONFIG_TQM8548_AG */
#else /* !CONFIG_TQM8548 */
sdram_conf_t ddr_cs_conf[] = {
{(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */

19
board/tqc/tqm85xx/tlb.c
View file

@ -121,12 +121,25 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 6, BOOKE_PAGESZ_64M, 1),
#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE)
/*
* TLB 7+8: 2G DDR, cache enabled
* 0x00000000 2G DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
*/
SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 7, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 8, BOOKE_PAGESZ_1G, 1),
#else
/*
* TLB 7+8: 512M DDR, cache disabled (needed for memory test)
* 0x00000000 512M DDR System memory
* Without SPD EEPROM configured DDR, this must be setup manually.
* Make sure the TLB count at the top of this table is correct.
* Likely it needs to be increased by two for these entries.
*/
SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
@ -136,7 +149,7 @@ struct fsl_e_tlb_entry tlb_table[] = {
CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
0, 8, BOOKE_PAGESZ_256M, 1),
#endif
#ifdef CONFIG_PCIE1
/*
* TLB 9: 16M Non-cacheable, guarded