mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-17 02:08:38 +00:00
arm: dts: rockchip: rk3288: partial sync grf and pmu nodes
In order to better compare the Linux rk3288.dtsi version 6.3 -rc2 with the U-Boot version partial sync the grf and pmu nodes. Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Johan Jonker
Kever Yang
parent
35e9e8aebf
commit
da5ae37fcd
1 changed files with 173 additions and 96 deletions
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@ -1,4 +1,4 @@
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// SPDX-License-Identifier: GPL-2.0+
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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@ -7,13 +7,16 @@
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <dt-bindings/clock/rk3288-cru.h>
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#include <dt-bindings/power/rk3288-power.h>
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#include <dt-bindings/power/rk3288-power.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/thermal/thermal.h>
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#include <dt-bindings/video/rk3288.h>
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#include <dt-bindings/soc/rockchip,boot-mode.h>
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#include "skeleton.dtsi"
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/ {
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "rockchip,rk3288";
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compatible = "rockchip,rk3288";
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interrupt-parent = <&gic>;
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interrupt-parent = <&gic>;
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aliases {
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aliases {
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ethernet0 = &gmac;
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ethernet0 = &gmac;
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i2c0 = &i2c0;
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i2c0 = &i2c0;
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@ -732,8 +735,128 @@
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};
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};
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pmu: power-management@ff730000 {
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pmu: power-management@ff730000 {
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compatible = "rockchip,rk3288-pmu", "syscon";
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compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
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reg = <0xff730000 0x100>;
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reg = <0xff730000 0x100>;
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power: power-controller {
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compatible = "rockchip,rk3288-power-controller";
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#power-domain-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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assigned-clocks = <&cru SCLK_EDP_24M>;
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assigned-clock-parents = <&xin24m>;
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/*
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* Note: Although SCLK_* are the working clocks
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* of device without including on the NOC, needed for
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* synchronous reset.
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*
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* The clocks on the which NOC:
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* ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
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* ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
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* ACLK_RGA is on ACLK_RGA_NIU.
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* The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
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*
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* Which clock are device clocks:
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* clocks devices
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* *_IEP IEP:Image Enhancement Processor
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* *_ISP ISP:Image Signal Processing
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* *_VIP VIP:Video Input Processor
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* *_VOP* VOP:Visual Output Processor
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* *_RGA RGA
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* *_EDP* EDP
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* *_LVDS_* LVDS
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* *_HDMI HDMI
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* *_MIPI_* MIPI
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*/
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power-domain@RK3288_PD_VIO {
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reg = <RK3288_PD_VIO>;
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clocks = <&cru ACLK_IEP>,
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<&cru ACLK_ISP>,
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<&cru ACLK_RGA>,
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<&cru ACLK_VIP>,
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<&cru ACLK_VOP0>,
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<&cru ACLK_VOP1>,
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<&cru DCLK_VOP0>,
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<&cru DCLK_VOP1>,
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<&cru HCLK_IEP>,
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<&cru HCLK_ISP>,
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<&cru HCLK_RGA>,
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<&cru HCLK_VIP>,
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<&cru HCLK_VOP0>,
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<&cru HCLK_VOP1>,
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<&cru PCLK_EDP_CTRL>,
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<&cru PCLK_HDMI_CTRL>,
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<&cru PCLK_LVDS_PHY>,
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<&cru PCLK_MIPI_CSI>,
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<&cru PCLK_MIPI_DSI0>,
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<&cru PCLK_MIPI_DSI1>,
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<&cru SCLK_EDP_24M>,
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<&cru SCLK_EDP>,
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<&cru SCLK_ISP_JPE>,
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<&cru SCLK_ISP>,
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<&cru SCLK_RGA>;
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pm_qos = <&qos_vio0_iep>,
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<&qos_vio1_vop>,
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<&qos_vio1_isp_w0>,
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<&qos_vio1_isp_w1>,
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<&qos_vio0_vop>,
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<&qos_vio0_vip>,
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<&qos_vio2_rga_r>,
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<&qos_vio2_rga_w>,
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<&qos_vio1_isp_r>;
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#power-domain-cells = <0>;
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};
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/*
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* Note: The following 3 are HEVC(H.265) clocks,
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* and on the ACLK_HEVC_NIU (NOC).
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*/
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power-domain@RK3288_PD_HEVC {
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reg = <RK3288_PD_HEVC>;
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clocks = <&cru ACLK_HEVC>,
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<&cru SCLK_HEVC_CABAC>,
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<&cru SCLK_HEVC_CORE>;
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pm_qos = <&qos_hevc_r>,
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<&qos_hevc_w>;
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#power-domain-cells = <0>;
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};
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/*
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* Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
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* (video endecoder & decoder) clocks that on the
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* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
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*/
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power-domain@RK3288_PD_VIDEO {
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reg = <RK3288_PD_VIDEO>;
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clocks = <&cru ACLK_VCODEC>,
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<&cru HCLK_VCODEC>;
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pm_qos = <&qos_video>;
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#power-domain-cells = <0>;
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};
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/*
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* Note: ACLK_GPU is the GPU clock,
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* and on the ACLK_GPU_NIU (NOC).
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*/
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power-domain@RK3288_PD_GPU {
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reg = <RK3288_PD_GPU>;
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clocks = <&cru ACLK_GPU>;
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pm_qos = <&qos_gpu_r>,
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<&qos_gpu_w>;
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#power-domain-cells = <0>;
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};
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};
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reboot-mode {
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compatible = "syscon-reboot-mode";
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offset = <0x94>;
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mode-normal = <BOOT_NORMAL>;
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mode-recovery = <BOOT_RECOVERY>;
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mode-bootloader = <BOOT_FASTBOOT>;
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mode-loader = <BOOT_BL_DOWNLOAD>;
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};
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};
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};
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sgrf: syscon@ff740000 {
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sgrf: syscon@ff740000 {
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@ -760,13 +883,58 @@
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};
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};
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grf: syscon@ff770000 {
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grf: syscon@ff770000 {
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compatible = "rockchip,rk3288-grf", "syscon";
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compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
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reg = <0xff770000 0x1000>;
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reg = <0xff770000 0x1000>;
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edp_phy: edp-phy {
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compatible = "rockchip,rk3288-dp-phy";
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clocks = <&cru SCLK_EDP_24M>;
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clock-names = "24m";
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#phy-cells = <0>;
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status = "disabled";
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};
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io_domains: io-domains {
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io_domains: io-domains {
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compatible = "rockchip,rk3288-io-voltage-domain";
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compatible = "rockchip,rk3288-io-voltage-domain";
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status = "disabled";
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status = "disabled";
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};
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};
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usbphy: usbphy {
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compatible = "rockchip,rk3288-usb-phy";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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usbphy0: usb-phy@320 {
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#phy-cells = <0>;
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reg = <0x320>;
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clocks = <&cru SCLK_OTGPHY0>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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resets = <&cru SRST_USBOTG_PHY>;
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reset-names = "phy-reset";
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};
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usbphy1: usb-phy@334 {
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#phy-cells = <0>;
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reg = <0x334>;
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clocks = <&cru SCLK_OTGPHY1>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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resets = <&cru SRST_USBHOST0_PHY>;
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reset-names = "phy-reset";
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};
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usbphy2: usb-phy@348 {
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#phy-cells = <0>;
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reg = <0x348>;
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clocks = <&cru SCLK_OTGPHY2>;
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clock-names = "phyclk";
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#clock-cells = <0>;
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resets = <&cru SRST_USBHOST1_PHY>;
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reset-names = "phy-reset";
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};
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};
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};
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};
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wdt: watchdog@ff800000 {
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wdt: watchdog@ff800000 {
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@ -1246,39 +1414,6 @@
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interrupts = <GIC_PPI 9 0xf04>;
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interrupts = <GIC_PPI 9 0xf04>;
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};
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};
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cpuidle: cpuidle {
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compatible = "rockchip,rk3288-cpuidle";
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};
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usbphy: phy {
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compatible = "rockchip,rk3288-usb-phy";
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rockchip,grf = <&grf>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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usbphy0: usb-phy0 {
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#phy-cells = <0>;
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reg = <0x320>;
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clocks = <&cru SCLK_OTGPHY0>;
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clock-names = "phyclk";
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};
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usbphy1: usb-phy1 {
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#phy-cells = <0>;
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reg = <0x334>;
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clocks = <&cru SCLK_OTGPHY1>;
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clock-names = "phyclk";
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};
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usbphy2: usb-phy2 {
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#phy-cells = <0>;
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reg = <0x348>;
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clocks = <&cru SCLK_OTGPHY2>;
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clock-names = "phyclk";
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};
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};
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pinctrl: pinctrl {
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pinctrl: pinctrl {
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compatible = "rockchip,rk3288-pinctrl";
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compatible = "rockchip,rk3288-pinctrl";
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rockchip,grf = <&grf>;
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rockchip,grf = <&grf>;
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@ -1865,62 +2000,4 @@
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};
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};
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};
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};
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};
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};
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power: power-controller {
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compatible = "rockchip,rk3288-power-controller";
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#power-domain-cells = <1>;
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rockchip,pmu = <&pmu>;
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#address-cells = <1>;
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#size-cells = <0>;
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pd_gpu {
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reg = <RK3288_PD_GPU>;
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clocks = <&cru ACLK_GPU>;
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};
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pd_hevc {
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reg = <RK3288_PD_HEVC>;
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clocks = <&cru ACLK_HEVC>,
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<&cru SCLK_HEVC_CABAC>,
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<&cru SCLK_HEVC_CORE>,
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<&cru HCLK_HEVC>;
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};
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pd_vio {
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reg = <RK3288_PD_VIO>;
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clocks = <&cru ACLK_IEP>,
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<&cru ACLK_ISP>,
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<&cru ACLK_RGA>,
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<&cru ACLK_VIP>,
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<&cru ACLK_VOP0>,
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<&cru ACLK_VOP1>,
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<&cru DCLK_VOP0>,
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<&cru DCLK_VOP1>,
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<&cru HCLK_IEP>,
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<&cru HCLK_ISP>,
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<&cru HCLK_RGA>,
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<&cru HCLK_VIP>,
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<&cru HCLK_VOP0>,
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<&cru HCLK_VOP1>,
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<&cru PCLK_EDP_CTRL>,
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<&cru PCLK_HDMI_CTRL>,
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<&cru PCLK_LVDS_PHY>,
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<&cru PCLK_MIPI_CSI>,
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<&cru PCLK_MIPI_DSI0>,
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<&cru PCLK_MIPI_DSI1>,
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<&cru SCLK_EDP_24M>,
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<&cru SCLK_EDP>,
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<&cru SCLK_HDMI_CEC>,
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<&cru SCLK_HDMI_HDCP>,
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<&cru SCLK_ISP_JPE>,
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<&cru SCLK_ISP>,
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<&cru SCLK_RGA>;
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};
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pd_video {
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reg = <RK3288_PD_VIDEO>;
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clocks = <&cru ACLK_VCODEC>,
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<&cru HCLK_VCODEC>;
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};
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};
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};
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};
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