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watchdog: Add StarFive Watchdog driver
Add to support StarFive watchdog driver. The driver is imported from linux kernel's drivers/watchdog/starfive-wdt.c without jh7100 support because there is no support of jh7100 SoC in u-boot yet. Howver, this patch has been kept the variant coding style because JH7100 can be added later and have a consistency with the linux driver. Signed-off-by: Chanho Park <chanho61.park@samsung.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Chanho Park
Leo Yu-Chi Liang
parent
8ef2d7926f
commit
da26455098
3 changed files with 337 additions and 0 deletions
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@ -344,6 +344,13 @@ config WDT_STM32MP
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Enable the STM32 watchdog (IWDG) driver. Enable support to
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configure STM32's on-SoC watchdog.
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config WDT_STARFIVE
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bool "StarFive watchdog timer support"
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depends on WDT
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imply WATCHDOG
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help
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Enable support for the watchdog timer of StarFive JH7110 SoC.
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config WDT_SUNXI
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bool "Allwinner sunxi watchdog timer support"
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depends on WDT && ARCH_SUNXI
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@ -44,6 +44,7 @@ obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
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obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o
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obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o
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obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
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obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o
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obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
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obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o
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obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o
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329
drivers/watchdog/starfive_wdt.c
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329
drivers/watchdog/starfive_wdt.c
Normal file
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@ -0,0 +1,329 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Starfive Watchdog driver
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*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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*/
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#include <clk.h>
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#include <dm.h>
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#include <reset.h>
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#include <wdt.h>
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#include <linux/iopoll.h>
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/* JH7110 Watchdog register define */
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#define STARFIVE_WDT_JH7110_LOAD 0x000
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#define STARFIVE_WDT_JH7110_VALUE 0x004
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#define STARFIVE_WDT_JH7110_CONTROL 0x008 /*
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* [0]: reset enable;
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* [1]: interrupt enable && watchdog enable
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* [31:2]: reserved.
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*/
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#define STARFIVE_WDT_JH7110_INTCLR 0x00c /* clear intterupt and reload the counter */
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#define STARFIVE_WDT_JH7110_IMS 0x014
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#define STARFIVE_WDT_JH7110_LOCK 0xc00 /* write 0x1ACCE551 to unlock */
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/* WDOGCONTROL */
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#define STARFIVE_WDT_ENABLE 0x1
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#define STARFIVE_WDT_EN_SHIFT 0
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#define STARFIVE_WDT_RESET_EN 0x1
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#define STARFIVE_WDT_JH7110_RST_EN_SHIFT 1
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/* WDOGLOCK */
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#define STARFIVE_WDT_JH7110_UNLOCK_KEY 0x1acce551
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/* WDOGINTCLR */
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#define STARFIVE_WDT_INTCLR 0x1
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#define STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT 1 /* Watchdog can clear interrupt when 0 */
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#define STARFIVE_WDT_MAXCNT 0xffffffff
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#define STARFIVE_WDT_DEFAULT_TIME (15)
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#define STARFIVE_WDT_DELAY_US 0
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#define STARFIVE_WDT_TIMEOUT_US 10000
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/* module parameter */
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#define STARFIVE_WDT_EARLY_ENA 0
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struct starfive_wdt_variant {
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unsigned int control; /* Watchdog Control Resgister for reset enable */
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unsigned int load; /* Watchdog Load register */
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unsigned int reload; /* Watchdog Reload Control register */
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unsigned int enable; /* Watchdog Enable Register */
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unsigned int value; /* Watchdog Counter Value Register */
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unsigned int int_clr; /* Watchdog Interrupt Clear Register */
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unsigned int unlock; /* Watchdog Lock Register */
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unsigned int int_status; /* Watchdog Interrupt Status Register */
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u32 unlock_key;
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char enrst_shift;
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char en_shift;
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bool intclr_check; /* whether need to check it before clearing interrupt */
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char intclr_ava_shift;
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bool double_timeout; /* The watchdog need twice timeout to reboot */
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};
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struct starfive_wdt_priv {
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void __iomem *base;
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struct clk *core_clk;
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struct clk *apb_clk;
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struct reset_ctl_bulk *rst;
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const struct starfive_wdt_variant *variant;
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unsigned long freq;
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u32 count; /* count of timeout */
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u32 reload; /* restore the count */
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};
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/* Register layout and configuration for the JH7110 */
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static const struct starfive_wdt_variant starfive_wdt_jh7110_variant = {
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.control = STARFIVE_WDT_JH7110_CONTROL,
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.load = STARFIVE_WDT_JH7110_LOAD,
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.enable = STARFIVE_WDT_JH7110_CONTROL,
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.value = STARFIVE_WDT_JH7110_VALUE,
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.int_clr = STARFIVE_WDT_JH7110_INTCLR,
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.unlock = STARFIVE_WDT_JH7110_LOCK,
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.unlock_key = STARFIVE_WDT_JH7110_UNLOCK_KEY,
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.int_status = STARFIVE_WDT_JH7110_IMS,
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.enrst_shift = STARFIVE_WDT_JH7110_RST_EN_SHIFT,
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.en_shift = STARFIVE_WDT_EN_SHIFT,
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.intclr_check = false,
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.double_timeout = true,
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};
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static int starfive_wdt_enable_clock(struct starfive_wdt_priv *wdt)
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{
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int ret;
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ret = clk_enable(wdt->apb_clk);
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if (ret)
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return ret;
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ret = clk_enable(wdt->core_clk);
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if (ret) {
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clk_disable(wdt->apb_clk);
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return ret;
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}
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return 0;
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}
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static void starfive_wdt_disable_clock(struct starfive_wdt_priv *wdt)
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{
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clk_disable(wdt->core_clk);
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clk_disable(wdt->apb_clk);
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}
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/* Write unlock-key to unlock. Write other value to lock. */
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static void starfive_wdt_unlock(struct starfive_wdt_priv *wdt)
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{
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writel(wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
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}
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static void starfive_wdt_lock(struct starfive_wdt_priv *wdt)
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{
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writel(~wdt->variant->unlock_key, wdt->base + wdt->variant->unlock);
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}
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/* enable watchdog interrupt to reset/reboot */
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static void starfive_wdt_enable_reset(struct starfive_wdt_priv *wdt)
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{
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u32 val;
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val = readl(wdt->base + wdt->variant->control);
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val |= STARFIVE_WDT_RESET_EN << wdt->variant->enrst_shift;
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writel(val, wdt->base + wdt->variant->control);
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}
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/* waiting interrupt can be free to clear */
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static int starfive_wdt_wait_int_free(struct starfive_wdt_priv *wdt)
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{
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u32 value;
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return readl_poll_timeout(wdt->base + wdt->variant->int_clr, value,
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!(value & BIT(wdt->variant->intclr_ava_shift)),
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STARFIVE_WDT_TIMEOUT_US);
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}
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/* clear interrupt signal before initialization or reload */
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static int starfive_wdt_int_clr(struct starfive_wdt_priv *wdt)
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{
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int ret;
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if (wdt->variant->intclr_check) {
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ret = starfive_wdt_wait_int_free(wdt);
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if (ret)
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return ret;
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}
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writel(STARFIVE_WDT_INTCLR, wdt->base + wdt->variant->int_clr);
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return 0;
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}
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static inline void starfive_wdt_set_count(struct starfive_wdt_priv *wdt,
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u32 val)
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{
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writel(val, wdt->base + wdt->variant->load);
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}
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/* enable watchdog */
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static inline void starfive_wdt_enable(struct starfive_wdt_priv *wdt)
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{
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u32 val;
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val = readl(wdt->base + wdt->variant->enable);
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val |= STARFIVE_WDT_ENABLE << wdt->variant->en_shift;
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writel(val, wdt->base + wdt->variant->enable);
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}
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/* disable watchdog */
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static inline void starfive_wdt_disable(struct starfive_wdt_priv *wdt)
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{
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u32 val;
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val = readl(wdt->base + wdt->variant->enable);
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val &= ~(STARFIVE_WDT_ENABLE << wdt->variant->en_shift);
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writel(val, wdt->base + wdt->variant->enable);
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}
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static inline void starfive_wdt_set_reload_count(struct starfive_wdt_priv *wdt,
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u32 count)
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{
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starfive_wdt_set_count(wdt, count);
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/* 7100 need set any value to reload register and could reload value to counter */
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if (wdt->variant->reload)
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writel(0x1, wdt->base + wdt->variant->reload);
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}
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static int starfive_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
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{
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int ret;
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struct starfive_wdt_priv *wdt = dev_get_priv(dev);
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starfive_wdt_unlock(wdt);
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/* disable watchdog, to be safe */
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starfive_wdt_disable(wdt);
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starfive_wdt_enable_reset(wdt);
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ret = starfive_wdt_int_clr(wdt);
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if (ret)
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goto exit;
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wdt->count = (timeout_ms / 1000) * wdt->freq;
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if (wdt->variant->double_timeout)
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wdt->count /= 2;
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starfive_wdt_set_count(wdt, wdt->count);
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starfive_wdt_enable(wdt);
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exit:
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starfive_wdt_lock(wdt);
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return ret;
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}
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static int starfive_wdt_stop(struct udevice *dev)
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{
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struct starfive_wdt_priv *wdt = dev_get_priv(dev);
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starfive_wdt_unlock(wdt);
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starfive_wdt_disable(wdt);
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starfive_wdt_lock(wdt);
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return 0;
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}
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static int starfive_wdt_reset(struct udevice *dev)
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{
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int ret;
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struct starfive_wdt_priv *wdt = dev_get_priv(dev);
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starfive_wdt_unlock(wdt);
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ret = starfive_wdt_int_clr(wdt);
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if (ret)
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goto exit;
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starfive_wdt_set_reload_count(wdt, wdt->count);
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exit:
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starfive_wdt_lock(wdt);
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return ret;
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}
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static const struct wdt_ops starfive_wdt_ops = {
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.start = starfive_wdt_start,
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.stop = starfive_wdt_stop,
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.reset = starfive_wdt_reset,
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};
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static int starfive_wdt_probe(struct udevice *dev)
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{
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struct starfive_wdt_priv *wdt = dev_get_priv(dev);
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int ret;
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ret = starfive_wdt_enable_clock(wdt);
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if (ret)
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return ret;
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ret = reset_deassert_bulk(wdt->rst);
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if (ret)
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goto err_reset;
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wdt->variant = (const struct starfive_wdt_variant *)dev_get_driver_data(dev);
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wdt->freq = clk_get_rate(wdt->core_clk);
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if (!wdt->freq) {
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ret = -EINVAL;
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goto err_get_freq;
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}
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return 0;
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err_get_freq:
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reset_assert_bulk(wdt->rst);
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err_reset:
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starfive_wdt_disable_clock(wdt);
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return ret;
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}
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static int starfive_wdt_of_to_plat(struct udevice *dev)
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{
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struct starfive_wdt_priv *wdt = dev_get_priv(dev);
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wdt->base = (void *)dev_read_addr(dev);
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if (!wdt->base)
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return -ENODEV;
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wdt->apb_clk = devm_clk_get(dev, "apb");
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if (IS_ERR(wdt->apb_clk))
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return -ENODEV;
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wdt->core_clk = devm_clk_get(dev, "core");
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if (IS_ERR(wdt->core_clk))
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return -ENODEV;
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wdt->rst = devm_reset_bulk_get(dev);
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if (IS_ERR(wdt->rst))
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return -ENODEV;
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return 0;
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}
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static const struct udevice_id starfive_wdt_ids[] = {
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{
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.compatible = "starfive,jh7110-wdt",
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.data = (ulong)&starfive_wdt_jh7110_variant
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}, {
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/* sentinel */
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}
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};
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U_BOOT_DRIVER(starfive_wdt) = {
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.name = "starfive_wdt",
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.id = UCLASS_WDT,
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.of_match = starfive_wdt_ids,
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.priv_auto = sizeof(struct starfive_wdt_priv),
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.probe = starfive_wdt_probe,
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.of_to_plat = starfive_wdt_of_to_plat,
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.ops = &starfive_wdt_ops,
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};
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