Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-13 08:27:23 +00:00
Code Issues Projects Releases Packages Wiki Activity

ppc4xx: Fix problem in 44x cache POST routine

Browse source 
As repoted by Larry Johnson, running "diag run cache" caused a crash
in U-Boot. This problem was introduced by a patch that removed the
TLB entry for the cache test after the test has completed. Since this
TLB was only setup once, a 2nd attempt to run this cache test
failed with a crash. Now this TLB entry is created every time the
routine is called.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-12-22 12:18:26 +01:00
parent b0265b576b
commit d91722102c
1 changed files with 18 additions and 21 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

39
post/cpu/ppc4xx/cache.c
View file

@ -51,8 +51,6 @@ int cache_post_test4 (int tlb, void *p, int size);
int cache_post_test5 (int tlb, void *p, int size); int cache_post_test5 (int tlb, void *p, int size);
int cache_post_test6 (int tlb, void *p, int size); int cache_post_test6 (int tlb, void *p, int size);
static int tlb = -1; /* index to the victim TLB entry */
#ifdef CONFIG_440 #ifdef CONFIG_440
static unsigned char testarea[CACHE_POST_SIZE] static unsigned char testarea[CACHE_POST_SIZE]
__attribute__((__aligned__(CACHE_POST_SIZE))); __attribute__((__aligned__(CACHE_POST_SIZE)));
@ -60,7 +58,7 @@ __attribute__((__aligned__(CACHE_POST_SIZE)));
int cache_post_test (int flags) int cache_post_test (int flags)
{ {
void* virt = (void*)CFG_POST_CACHE_ADDR; void *virt = (void *)CFG_POST_CACHE_ADDR;
int ints; int ints;
int res = 0; int res = 0;
@ -72,26 +70,25 @@ int cache_post_test (int flags)
*/ */
#ifdef CONFIG_440 #ifdef CONFIG_440
int word0, i; int word0, i;
int tlb; /* index to the victim TLB entry */
if (tlb < 0) { /*
/* * Allocate a new TLB entry, since we are going to modify
* Allocate a new TLB entry, since we are going to modify * the write-through and caching inhibited storage attributes.
* the write-through and caching inhibited storage attributes. */
*/ program_tlb((u32)testarea, (u32)virt, CACHE_POST_SIZE,
program_tlb((u32)testarea, (u32)virt, TLB_WORD2_I_ENABLE);
CACHE_POST_SIZE, TLB_WORD2_I_ENABLE);
/* Find the TLB entry */ /* Find the TLB entry */
for (i = 0;; i++) { for (i = 0;; i++) {
if (i >= PPC4XX_TLB_SIZE) { if (i >= PPC4XX_TLB_SIZE) {
printf ("Failed to program tlb entry\n"); printf ("Failed to program tlb entry\n");
return -1; return -1;
} }
word0 = mftlb1(i); word0 = mftlb1(i);
if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) { if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) {
tlb = i; tlb = i;
break; break;
}
} }
} }
#endif #endif