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ppc4xx: Cleanup Katmai & Yucca PCIe register usage

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This patch cleans up the 440SPe PCIe register usage. Now only defines
from the include/asm-ppc/4xx_pcie.h are used.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2008-06-30 14:05:05 +02:00
parent 5de851403b
commit d9056b7913
3 changed files with 8 additions and 127 deletions
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72
board/amcc/katmai/katmai.c
View file

@ -349,7 +349,7 @@ int is_pci_host(struct pci_controller *hose)
return 1; return 1;
} }
int katmai_pcie_card_present(int port) static int katmai_pcie_card_present(int port)
{ {
u32 val; u32 val;
@ -437,76 +437,6 @@ void pcie_setup_hoses(int busno)
} }
#endif /* defined(CONFIG_PCI) */ #endif /* defined(CONFIG_PCI) */
int misc_init_f (void)
{
uint reg;
#if defined(CONFIG_STRESS)
uint i ;
uint disp;
#endif
/* minimal init for PCIe */
#if 0 /* test-only: test endpoint at some time, for now rootpoint only */
/* pci express 0 Endpoint Mode */
mfsdr(SDR0_PE0DLPSET, reg);
reg &= (~0x00400000);
mtsdr(SDR0_PE0DLPSET, reg);
#else
/* pci express 0 Rootpoint Mode */
mfsdr(SDR0_PE0DLPSET, reg);
reg |= 0x00400000;
mtsdr(SDR0_PE0DLPSET, reg);
#endif
/* pci express 1 Rootpoint Mode */
mfsdr(SDR0_PE1DLPSET, reg);
reg |= 0x00400000;
mtsdr(SDR0_PE1DLPSET, reg);
/* pci express 2 Rootpoint Mode */
mfsdr(SDR0_PE2DLPSET, reg);
reg |= 0x00400000;
mtsdr(SDR0_PE2DLPSET, reg);
#if defined(CONFIG_STRESS)
/*
* All this setting done by linux only needed by stress an charac. test
* procedure
* PCIe 1 Rootpoint PCIe2 Endpoint
* PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level
*/
for (i=0,disp=0; i<8; i++,disp+=3) {
mfsdr(SDR0_PE0HSSSET1L0+disp, reg);
reg |= 0x33000000;
mtsdr(SDR0_PE0HSSSET1L0+disp, reg);
}
/*PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
for (i=0,disp=0; i<4; i++,disp+=3) {
mfsdr(SDR0_PE1HSSSET1L0+disp, reg);
reg |= 0x33000000;
mtsdr(SDR0_PE1HSSSET1L0+disp, reg);
}
/*PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */
for (i=0,disp=0; i<4; i++,disp+=3) {
mfsdr(SDR0_PE2HSSSET1L0+disp, reg);
reg |= 0x33000000;
mtsdr(SDR0_PE2HSSSET1L0+disp, reg);
}
reg = 0x21242222;
mtsdr(SDR0_PE2UTLSET1, reg);
reg = 0x11000000;
mtsdr(SDR0_PE2UTLSET2, reg);
/* pci express 1 Endpoint Mode */
reg = 0x00004000;
mtsdr(SDR0_PE2DLPSET, reg);
mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
#endif
return 0;
}
#ifdef CONFIG_POST #ifdef CONFIG_POST
/* /*
* Returns 1 if keys pressed to start the power-on long-running tests * Returns 1 if keys pressed to start the power-on long-running tests

62
board/amcc/yucca/yucca.c
View file

@ -677,7 +677,7 @@ int is_pci_host(struct pci_controller *hose)
return 1; return 1;
} }
int yucca_pcie_card_present(int port) static int yucca_pcie_card_present(int port)
{ {
u16 reg; u16 reg;
@ -879,10 +879,6 @@ void pcie_setup_hoses(int busno)
int misc_init_f (void) int misc_init_f (void)
{ {
uint reg; uint reg;
#if defined(CONFIG_STRESS)
uint i ;
uint disp;
#endif
out16(FPGA_REG10, (in16(FPGA_REG10) & out16(FPGA_REG10, (in16(FPGA_REG10) &
~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) | ~(FPGA_REG10_AUTO_NEG_DIS|FPGA_REG10_RESET_ETH)) |
@ -897,67 +893,23 @@ int misc_init_f (void)
/* minimal init for PCIe */ /* minimal init for PCIe */
/* pci express 0 Endpoint Mode */ /* pci express 0 Endpoint Mode */
mfsdr(SDR0_PE0DLPSET, reg); mfsdr(SDRN_PESDR_DLPSET(0), reg);
reg &= (~0x00400000); reg &= (~0x00400000);
mtsdr(SDR0_PE0DLPSET, reg); mtsdr(SDRN_PESDR_DLPSET(0), reg);
/* pci express 1 Rootpoint Mode */ /* pci express 1 Rootpoint Mode */
mfsdr(SDR0_PE1DLPSET, reg); mfsdr(SDRN_PESDR_DLPSET(1), reg);
reg |= 0x00400000; reg |= 0x00400000;
mtsdr(SDR0_PE1DLPSET, reg); mtsdr(SDRN_PESDR_DLPSET(1), reg);
/* pci express 2 Rootpoint Mode */ /* pci express 2 Rootpoint Mode */
mfsdr(SDR0_PE2DLPSET, reg); mfsdr(SDRN_PESDR_DLPSET(2), reg);
reg |= 0x00400000; reg |= 0x00400000;
mtsdr(SDR0_PE2DLPSET, reg); mtsdr(SDRN_PESDR_DLPSET(2), reg);
out16(FPGA_REG1C,(in16 (FPGA_REG1C) & out16(FPGA_REG1C,(in16 (FPGA_REG1C) &
~FPGA_REG1C_PE0_ROOTPOINT & ~FPGA_REG1C_PE0_ROOTPOINT &
~FPGA_REG1C_PE1_ENDPOINT & ~FPGA_REG1C_PE1_ENDPOINT &
~FPGA_REG1C_PE2_ENDPOINT)); ~FPGA_REG1C_PE2_ENDPOINT));
#if defined(CONFIG_STRESS)
/*
* all this setting done by linux only needed by stress an charac. test
* procedure
* PCIe 1 Rootpoint PCIe2 Endpoint
* PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver
* Power Level
*/
for (i = 0, disp = 0; i < 8; i++, disp += 3) {
mfsdr(SDR0_PE0HSSSET1L0 + disp, reg);
reg |= 0x33000000;
mtsdr(SDR0_PE0HSSSET1L0 + disp, reg);
}
/*
* PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver
* Power Level
*/
for (i = 0, disp = 0; i < 4; i++, disp += 3) {
mfsdr(SDR0_PE1HSSSET1L0 + disp, reg);
reg |= 0x33000000;
mtsdr(SDR0_PE1HSSSET1L0 + disp, reg);
}
/*
* PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver
* Power Level
*/
for (i = 0, disp = 0; i < 4; i++, disp += 3) {
mfsdr(SDR0_PE2HSSSET1L0 + disp, reg);
reg |= 0x33000000;
mtsdr(SDR0_PE2HSSSET1L0 + disp, reg);
}
reg = 0x21242222;
mtsdr(SDR0_PE2UTLSET1, reg);
reg = 0x11000000;
mtsdr(SDR0_PE2UTLSET2, reg);
/* pci express 1 Endpoint Mode */
reg = 0x00004000;
mtsdr(SDR0_PE2DLPSET, reg);
mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */
#endif
return 0; return 0;
} }

1
include/configs/katmai.h
View file

@ -54,7 +54,6 @@
#include "amcc-common.h" #include "amcc-common.h"
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
#undef CONFIG_SHOW_BOOT_PROGRESS #undef CONFIG_SHOW_BOOT_PROGRESS
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------