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fsl_sec: fix register layout on Layerscape architectures

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On Layerscape architectures the SEC memory map is 1MB and the
register blocks contained in it are 64KB aligned, not 4KB as
the ccsr_sec structure currently assumes. Fix the layout of
the structure for these architectures.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reviewed-by: Horia Geanta <horia.geanta@nxp.com>
Reviewed-by: Bharat Bhushan <bharat.bhushan@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Laurentiu Tudor 2019-02-26 13:18:32 +02:00 committed by Prabhakar Kushwaha
parent 910e8fdaac
commit d8d5fdb7b2
1 changed files with 8 additions and 0 deletions
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8
include/fsl_sec.h
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@ -121,10 +121,18 @@ typedef struct ccsr_sec {
u32 chanum_ls; /* CHA Number Register, LS */
u32 secvid_ms; /* SEC Version ID Register, MS */
u32 secvid_ls; /* SEC Version ID Register, LS */
#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
u8 res9[0x6f020];
#else
u8 res9[0x6020];
#endif
u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
u8 res10[0x8ffd8];
#else
u8 res10[0x8fd8];
#endif
} ccsr_sec_t;
#define SEC_CTPR_MS_AXI_LIODN 0x08000000