mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 06:00:43 +00:00
M68K: eb_cpu5282: general update and enhanced board support
- update clock settings for higher perfomance - change standard baud rate to 115200 - fix flash base address - remove unused defines - add I2C support - switch form board dependent flash to cfi - remove board dependent flash code - use sdram bank 0 instead of bank 1 on boot - enable on board frame buffer instead external - remove fake mac address form config - add watchdog support - add status led support Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de> [agust: fixed small style issues and build warning] Signed-off-by: Anatolij Gustschin <agust@denx.de>
This commit is contained in:
Jens Scharsig (BuS Elektronik)
Anatolij Gustschin
parent
f5a7004cf7
commit
d858c335bf
8 changed files with 146 additions and 764 deletions
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@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS = $(BOARD).o cfm_flash.o flash.o
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COBJS = $(BOARD).o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -1,212 +0,0 @@
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/*
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* Basic Flash Driver for Freescale MCF 5281/5282 internal FLASH
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*
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* (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/m5282.h>
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#include "cfm_flash.h"
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#if defined(CONFIG_M5281) || defined(CONFIG_M5282)
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#if (CONFIG_SYS_CLK>20000000)
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#define CFM_CLK (((long) CONFIG_SYS_CLK / (400000 * 8) + 1) | 0x40)
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#else
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#define CFM_CLK ((long) CONFIG_SYS_CLK / 400000 + 1)
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#endif
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#define cmf_backdoor_address(addr) (((addr) & 0x0007FFFF) | 0x04000000 | \
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(CONFIG_SYS_MBAR & 0xC0000000))
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void cfm_flash_print_info (flash_info_t * info)
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{
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printf ("Freescale: ");
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switch (info->flash_id & FLASH_TYPEMASK) {
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case FREESCALE_ID_MCF5281 & FLASH_TYPEMASK:
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printf ("MCF5281 internal FLASH\n");
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break;
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case FREESCALE_ID_MCF5282 & FLASH_TYPEMASK:
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printf ("MCF5282 internal FLASH\n");
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break;
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default:
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printf ("Unknown Chip Type\n");
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break;
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}
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}
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void cfm_flash_init (flash_info_t * info)
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{
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int sector;
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ulong protection;
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MCFCFM_MCR = 0;
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MCFCFM_CLKD = CFM_CLK;
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debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\
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CONFIG_SYS_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
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CONFIG_SYS_CLK);
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MCFCFM_SACC = 0;
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MCFCFM_DACC = 0;
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if (MCFCFM_SEC & MCFCFM_SEC_KEYEN)
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puts("CFM backdoor access is enabled\n");
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if (MCFCFM_SEC & MCFCFM_SEC_SECSTAT)
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puts("CFM securety is enabled\n");
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#ifdef CONFIG_M5281
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info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) |
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(FREESCALE_ID_MCF5281 & FLASH_TYPEMASK);
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info->size = 256*1024;
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info->sector_count = 16;
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#else
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info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) |
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(FREESCALE_ID_MCF5282 & FLASH_TYPEMASK);
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info->size = 512*1024;
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info->sector_count = 32;
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#endif
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protection = MCFCFM_PROT;
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for (sector = 0; sector < info->sector_count; sector++)
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{
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if (sector == 0)
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{
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info->start[sector] = CONFIG_SYS_INT_FLASH_BASE;
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}
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else
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{
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info->start[sector] = info->start[sector-1] + 0x04000;
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}
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info->protect[sector] = protection & 1;
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protection >>= 1;
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}
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}
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int cfm_flash_readycheck(int checkblank)
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{
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int rc;
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unsigned char state;
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rc = ERR_OK;
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while (!(MCFCFM_USTAT & MCFCFM_USTAT_CCIF));
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state = MCFCFM_USTAT;
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if (state & MCFCFM_USTAT_ACCERR)
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{
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debug ("%s(): CFM access error",__FUNCTION__);
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rc = ERR_PROG_ERROR;
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}
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if (state & MCFCFM_USTAT_PVIOL)
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{
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debug ("%s(): CFM protection violation",__FUNCTION__);
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rc = ERR_PROTECTED;
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}
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if (checkblank)
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{
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if (!(state & MCFCFM_USTAT_BLANK))
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{
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debug ("%s(): CFM erras error",__FUNCTION__);
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rc = ERR_NOT_ERASED;
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}
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}
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MCFCFM_USTAT = state & 0x34; /* reset state */
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return rc;
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}
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/* Erase 16KiB = 8 2KiB pages */
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int cfm_flash_erase_sector (flash_info_t * info, int sector)
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{
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ulong address;
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int page;
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int rc;
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rc= ERR_OK;
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address = cmf_backdoor_address(info->start[sector]);
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for (page=0; (page<8) && (rc==ERR_OK); page++)
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{
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*(volatile __u32*) address = 0;
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MCFCFM_CMD = MCFCFM_CMD_PGERS;
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MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
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rc = cfm_flash_readycheck(0);
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if (rc==ERR_OK)
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{
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*(volatile __u32*) address = 0;
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MCFCFM_CMD = MCFCFM_CMD_PGERSVER;
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MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
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rc = cfm_flash_readycheck(1);
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}
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address += 0x800;
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}
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return rc;
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}
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int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
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{
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int rc;
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ulong dest, data;
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rc = ERR_OK;
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if (addr & 3)
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{
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debug ("Byte and Word alignment not supported\n");
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rc = ERR_ALIGN;
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}
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if (cnt & 3)
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{
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debug ("Byte and Word transfer not supported\n");
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rc = ERR_ALIGN;
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}
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dest = cmf_backdoor_address(addr);
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while ((cnt>=4) && (rc == ERR_OK))
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{
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data = *((volatile u32 *) src);
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*(volatile u32*) dest = data;
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MCFCFM_CMD = MCFCFM_CMD_PGM;
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MCFCFM_USTAT = MCFCFM_USTAT_CBEIF;
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rc = cfm_flash_readycheck(0);
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if (*(volatile u32*) addr != data) rc = ERR_PROG_ERROR;
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src +=4;
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dest +=4;
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addr +=4;
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cnt -=4;
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}
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return rc;
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}
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#ifdef CONFIG_SYS_FLASH_PROTECTION
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int cfm_flash_protect(flash_info_t * info,long sector,int prot)
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{
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int rc;
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rc= ERR_OK;
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if (prot)
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{
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MCFCFM_PROT |= (1<<sector);
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info->protect[sector]=1;
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}
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else
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{
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MCFCFM_PROT &= ~(1<<sector);
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info->protect[sector]=0;
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}
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return rc;
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}
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#endif
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#endif
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@ -1,40 +0,0 @@
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/*
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* Basic Flash Driver for Freescale MCF 5282 internal FLASH
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*
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* (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __CFM_FLASH_H_
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#define __CFM_FLASH_H_
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#define FREESCALE_MANUFACT 0xFACFFACF
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#define FREESCALE_ID_MCF5281 0x5281
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#define FREESCALE_ID_MCF5282 0x5282
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extern void cfm_flash_print_info (flash_info_t * info);
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extern int cfm_flash_erase_sector (flash_info_t * info, int sector);
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extern void cfm_flash_init (flash_info_t * info);
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extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
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#ifdef CONFIG_SYS_FLASH_PROTECTION
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extern int cfm_flash_protect(flash_info_t * info,long sector,int prot);
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#endif
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#endif
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@ -1,27 +0,0 @@
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#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com>
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
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# published by the Free Software Foundation; either version 2 of
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# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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ifndef CONFIG_SYS_TEXT_BASE
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CONFIG_SYS_TEXT_BASE = 0xFE000000
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endif
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@ -35,18 +35,19 @@
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_VIDEO
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unsigned long display_width;
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unsigned long display_height;
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#endif
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/*---------------------------------------------------------------------------*/
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int checkboard (void)
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{
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puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
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puts("Board: EB+CPU5282 (BuS Elektronik GmbH & Co. KG)\n");
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#if (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE)
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puts (" Boot from Internal FLASH\n");
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puts(" Boot from Internal FLASH\n");
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#endif
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return 0;
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}
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@ -55,29 +56,39 @@ phys_size_t initdram (int board_type)
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int size, i;
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size = 0;
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MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6
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| MCFSDRAMC_DCR_RC ((15 * CONFIG_SYS_CLK) >> 4);
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MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 |
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MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4);
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asm (" nop");
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#ifdef CONFIG_SYS_SDRAM_BASE0
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MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE0)
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| MCFSDRAMC_DACR_CASL (1)
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| MCFSDRAMC_DACR_CBM (3)
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| MCFSDRAMC_DACR_PS_16;
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MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE0)|
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MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) |
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MCFSDRAMC_DACR_PS_32;
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asm (" nop");
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MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V;
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asm (" nop");
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MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
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asm (" nop");
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for (i = 0; i < 10; i++)
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asm (" nop");
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*(unsigned short *) (CONFIG_SYS_SDRAM_BASE0) = 0xA5A5;
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*(unsigned long *)(CONFIG_SYS_SDRAM_BASE0) = 0xA5A5A5A5;
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asm (" nop");
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MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
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asm (" nop");
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for (i = 0; i < 2000; i++)
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asm (" nop");
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mbar_writeLong (MCFSDRAMC_DACR0,
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mbar_readLong (MCFSDRAMC_DACR0) | MCFSDRAMC_DACR_IMRS);
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*(unsigned int *) (CONFIG_SYS_SDRAM_BASE0 + 0x220) = 0xA5A5;
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size += CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
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asm (" nop");
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/* write SDRAM mode register */
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*(unsigned long *)(CONFIG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5;
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asm (" nop");
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size += CONFIG_SYS_SDRAM_SIZE0 * 1024 * 1024;
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#endif
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#ifdef CONFIG_SYS_SDRAM_BASE1
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#ifdef CONFIG_SYS_SDRAM_BASE1xx
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MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
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| MCFSDRAMC_DACR_CASL (1)
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| MCFSDRAMC_DACR_CBM (3)
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@ -134,38 +145,74 @@ int testdram (void)
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}
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#endif
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#if defined(CONFIG_HW_WATCHDOG)
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void hw_watchdog_init(void)
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{
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char *s;
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int enable;
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enable = 1;
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s = getenv("watchdog");
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if (s != NULL)
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if ((strncmp(s, "off", 3) == 0) || (strncmp(s, "0", 1) == 0))
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enable = 0;
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if (enable)
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MCFGPTA_GPTDDR |= (1<<2);
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else
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MCFGPTA_GPTDDR &= ~(1<<2);
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}
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void hw_watchdog_reset(void)
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{
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MCFGPTA_GPTPORT ^= (1<<2);
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}
|
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#endif
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|
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int misc_init_r(void)
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{
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#ifdef CONFIG_HW_WATCHDOG
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hw_watchdog_init();
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#endif
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#ifndef CONFIG_VIDEO
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vcxk_init(16, 16);
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#endif
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return 1;
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}
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void __led_toggle(led_id_t mask)
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{
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MCFGPTA_GPTPORT ^= (1 << 3);
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}
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|
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void __led_init(led_id_t mask, int state)
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{
|
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__led_set(mask, state);
|
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MCFGPTA_GPTDDR |= (1 << 3);
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}
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|
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void __led_set(led_id_t mask, int state)
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{
|
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if (state == STATUS_LED_ON)
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MCFGPTA_GPTPORT |= (1 << 3);
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else
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MCFGPTA_GPTPORT &= ~(1 << 3);
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}
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|
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#if defined(CONFIG_VIDEO)
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/*
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****h* EB+CPU5282-T1/drv_video_init
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* FUNCTION
|
||||
***
|
||||
*/
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|
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int drv_video_init(void)
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{
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||||
char *s;
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||||
#ifdef CONFIG_SPLASH_SCREEN
|
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unsigned long splash;
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#endif
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printf("Init Video as ");
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if ((s = getenv("displaywidth")) != NULL)
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s = getenv("displaywidth");
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if (s != NULL)
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display_width = simple_strtoul(s, NULL, 10);
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else
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display_width = 256;
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||||
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if ((s = getenv("displayheight")) != NULL)
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s = getenv("displayheight");
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if (s != NULL)
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display_height = simple_strtoul(s, NULL, 10);
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else
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display_height = 256;
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|
|
@ -178,10 +225,9 @@ int drv_video_init(void)
|
|||
vcxk_init(display_width, display_height);
|
||||
|
||||
#ifdef CONFIG_SPLASH_SCREEN
|
||||
if ((s = getenv("splashimage")) != NULL) {
|
||||
debug("use splashimage: %s\n", s);
|
||||
s = getenv("splashimage");
|
||||
if (s != NULL) {
|
||||
splash = simple_strtoul(s, NULL, 16);
|
||||
debug("use splashimage: %x\n", splash);
|
||||
vcxk_acknowledge_wait();
|
||||
video_display_bitmap(splash, 0, 0);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,415 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2005
|
||||
* BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de>
|
||||
*
|
||||
* Based On
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include "cfm_flash.h"
|
||||
|
||||
#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
|
||||
#define FLASH_BANK_SIZE 0x200000
|
||||
|
||||
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
|
||||
|
||||
void flash_print_info (flash_info_t * info)
|
||||
{
|
||||
int i;
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK) {
|
||||
case (AMD_MANUFACT & FLASH_VENDMASK):
|
||||
printf ("AMD: ");
|
||||
switch (info->flash_id & FLASH_TYPEMASK) {
|
||||
case (AMD_ID_LV160B & FLASH_TYPEMASK):
|
||||
printf ("AM29LV160B (16Bit)\n");
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Chip Type\n");
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case FREESCALE_MANUFACT & FLASH_VENDMASK:
|
||||
cfm_flash_print_info (info);
|
||||
break;
|
||||
default:
|
||||
printf ("Unknown Vendor ");
|
||||
break;
|
||||
}
|
||||
|
||||
puts (" Size: ");
|
||||
if ((info->size >> 20) > 0)
|
||||
{
|
||||
printf ("%ld MiB",info->size >> 20);
|
||||
}
|
||||
else
|
||||
{
|
||||
printf ("%ld KiB",info->size >> 10);
|
||||
}
|
||||
printf (" in %d Sectors\n", info->sector_count);
|
||||
|
||||
printf (" Sector Start Addresses:");
|
||||
for (i = 0; i < info->sector_count; i++) {
|
||||
if ((i % 4) == 0) {
|
||||
printf ("\n ");
|
||||
}
|
||||
printf ("%02d: %08lX%s ", i,info->start[i],
|
||||
info->protect[i] ? " P" : " ");
|
||||
}
|
||||
printf ("\n\n");
|
||||
}
|
||||
|
||||
unsigned long flash_init (void)
|
||||
{
|
||||
int i, j;
|
||||
ulong size = 0;
|
||||
|
||||
for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
|
||||
ulong flashbase = 0;
|
||||
|
||||
switch (i)
|
||||
{
|
||||
case 1:
|
||||
flash_info[i].flash_id =
|
||||
(AMD_MANUFACT & FLASH_VENDMASK) |
|
||||
(AMD_ID_LV160B & FLASH_TYPEMASK);
|
||||
flash_info[i].size = FLASH_BANK_SIZE;
|
||||
flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
|
||||
memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
|
||||
flashbase = PHYS_FLASH_1;
|
||||
for (j = 0; j < flash_info[i].sector_count; j++) {
|
||||
if (j == 0) {
|
||||
/* 1st is 16 KiB */
|
||||
flash_info[i].start[j] = flashbase;
|
||||
}
|
||||
if ((j >= 1) && (j <= 2)) {
|
||||
/* 2nd and 3rd are 8 KiB */
|
||||
flash_info[i].start[j] =
|
||||
flashbase + 0x4000 + 0x2000 * (j - 1);
|
||||
}
|
||||
if (j == 3) {
|
||||
/* 4th is 32 KiB */
|
||||
flash_info[i].start[j] = flashbase + 0x8000;
|
||||
}
|
||||
if ((j >= 4) && (j <= 34)) {
|
||||
/* rest is 256 KiB */
|
||||
flash_info[i].start[j] =
|
||||
flashbase + 0x10000 + 0x10000 * (j - 4);
|
||||
}
|
||||
}
|
||||
break;
|
||||
case 0:
|
||||
cfm_flash_init (&flash_info[i]);
|
||||
break;
|
||||
default:
|
||||
panic ("configured to many flash banks!\n");
|
||||
}
|
||||
|
||||
size += flash_info[i].size;
|
||||
}
|
||||
|
||||
flash_protect (FLAG_PROTECT_SET,
|
||||
CONFIG_SYS_FLASH_BASE,
|
||||
CONFIG_SYS_FLASH_BASE + 0xffff, &flash_info[0]);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
#define CMD_READ_ARRAY 0x00F0
|
||||
#define CMD_UNLOCK1 0x00AA
|
||||
#define CMD_UNLOCK2 0x0055
|
||||
#define CMD_ERASE_SETUP 0x0080
|
||||
#define CMD_ERASE_CONFIRM 0x0030
|
||||
#define CMD_PROGRAM 0x00A0
|
||||
#define CMD_UNLOCK_BYPASS 0x0020
|
||||
|
||||
#define MEM_FLASH_ADDR1 (*(volatile u16 *)(info->start[0] + (0x00000555<<1)))
|
||||
#define MEM_FLASH_ADDR2 (*(volatile u16 *)(info->start[0] + (0x000002AA<<1)))
|
||||
|
||||
|
||||
#define BIT_ERASE_DONE 0x0080
|
||||
#define BIT_RDY_MASK 0x0080
|
||||
#define BIT_PROGRAM_ERROR 0x0020
|
||||
#define BIT_TIMEOUT 0x80000000 /* our flag */
|
||||
|
||||
#define ERR_READY -1
|
||||
|
||||
int amd_flash_erase_sector(flash_info_t * info, int sector)
|
||||
{
|
||||
int state;
|
||||
ulong result;
|
||||
ulong start;
|
||||
|
||||
volatile u16 *addr =
|
||||
(volatile u16 *) (info->start[sector]);
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
*addr = CMD_ERASE_CONFIRM;
|
||||
|
||||
/* wait until flash is ready */
|
||||
state = 0;
|
||||
start = get_timer(0);
|
||||
|
||||
do {
|
||||
result = *addr;
|
||||
|
||||
/* check timeout */
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
|
||||
state = ERR_TIMOUT;
|
||||
}
|
||||
|
||||
if (!state && (result & 0xFFFF) & BIT_ERASE_DONE)
|
||||
state = ERR_READY;
|
||||
}
|
||||
while (!state);
|
||||
if (state == ERR_READY)
|
||||
state = ERR_OK;
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
int flash_erase (flash_info_t * info, int s_first, int s_last)
|
||||
{
|
||||
int iflag, cflag;
|
||||
int sector;
|
||||
int rc;
|
||||
|
||||
rc = ERR_OK;
|
||||
|
||||
if (info->flash_id == FLASH_UNKNOWN)
|
||||
{
|
||||
rc = ERR_UNKNOWN_FLASH_TYPE;
|
||||
} /* (info->flash_id == FLASH_UNKNOWN) */
|
||||
|
||||
if ((s_first < 0) || (s_first > s_last) || s_last >= info->sector_count)
|
||||
{
|
||||
rc = ERR_INVAL;
|
||||
}
|
||||
|
||||
cflag = icache_status ();
|
||||
icache_disable ();
|
||||
iflag = disable_interrupts ();
|
||||
|
||||
for (sector = s_first; (sector <= s_last) && (rc == ERR_OK); sector++) {
|
||||
|
||||
if (info->protect[sector])
|
||||
{
|
||||
putc('P'); /* protected sector will not erase */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* erase on unprotected sector */
|
||||
puts("E\b");
|
||||
switch (info->flash_id & FLASH_VENDMASK)
|
||||
{
|
||||
case (AMD_MANUFACT & FLASH_VENDMASK):
|
||||
rc = amd_flash_erase_sector(info,sector);
|
||||
break;
|
||||
case (FREESCALE_MANUFACT & FLASH_VENDMASK):
|
||||
rc = cfm_flash_erase_sector(info,sector);
|
||||
break;
|
||||
default:
|
||||
return ERR_UNKNOWN_FLASH_VENDOR;
|
||||
}
|
||||
putc('.');
|
||||
}
|
||||
}
|
||||
if (rc!=ERR_OK)
|
||||
{
|
||||
printf ("\n ");
|
||||
flash_perror (rc);
|
||||
}
|
||||
else
|
||||
{
|
||||
printf (" done\n");
|
||||
}
|
||||
|
||||
udelay (10000); /* allow flash to settle - wait 10 ms */
|
||||
|
||||
if (iflag)
|
||||
enable_interrupts ();
|
||||
|
||||
if (cflag)
|
||||
icache_enable ();
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data)
|
||||
{
|
||||
volatile u16 *addr;
|
||||
ulong result;
|
||||
int cflag, iflag;
|
||||
int state;
|
||||
ulong start;
|
||||
|
||||
/*
|
||||
* Check if Flash is (sufficiently) erased
|
||||
*/
|
||||
addr = (volatile u16 *) dest;
|
||||
|
||||
result = *addr;
|
||||
if ((result & data) != data)
|
||||
return ERR_NOT_ERASED;
|
||||
|
||||
/*
|
||||
* Disable interrupts which might cause a timeout
|
||||
* here. Remember that our exception vectors are
|
||||
* at address 0 in the flash, and we don't want a
|
||||
* (ticker) exception to happen while the flash
|
||||
* chip is in programming mode.
|
||||
*/
|
||||
|
||||
cflag = icache_status ();
|
||||
icache_disable ();
|
||||
iflag = disable_interrupts ();
|
||||
|
||||
MEM_FLASH_ADDR1 = CMD_UNLOCK1;
|
||||
MEM_FLASH_ADDR2 = CMD_UNLOCK2;
|
||||
MEM_FLASH_ADDR1 = CMD_PROGRAM;
|
||||
*addr = data;
|
||||
|
||||
/* arm simple, non interrupt dependent timer */
|
||||
start = get_timer(0);
|
||||
|
||||
/* wait until flash is ready */
|
||||
state = 0;
|
||||
do {
|
||||
result = *addr;
|
||||
|
||||
/* check timeout */
|
||||
if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
|
||||
state = ERR_TIMOUT;
|
||||
}
|
||||
if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK)))
|
||||
state = ERR_READY;
|
||||
|
||||
} while (!state);
|
||||
|
||||
*addr = CMD_READ_ARRAY;
|
||||
|
||||
if (state == ERR_READY)
|
||||
state = ERR_OK;
|
||||
if ((*addr != data) && (state != ERR_TIMOUT))
|
||||
state = ERR_PROG_ERROR;
|
||||
|
||||
if (iflag)
|
||||
enable_interrupts ();
|
||||
|
||||
if (cflag)
|
||||
icache_enable ();
|
||||
|
||||
return state;
|
||||
}
|
||||
|
||||
int amd_flash_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
int rc;
|
||||
ulong dest;
|
||||
u16 data;
|
||||
|
||||
rc = ERR_OK;
|
||||
if (addr & 1)
|
||||
{
|
||||
debug ("Byte alignment not supported\n");
|
||||
rc = ERR_ALIGN;
|
||||
}
|
||||
if (cnt & 1)
|
||||
{
|
||||
debug ("Byte transfer not supported\n");
|
||||
rc = ERR_ALIGN;
|
||||
}
|
||||
|
||||
dest = addr;
|
||||
while ((cnt>=2) && (rc == ERR_OK))
|
||||
{
|
||||
data = *((volatile u16 *) src);
|
||||
rc=amd_write_word (info,dest,data);
|
||||
src +=2;
|
||||
dest +=2;
|
||||
cnt -=2;
|
||||
}
|
||||
return rc;
|
||||
}
|
||||
|
||||
int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
|
||||
{
|
||||
int rc;
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK)
|
||||
{
|
||||
case (AMD_MANUFACT & FLASH_VENDMASK):
|
||||
rc = amd_flash_write_buff(info,src,addr,cnt);
|
||||
break;
|
||||
case (FREESCALE_MANUFACT & FLASH_VENDMASK):
|
||||
rc = cfm_flash_write_buff(info,src,addr,cnt);
|
||||
break;
|
||||
default:
|
||||
rc = ERR_UNKNOWN_FLASH_VENDOR;
|
||||
}
|
||||
return rc;
|
||||
|
||||
}
|
||||
int amd_flash_protect(flash_info_t * info,long sector,int prot)
|
||||
{
|
||||
int rc;
|
||||
rc= ERR_OK;
|
||||
if (prot)
|
||||
{
|
||||
info->protect[sector]=1;
|
||||
}
|
||||
else
|
||||
{
|
||||
info->protect[sector]=0;
|
||||
}
|
||||
return rc;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SYS_FLASH_PROTECTION
|
||||
|
||||
int flash_real_protect(flash_info_t * info,long sector,int prot)
|
||||
{
|
||||
int rc;
|
||||
|
||||
switch (info->flash_id & FLASH_VENDMASK)
|
||||
{
|
||||
case (AMD_MANUFACT & FLASH_VENDMASK):
|
||||
rc = amd_flash_protect(info,sector,prot);
|
||||
break;
|
||||
case (FREESCALE_MANUFACT & FLASH_VENDMASK):
|
||||
rc = cfm_flash_protect(info,sector,prot);
|
||||
break;
|
||||
default:
|
||||
rc = ERR_UNKNOWN_FLASH_VENDOR;
|
||||
}
|
||||
return rc;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -372,7 +372,7 @@ M5235EVB m68k mcf523x m5235evb freesca
|
|||
M5235EVB_Flash32 m68k mcf523x m5235evb freescale - M5235EVB:NORFLASH_PS32BIT,SYS_TEXT_BASE=0xFFC00000
|
||||
cobra5272 m68k mcf52x2 cobra5272 -
|
||||
idmr m68k mcf52x2
|
||||
eb_cpu5282 m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xFFE00000
|
||||
eb_cpu5282 m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xFF000000
|
||||
eb_cpu5282_internal m68k mcf52x2 eb_cpu5282 BuS - eb_cpu5282:SYS_TEXT_BASE=0xF0000000
|
||||
TASREG m68k mcf52x2 tasreg esd
|
||||
M5208EVBE m68k mcf52x2 m5208evbe freescale
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@
|
|||
|
||||
#define CONFIG_MCFUART
|
||||
#define CONFIG_SYS_UART_PORT (0)
|
||||
#define CONFIG_BAUDRATE 9600
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */
|
||||
|
||||
|
|
@ -52,20 +52,24 @@
|
|||
#define CONFIG_RESET_TO_RETRY
|
||||
#define CONFIG_SPLASH_SCREEN
|
||||
|
||||
#define CONFIG_HW_WATCHDOG
|
||||
|
||||
#define CONFIG_STATUS_LED
|
||||
#define CONFIG_BOARD_SPECIFIC_LED
|
||||
#define STATUS_LED_ACTIVE 0
|
||||
#define STATUS_LED_BIT 0x0008 /* Timer7 GPIO */
|
||||
#define STATUS_LED_BOOT 0
|
||||
#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
|
||||
#define STATUS_LED_STATE STATUS_LED_OFF
|
||||
|
||||
/*----------------------------------------------------------------------*
|
||||
* Configuration for environment *
|
||||
* Environment is in the second sector of the first 256k of flash *
|
||||
*----------------------------------------------------------------------*/
|
||||
|
||||
#ifndef CONFIG_MONITOR_IS_IN_RAM
|
||||
#define CONFIG_ENV_ADDR 0xF003C000 /* End of 256K */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x4000
|
||||
#define CONFIG_ENV_ADDR 0xFF040000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x00020000
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#else
|
||||
#define CONFIG_ENV_ADDR 0xFFE04000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x2000
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#endif
|
||||
|
||||
/*
|
||||
* BOOTP options
|
||||
|
|
@ -78,26 +82,24 @@
|
|||
/*
|
||||
* Command line configuration.
|
||||
*/
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#include <config_cmd_default.h>
|
||||
|
||||
#undef CONFIG_CMD_LOADB
|
||||
#define CONFIG_CMD_DATE
|
||||
#define CONFIG_CMD_DHCP
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_CMD_LED
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_NET
|
||||
|
||||
#define CONFIG_MCFTMR
|
||||
|
||||
|
||||
#define CONFIG_BOOTDELAY 5
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_PROMPT "\nEB+CPU5282> "
|
||||
#define CONFIG_SYS_LONGHELP 1
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
|
|
@ -112,12 +114,12 @@
|
|||
/*----------------------------------------------------------------------*
|
||||
* Clock and PLL Configuration *
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_HZ 10000000
|
||||
#define CONFIG_SYS_CLK 58982400 /* 9,8304MHz * 6 */
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */
|
||||
|
||||
/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
|
||||
/* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */
|
||||
|
||||
#define CONFIG_SYS_MFD 0x01 /* PLL Multiplication Factor Devider */
|
||||
#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
|
||||
#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
|
||||
|
||||
/*----------------------------------------------------------------------*
|
||||
|
|
@ -135,7 +137,6 @@
|
|||
#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
|
||||
#define MCFFEC_TOUT_LOOP 50000
|
||||
|
||||
#define CONFIG_ETHADDR 00:CF:52:82:EB:01
|
||||
#define CONFIG_OVERWRITE_ETHADDR_ONCE
|
||||
|
||||
/*-------------------------------------------------------------------------
|
||||
|
|
@ -161,12 +162,11 @@
|
|||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE1 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_SIZE1 16 /* SDRAM size in MB */
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE1
|
||||
#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE1
|
||||
#define CONFIG_SYS_SDRAM_BASE0 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0
|
||||
#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
|
||||
|
||||
/* If M5282 port is fully implemented the monitor base will be behind
|
||||
* the vector table. */
|
||||
|
|
@ -190,16 +190,24 @@
|
|||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45
|
||||
|
||||
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
|
||||
#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000
|
||||
#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 35
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 128
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 10000000
|
||||
#define CONFIG_SYS_FLASH_PROTECTION
|
||||
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_SIZE 16*1024*1024
|
||||
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
|
|
@ -221,12 +229,16 @@
|
|||
* Memory bank definitions
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_CS0_BASE 0xFFE00000
|
||||
#define CONFIG_SYS_CS0_BASE 0xFF000000
|
||||
#define CONFIG_SYS_CS0_CTRL 0x00001980
|
||||
#define CONFIG_SYS_CS0_MASK 0x001F0001
|
||||
#define CONFIG_SYS_CS0_MASK 0x00FF0001
|
||||
|
||||
#define CONFIG_SYS_CS3_BASE 0xE0000000
|
||||
#define CONFIG_SYS_CS0_CTRL 0x00001980
|
||||
#define CONFIG_SYS_CS2_BASE 0xE0000000
|
||||
#define CONFIG_SYS_CS2_CTRL 0x00001980
|
||||
#define CONFIG_SYS_CS2_MASK 0x000F0001
|
||||
|
||||
#define CONFIG_SYS_CS3_BASE 0xE0100000
|
||||
#define CONFIG_SYS_CS3_CTRL 0x00001980
|
||||
#define CONFIG_SYS_CS3_MASK 0x000F0001
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
|
|
@ -248,11 +260,30 @@
|
|||
#define CONFIG_SYS_PCDDR 0x0000000
|
||||
#define CONFIG_SYS_PCDAT 0x0000000
|
||||
|
||||
#define CONFIG_SYS_PASPAR 0x0F0F
|
||||
#define CONFIG_SYS_PEHLPAR 0xC0
|
||||
#define CONFIG_SYS_PUAPAR 0x0F
|
||||
#define CONFIG_SYS_DDRUA 0x05
|
||||
#define CONFIG_SYS_PJPAR 0xFF
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*/
|
||||
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_FSL_I2C
|
||||
|
||||
#define CONFIG_SYS_I2C_OFFSET 0x00000300
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
|
||||
|
||||
#define CONFIG_SYS_I2C_SPEED 100000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0
|
||||
|
||||
#ifdef CONFIG_CMD_DATE
|
||||
#define CONFIG_RTC_DS1338
|
||||
#define CONFIG_I2C_RTC_ADDR 0x68
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* VIDEO configuration
|
||||
*/
|
||||
|
|
@ -264,8 +295,7 @@
|
|||
|
||||
#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2
|
||||
#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1
|
||||
#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS3_BASE
|
||||
#define CONFIG_SYS_VCXK_AUTODETECT 1
|
||||
#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE
|
||||
|
||||
#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT
|
||||
#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR
|
||||
|
|
|
|||
Loading…
Reference in a new issue