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Merge git://source.denx.de/u-boot-socfpga

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Bugfixes for this one socfpga platform
This commit is contained in:
Tom Rini 2021-09-23 08:30:45 -04:00
commit d7ac865b98
5 changed files with 11 additions and 20 deletions
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6
arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi
View file

@ -11,14 +11,10 @@
/{ /{
aliases { aliases {
spi0 = "/soc/spi@ff705000"; spi0 = "/soc/spi@ff705000";
udc0 = &usb0; udc0 = &usb1;
}; };
}; };
&watchdog0 {
status = "disabled";
};
&mmc { &mmc {
status = "disabled"; status = "disabled";
}; };

7
board/softing/vining_fpga/socfpga.c
View file

@ -23,7 +23,6 @@ DECLARE_GLOBAL_DATA_PTR;
*/ */
int board_late_init(void) int board_late_init(void)
{ {
const unsigned int phy_nrst_gpio = 0;
const unsigned int usb_nrst_gpio = 35; const unsigned int usb_nrst_gpio = 35;
int ret; int ret;
@ -33,12 +32,6 @@ int board_late_init(void)
/* Address of boot parameters for ATAG (if ATAG is used) */ /* Address of boot parameters for ATAG (if ATAG is used) */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
ret = gpio_request(phy_nrst_gpio, "phy_nrst_gpio");
if (!ret)
gpio_direction_output(phy_nrst_gpio, 1);
else
printf("Cannot remove PHY from reset!\n");
ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio"); ret = gpio_request(usb_nrst_gpio, "usb_nrst_gpio");
if (!ret) if (!ret)
gpio_direction_output(usb_nrst_gpio, 1); gpio_direction_output(usb_nrst_gpio, 1);

8
configs/socfpga_vining_fpga_defconfig
View file

@ -1,6 +1,6 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y CONFIG_DM_GPIO=y
@ -56,6 +56,7 @@ CONFIG_DFU_SF=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000
CONFIG_DWAPB_GPIO=y CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_LED_STATUS=y CONFIG_LED_STATUS=y
CONFIG_LED_STATUS_GPIO=y CONFIG_LED_STATUS_GPIO=y
CONFIG_LED_STATUS0=y CONFIG_LED_STATUS0=y
@ -74,6 +75,9 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70
CONFIG_MMC_DW=y CONFIG_MMC_DW=y
CONFIG_MTD=y CONFIG_MTD=y
CONFIG_SF_DEFAULT_MODE=0x0
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
@ -91,7 +95,7 @@ CONFIG_DESIGNWARE_SPI=y
CONFIG_USB=y CONFIG_USB=y
CONFIG_USB_DWC2=y CONFIG_USB_DWC2=y
CONFIG_USB_GADGET=y CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="softing" CONFIG_USB_GADGET_MANUFACTURER="Softing"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DWC2_OTG=y

8
drivers/ddr/altera/sequencer.c
View file

@ -3714,7 +3714,7 @@ static void debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass)
u32 debug_info; u32 debug_info;
if (pass) { if (pass) {
debug("%s: CALIBRATION PASSED\n", __FILE__); debug(KBUILD_BASENAME ": CALIBRATION PASSED\n");
seq->gbl.fom_in /= 2; seq->gbl.fom_in /= 2;
seq->gbl.fom_out /= 2; seq->gbl.fom_out /= 2;
@ -3733,7 +3733,7 @@ static void debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass)
writel(debug_info, &phy_mgr_cfg->cal_debug_info); writel(debug_info, &phy_mgr_cfg->cal_debug_info);
writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status); writel(PHY_MGR_CAL_SUCCESS, &phy_mgr_cfg->cal_status);
} else { } else {
debug("%s: CALIBRATION FAILED\n", __FILE__); debug(KBUILD_BASENAME ": CALIBRATION FAILED\n");
debug_info = seq->gbl.error_stage; debug_info = seq->gbl.error_stage;
debug_info |= seq->gbl.error_substage << 8; debug_info |= seq->gbl.error_substage << 8;
@ -3750,7 +3750,7 @@ static void debug_mem_calibrate(struct socfpga_sdrseq *seq, int pass)
writel(debug_info, &sdr_reg_file->failing_stage); writel(debug_info, &sdr_reg_file->failing_stage);
} }
debug("%s: Calibration complete\n", __FILE__); debug(KBUILD_BASENAME ": Calibration complete\n");
} }
/** /**
@ -3934,7 +3934,7 @@ int sdram_calibration_full(struct socfpga_sdr *sdr)
initialize_tracking(&seq); initialize_tracking(&seq);
debug("%s: Preparing to start memory calibration\n", __FILE__); debug(KBUILD_BASENAME ": Preparing to start memory calibration\n");
debug("%s:%d\n", __func__, __LINE__); debug("%s:%d\n", __func__, __LINE__);
debug_cond(DLEVEL >= 1, debug_cond(DLEVEL >= 1,

2
include/configs/socfpga_vining_fpga.h
View file

@ -17,8 +17,6 @@
#define CONFIG_LOADADDR 0x01000000 #define CONFIG_LOADADDR 0x01000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* Ethernet on SoC (EMAC) */
/* Extra Environment */ /* Extra Environment */
#define CONFIG_HOSTNAME "socfpga_vining_fpga" #define CONFIG_HOSTNAME "socfpga_vining_fpga"