da850: Enable SPI Flash

The patch was already posted to the arago project,
but not yet to mainline. It allows to save environment into
the spi flash. Tested on LogiPD tmdxl138.

Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Detlev Zundev <dzu@denx.de>
CC: Ben Gardiner <bengardiner@nanometrics.ca>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Stefano Babic 2010-11-11 15:38:02 +01:00 committed by Sandeep Paulraj
parent a131148efe
commit d73a8a1b8c
2 changed files with 39 additions and 1 deletions

View file

@ -133,7 +133,8 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_PSC1_BASE 0x01e27000 #define DAVINCI_PSC1_BASE 0x01e27000
#define DAVINCI_SPI0_BASE 0x01c41000 #define DAVINCI_SPI0_BASE 0x01c41000
#define DAVINCI_USB_OTG_BASE 0x01e00000 #define DAVINCI_USB_OTG_BASE 0x01e00000
#define DAVINCI_SPI1_BASE 0x01e12000 #define DAVINCI_SPI1_BASE (cpu_is_da830() ? \
0x01e12000 : 0x01f0e000)
#define DAVINCI_GPIO_BASE 0x01e26000 #define DAVINCI_GPIO_BASE 0x01e26000
#define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000 #define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
@ -364,6 +365,9 @@ struct davinci_pllc_regs {
#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE) #define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
#define DAVINCI_PLLC_DIV_MASK 0x1f #define DAVINCI_PLLC_DIV_MASK 0x1f
#define ASYNC3 get_async3_src()
#define PLL1_SYSCLK2 ((1 << 16) | 0x2)
#define DAVINCI_SPI1_CLKID (cpu_is_da830() ? 2 : ASYNC3)
/* Clock IDs */ /* Clock IDs */
enum davinci_clk_ids { enum davinci_clk_ids {
DAVINCI_SPI0_CLKID = 2, DAVINCI_SPI0_CLKID = 2,
@ -458,6 +462,12 @@ static inline int cpu_is_da850(void)
return ((part_no == 0xb7d1) ? 1 : 0); return ((part_no == 0xb7d1) ? 1 : 0);
} }
static inline int get_async3_src(void)
{
return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
PLL1_SYSCLK2 : 2;
}
#endif /* CONFIG_SOC_DA8XX */ #endif /* CONFIG_SOC_DA8XX */
#endif /* __ASM_ARCH_HARDWARE_H */ #endif /* __ASM_ARCH_HARDWARE_H */

View file

@ -27,6 +27,7 @@
* Board * Board
*/ */
#define CONFIG_DRIVER_TI_EMAC #define CONFIG_DRIVER_TI_EMAC
#define CONFIG_USE_SPIFLASH
/* /*
* SoC Configuration * SoC Configuration
@ -71,6 +72,15 @@
#define CONFIG_BAUDRATE 115200 /* Default baud rate */ #define CONFIG_BAUDRATE 115200 /* Default baud rate */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_DAVINCI_SPI
#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
#define CONFIG_SF_DEFAULT_SPEED 30000000
#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
/* /*
* I2C Configuration * I2C Configuration
*/ */
@ -115,6 +125,16 @@
#define CONFIG_NET_MULTI #define CONFIG_NET_MULTI
#endif #endif
#ifdef CONFIG_USE_SPIFLASH
#undef CONFIG_ENV_IS_IN_FLASH
#undef CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (64 << 10)
#define CONFIG_ENV_OFFSET (256 << 10)
#define CONFIG_ENV_SECT_SIZE (64 << 10)
#define CONFIG_SYS_NO_FLASH
#endif
/* /*
* U-Boot general configuration * U-Boot general configuration
*/ */
@ -179,6 +199,14 @@
#define CONFIG_CMD_UBIFS #define CONFIG_CMD_UBIFS
#endif #endif
#ifdef CONFIG_USE_SPIFLASH
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_FLASH
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF
#define CONFIG_CMD_SAVEENV
#endif
#if !defined(CONFIG_USE_NAND) && \ #if !defined(CONFIG_USE_NAND) && \
!defined(CONFIG_USE_NOR) && \ !defined(CONFIG_USE_NOR) && \
!defined(CONFIG_USE_SPIFLASH) !defined(CONFIG_USE_SPIFLASH)