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armv8: Enable CPUECTLR.SMPEN for coherency

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For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.

For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.

Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Mingkai Hu 2016-07-07 12:22:12 +08:00 committed by Tom Rini
parent d56dd0b1f8
commit d73718f323
1 changed files with 8 additions and 0 deletions
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8
arch/arm/cpu/armv8/start.S
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@ -81,6 +81,14 @@ reset:
msr cpacr_el1, x0 /* Enable FP/SIMD */ msr cpacr_el1, x0 /* Enable FP/SIMD */
0: 0:
/* Enalbe SMPEN bit for coherency.
* This register is not architectural but at the moment
* this bit should be set for A53/A57/A72.
*/
mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */
orr x0, x0, #0x40
msr S3_1_c15_c2_1, x0
/* Apply ARM core specific erratas */ /* Apply ARM core specific erratas */
bl apply_core_errata bl apply_core_errata