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sunxi: HYP/non-sec: add sun7i PSCI backend
So far, only supporting the CPU_ON method. Other functions can be added later. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Marc Zyngier
Hans de Goede
parent
366cc50278
commit
d5db7024aa
3 changed files with 171 additions and 0 deletions
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@ -17,6 +17,9 @@ obj-$(CONFIG_SUN7I) += clock_sun4i.o
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ifndef CONFIG_SPL_BUILD
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obj-y += cpu_info.o
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ifdef CONFIG_ARMV7_PSCI
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obj-y += psci.o
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endif
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endif
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ifdef CONFIG_SPL_BUILD
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162
arch/arm/cpu/armv7/sunxi/psci.S
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162
arch/arm/cpu/armv7/sunxi/psci.S
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@ -0,0 +1,162 @@
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/*
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* Copyright (C) 2013 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*
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* Based on code by Carl van Schaik <carl@ok-labs.com>.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <config.h>
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#include <asm/psci.h>
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#include <asm/arch/cpu.h>
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/*
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* Memory layout:
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*
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* SECURE_RAM to text_end :
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* ._secure_text section
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* text_end to ALIGN_PAGE(text_end):
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* nothing
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* ALIGN_PAGE(text_end) to ALIGN_PAGE(text_end) + 0x1000)
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* 1kB of stack per CPU (4 CPUs max).
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*/
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.pushsection ._secure.text, "ax"
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.arch_extension sec
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#define ONE_MS (CONFIG_SYS_CLK_FREQ / 1000)
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#define TEN_MS (10 * ONE_MS)
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.macro timer_wait reg, ticks
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@ Program CNTP_TVAL
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movw \reg, #(\ticks & 0xffff)
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movt \reg, #(\ticks >> 16)
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mcr p15, 0, \reg, c14, c2, 0
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isb
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@ Enable physical timer, mask interrupt
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mov \reg, #3
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mcr p15, 0, \reg, c14, c2, 1
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@ Poll physical timer until ISTATUS is on
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1: isb
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mrc p15, 0, \reg, c14, c2, 1
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ands \reg, \reg, #4
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bne 1b
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@ Disable timer
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mov \reg, #0
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mcr p15, 0, \reg, c14, c2, 1
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isb
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.endm
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.globl psci_arch_init
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psci_arch_init:
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mrc p15, 0, r5, c1, c1, 0 @ Read SCR
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bic r5, r5, #1 @ Secure mode
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mcr p15, 0, r5, c1, c1, 0 @ Write SCR
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isb
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mrc p15, 0, r4, c0, c0, 5 @ MPIDR
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and r4, r4, #3 @ cpu number in cluster
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mov r5, #400 @ 1kB of stack per CPU
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mul r4, r4, r5
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adr r5, text_end @ end of text
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add r5, r5, #0x2000 @ Skip two pages
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lsr r5, r5, #12 @ Align to start of page
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lsl r5, r5, #12
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sub sp, r5, r4 @ here's our stack!
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bx lr
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@ r1 = target CPU
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@ r2 = target PC
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.globl psci_cpu_on
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psci_cpu_on:
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adr r0, _target_pc
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str r2, [r0]
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dsb
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movw r0, #(SUNXI_CPUCFG_BASE & 0xffff)
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movt r0, #(SUNXI_CPUCFG_BASE >> 16)
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@ CPU mask
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and r1, r1, #3 @ only care about first cluster
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mov r4, #1
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lsl r4, r4, r1
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adr r6, _sunxi_cpu_entry
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str r6, [r0, #0x1a4] @ PRIVATE_REG (boot vector)
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@ Assert reset on target CPU
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mov r6, #0
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lsl r5, r1, #6 @ 64 bytes per CPU
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add r5, r5, #0x40 @ Offset from base
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add r5, r5, r0 @ CPU control block
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str r6, [r5] @ Reset CPU
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@ l1 invalidate
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ldr r6, [r0, #0x184]
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bic r6, r6, r4
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str r6, [r0, #0x184]
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@ Lock CPU
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ldr r6, [r0, #0x1e4]
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bic r6, r6, r4
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str r6, [r0, #0x1e4]
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@ Release power clamp
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movw r6, #0x1ff
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movt r6, #0
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1: lsrs r6, r6, #1
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str r6, [r0, #0x1b0]
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bne 1b
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timer_wait r1, TEN_MS
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@ Clear power gating
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ldr r6, [r0, #0x1b4]
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bic r6, r6, #1
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str r6, [r0, #0x1b4]
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@ Deassert reset on target CPU
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mov r6, #3
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str r6, [r5]
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@ Unlock CPU
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ldr r6, [r0, #0x1e4]
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orr r6, r6, r4
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str r6, [r0, #0x1e4]
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mov r0, #ARM_PSCI_RET_SUCCESS @ Return PSCI_RET_SUCCESS
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mov pc, lr
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_target_pc:
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.word 0
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_sunxi_cpu_entry:
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@ Set SMP bit
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mrc p15, 0, r0, c1, c0, 1
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orr r0, r0, #0x40
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mcr p15, 0, r0, c1, c0, 1
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isb
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bl _nonsec_init
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bl psci_arch_init
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adr r0, _target_pc
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ldr r0, [r0]
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b _do_nonsec_entry
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text_end:
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.popsection
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@ -29,6 +29,12 @@
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#endif
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#endif
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#define CONFIG_ARMV7_VIRT 1
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#define CONFIG_ARMV7_NONSEC 1
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#define CONFIG_ARMV7_PSCI 1
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#define CONFIG_ARMV7_PSCI_NR_CPUS 2
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#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
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/*
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* Include common sunxi configuration where most the settings are
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*/
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