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t210: do not enable PLLE and UPHY PLL HW PWRSEQ

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This commit removes the programming sequence that enables PLLE and UPHY
PLL hardware power sequencers. Per TRM, boot software should enable PLLE
and UPHY PLLs in software controlled power-on state and should power
down PLL before jumping into kernel or the next stage boot software.

Adds call to board_cleanup_before_linux to facilitate this.

Signed-off-by: JC Kuo <jckuo@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
JC Kuo 2020-03-26 16:10:09 -07:00 committed by Tom Warren
parent 9eb15cbe5c
commit d491dc09e4
6 changed files with 59 additions and 44 deletions
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5
arch/arm/cpu/armv8/cpu.c
View file

@ -32,6 +32,8 @@ void sdelay(unsigned long loops)
"b.ne 1b" : "=r" (loops) : "0"(loops) : "cc");
}
void __weak board_cleanup_before_linux(void){}
int cleanup_before_linux(void)
{
/*
@ -40,6 +42,9 @@ int cleanup_before_linux(void)
*
* disable interrupt and turn off caches etc ...
*/
board_cleanup_before_linux();
disable_interrupts();
/*

1
arch/arm/include/asm/arch-tegra/xusb-padctl.h
View file

@ -16,6 +16,7 @@ struct tegra_xusb_phy;
struct tegra_xusb_phy *tegra_xusb_phy_get(unsigned int type);
void tegra_xusb_padctl_init(void);
void tegra_xusb_padctl_exit(void);
int tegra_xusb_phy_prepare(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_enable(struct tegra_xusb_phy *phy);
int tegra_xusb_phy_disable(struct tegra_xusb_phy *phy);

6
arch/arm/mach-tegra/board2.c
View file

@ -181,6 +181,12 @@ int board_init(void)
return nvidia_board_init();
}
void board_cleanup_before_linux(void)
{
/* power down UPHY PLL */
tegra_xusb_padctl_exit();
}
#ifdef CONFIG_BOARD_EARLY_INIT_F
static void __gpio_early_init(void)
{

19
arch/arm/mach-tegra/tegra210/clock.c
View file

@ -1235,25 +1235,6 @@ int tegra_plle_enable(void)
value &= ~PLLE_SS_CNTL_INTERP_RESET;
writel(value, NV_PA_CLK_RST_BASE + PLLE_SS_CNTL);
/* 7. Enable HW power sequencer for PLLE */
value = readl(NV_PA_CLK_RST_BASE + PLLE_MISC);
value &= ~PLLE_MISC_IDDQ_SWCTL;
writel(value, NV_PA_CLK_RST_BASE + PLLE_MISC);
value = readl(NV_PA_CLK_RST_BASE + PLLE_AUX);
value &= ~PLLE_AUX_SS_SWCTL;
value &= ~PLLE_AUX_ENABLE_SWCTL;
value |= PLLE_AUX_SS_SEQ_INCLUDE;
value |= PLLE_AUX_USE_LOCKDET;
writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
/* 8. Wait 1 us */
udelay(1);
value |= PLLE_AUX_SEQ_ENABLE;
writel(value, NV_PA_CLK_RST_BASE + PLLE_AUX);
return 0;
}

68
arch/arm/mach-tegra/tegra210/xusb-padctl.c
View file

@ -170,6 +170,17 @@ static int phy_unprepare(struct tegra_xusb_phy *phy)
return tegra_xusb_padctl_disable(phy->padctl);
}
#define XUSB_PADCTL_USB3_PAD_MUX 0x28
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE (1 << 0)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0 (1 << 1)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1 (1 << 2)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2 (1 << 3)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3 (1 << 4)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4 (1 << 5)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5 (1 << 6)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6 (1 << 7)
#define XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0 (1 << 8)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1 0x360
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20)
#define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV(x) (((x) & 0xff) << 20)
@ -366,31 +377,6 @@ static int pcie_phy_enable(struct tegra_xusb_phy *phy)
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_CLK_EN;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
value &= ~CLK_RST_XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL;
value &= ~CLK_RST_XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL;
value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET;
value |= CLK_RST_XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL2_CAL_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL8_RCAL_OVRD;
padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
udelay(1);
value = readl(NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
value |= CLK_RST_XUSBIO_PLL_CFG0_SEQ_ENABLE;
writel(value, NV_PA_CLK_RST_BASE + CLK_RST_XUSBIO_PLL_CFG0);
debug("< %s()\n", __func__);
return 0;
}
@ -454,3 +440,35 @@ void tegra_xusb_padctl_init(void)
ret = tegra_xusb_process_nodes(nodes, count, &tegra210_socdata);
debug("%s: done, ret=%d\n", __func__, ret);
}
void tegra_xusb_padctl_exit(void)
{
u32 value;
debug("> %s\n", __func__);
value = padctl_readl(&padctl, XUSB_PADCTL_USB3_PAD_MUX);
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE;
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK0;
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK1;
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK2;
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK3;
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK4;
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK5;
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_PCIE_PAD_IDDQ_DISABLE_MASK6;
value &= ~XUSB_PADCTL_USB3_PAD_MUX_FORCE_SATA_PAD_IDDQ_DISABLE_MASK0;
padctl_writel(&padctl, value, XUSB_PADCTL_USB3_PAD_MUX);
value = padctl_readl(&padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_IDDQ;
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP_MASK;
value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_SLEEP(3);
value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE;
padctl_writel(&padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
reset_set_enable(PERIPH_ID_PEX_USB_UPHY, 1);
while (padctl.enable)
tegra_xusb_padctl_disable(&padctl);
debug("< %s()\n", __func__);
}

4
arch/arm/mach-tegra/xusb-padctl-dummy.c
View file

@ -36,3 +36,7 @@ int __weak tegra_xusb_phy_unprepare(struct tegra_xusb_phy *phy)
void __weak tegra_xusb_padctl_init(void)
{
}
void __weak tegra_xusb_padctl_exit(void)
{
}