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Merge branch 'u-boot-microblaze/zynq' into 'u-boot-arm/master'

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This commit is contained in:
Albert ARIBAUD 2013-11-22 10:19:35 +01:00
commit d44a5f5128
1 changed files with 5 additions and 4 deletions
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9
arch/arm/cpu/armv7/zynq/cpu.c
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@ -16,23 +16,24 @@ void lowlevel_init(void)
int arch_cpu_init(void) int arch_cpu_init(void)
{ {
zynq_slcr_unlock(); zynq_slcr_unlock();
/* remap DDR to zero, FILTERSTART */
writel(0, &scu_base->filter_start);
/* Device config APB, unlock the PCAP */ /* Device config APB, unlock the PCAP */
writel(0x757BDF0D, &devcfg_base->unlock); writel(0x757BDF0D, &devcfg_base->unlock);
writel(0xFFFFFFFF, &devcfg_base->rom_shadow); writel(0xFFFFFFFF, &devcfg_base->rom_shadow);
#if (CONFIG_SYS_SDRAM_BASE == 0)
/* remap DDR to zero, FILTERSTART */
writel(0, &scu_base->filter_start);
/* OCM_CFG, Mask out the ROM, map ram into upper addresses */ /* OCM_CFG, Mask out the ROM, map ram into upper addresses */
writel(0x1F, &slcr_base->ocm_cfg); writel(0x1F, &slcr_base->ocm_cfg);
/* FPGA_RST_CTRL, clear resets on AXI fabric ports */ /* FPGA_RST_CTRL, clear resets on AXI fabric ports */
writel(0x0, &slcr_base->fpga_rst_ctrl); writel(0x0, &slcr_base->fpga_rst_ctrl);
/* TZ_DDR_RAM, Set DDR trust zone non-secure */
writel(0xFFFFFFFF, &slcr_base->trust_zone);
/* Set urgent bits with register */ /* Set urgent bits with register */
writel(0x0, &slcr_base->ddr_urgent_sel); writel(0x0, &slcr_base->ddr_urgent_sel);
/* Urgent write, ports S2/S3 */ /* Urgent write, ports S2/S3 */
writel(0xC, &slcr_base->ddr_urgent); writel(0xC, &slcr_base->ddr_urgent);
#endif
zynq_slcr_lock(); zynq_slcr_lock();