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mtd: nand: pxa3xx: Add support for the Marvell AC5 SoC

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The NAND flash controller (NFC) on the AC5/AC5X SoC is the same as
the NFC used on other Marvell SoCs. It does have the additional
restriction of only supporting SDR timing modes up to 3.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Chris Packham 2023-07-10 10:47:34 +12:00 committed by Stefan Roese
parent f52e2d884c
commit d4360b4ecb
1 changed files with 14 additions and 3 deletions
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17
drivers/mtd/nand/raw/pxa3xx_nand.c
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@ -167,6 +167,7 @@ enum pxa3xx_nand_variant {
PXA3XX_NAND_VARIANT_PXA, PXA3XX_NAND_VARIANT_PXA,
PXA3XX_NAND_VARIANT_ARMADA370, PXA3XX_NAND_VARIANT_ARMADA370,
PXA3XX_NAND_VARIANT_ARMADA_8K, PXA3XX_NAND_VARIANT_ARMADA_8K,
PXA3XX_NAND_VARIANT_AC5,
}; };
struct pxa3xx_nand_host { struct pxa3xx_nand_host {
@ -391,6 +392,10 @@ static const struct udevice_id pxa3xx_nand_dt_ids[] = {
.compatible = "marvell,armada-8k-nand-controller", .compatible = "marvell,armada-8k-nand-controller",
.data = PXA3XX_NAND_VARIANT_ARMADA_8K, .data = PXA3XX_NAND_VARIANT_ARMADA_8K,
}, },
{
.compatible = "marvell,mvebu-ac5-pxa3xx-nand",
.data = PXA3XX_NAND_VARIANT_AC5,
},
{} {}
}; };
@ -505,6 +510,9 @@ static int pxa3xx_nand_init_timings(struct pxa3xx_nand_host *host)
if (mode < 0) if (mode < 0)
mode = 0; mode = 0;
if (info->variant == PXA3XX_NAND_VARIANT_AC5)
mode = min(mode, 3);
timings = onfi_async_timing_mode_to_sdr_timings(mode); timings = onfi_async_timing_mode_to_sdr_timings(mode);
if (IS_ERR(timings)) if (IS_ERR(timings))
return PTR_ERR(timings); return PTR_ERR(timings);
@ -730,7 +738,8 @@ static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
/* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */ /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 || if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K ||
info->variant == PXA3XX_NAND_VARIANT_AC5)
nand_writel(info, NDCB0, info->ndcb3); nand_writel(info, NDCB0, info->ndcb3);
} }
@ -1579,7 +1588,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
/* Device detection must be done with ECC disabled */ /* Device detection must be done with ECC disabled */
if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 || if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K ||
info->variant == PXA3XX_NAND_VARIANT_AC5)
nand_writel(info, NDECCCTRL, 0x0); nand_writel(info, NDECCCTRL, 0x0);
if (nand_scan_ident(mtd, 1, NULL)) if (nand_scan_ident(mtd, 1, NULL))
@ -1630,7 +1640,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
*/ */
if (mtd->writesize > info->chunk_size) { if (mtd->writesize > info->chunk_size) {
if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 || if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 ||
info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K) { info->variant == PXA3XX_NAND_VARIANT_ARMADA_8K ||
info->variant == PXA3XX_NAND_VARIANT_AC5) {
chip->cmdfunc = nand_cmdfunc_extended; chip->cmdfunc = nand_cmdfunc_extended;
} else { } else {
dev_err(mtd->dev, dev_err(mtd->dev,