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ddr: altera: Clean up scc_mgr_zero_group()
First, zap unused argument of the function. Next, clean up the data types, constify where applicable, clean up comments and add kerneldoc. Signed-off-by: Marek Vasut <marex@denx.de>
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f42af35bdc
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1 changed files with 21 additions and 18 deletions
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@ -565,43 +565,47 @@ static void scc_mgr_load_dqs_for_write_group(const u32 write_group)
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writel(base + i, &sdr_scc_mgr->dqs_ena);
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}
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static void scc_mgr_zero_group(uint32_t write_group, uint32_t test_begin,
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int32_t out_only)
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/**
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* scc_mgr_zero_group() - Zero all configs for a group
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*
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* Zero DQ, DM, DQS and OCT configs for a group.
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*/
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static void scc_mgr_zero_group(const u32 write_group, const int out_only)
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{
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uint32_t i, r;
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int i, r;
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for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS; r +=
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NUM_RANKS_PER_SHADOW_REG) {
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/* Zero all DQ config settings */
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for (r = 0; r < RW_MGR_MEM_NUMBER_OF_RANKS;
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r += NUM_RANKS_PER_SHADOW_REG) {
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/* Zero all DQ config settings. */
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for (i = 0; i < RW_MGR_MEM_DQ_PER_WRITE_DQS; i++) {
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scc_mgr_set_dq_out1_delay(i, 0);
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if (!out_only)
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scc_mgr_set_dq_in_delay(i, 0);
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}
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/* multicast to all DQ enables */
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/* Multicast to all DQ enables. */
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writel(0xff, &sdr_scc_mgr->dq_ena);
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/* Zero all DM config settings */
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for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++) {
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/* Zero all DM config settings. */
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for (i = 0; i < RW_MGR_NUM_DM_PER_WRITE_GROUP; i++)
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scc_mgr_set_dm_out1_delay(i, 0);
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}
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/* multicast to all DM enables */
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/* Multicast to all DM enables. */
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writel(0xff, &sdr_scc_mgr->dm_ena);
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/* zero all DQS io settings */
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/* Zero all DQS IO settings. */
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if (!out_only)
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scc_mgr_set_dqs_io_in_delay(0);
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/* av/cv don't have out2 */
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/* Arria V/Cyclone V don't have out2. */
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scc_mgr_set_dqs_out1_delay(IO_DQS_OUT_RESERVE);
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scc_mgr_set_oct_out1_delay(write_group, IO_DQS_OUT_RESERVE);
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scc_mgr_load_dqs_for_write_group(write_group);
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/* multicast to all DQS IO enables (only 1) */
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/* Multicast to all DQS IO enables (only 1 in total). */
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writel(0, &sdr_scc_mgr->dqs_io_ena);
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/* hit update to zero everything */
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/* Hit update to zero everything. */
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writel(0, &sdr_scc_mgr->update);
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}
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}
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@ -2344,7 +2348,7 @@ static uint32_t rw_mgr_mem_calibrate_vfifo(uint32_t read_group,
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* first case).
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*/
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if (d > 2)
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scc_mgr_zero_group(write_group, write_test_bgn, 1);
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scc_mgr_zero_group(write_group, 1);
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return 1;
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}
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@ -3368,8 +3372,7 @@ static uint32_t mem_calibrate(void)
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writel(write_group, SDR_PHYGRP_SCCGRP_ADDRESS |
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SCC_MGR_GROUP_COUNTER_OFFSET);
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scc_mgr_zero_group(write_group, write_test_bgn,
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0);
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scc_mgr_zero_group(write_group, 0);
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for (read_group = write_group *
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RW_MGR_MEM_IF_READ_DQS_WIDTH /
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