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ARM: imx: udoo_neo: Convert to ethernet DM

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Convert the UDOO Neo to ethernet DM support.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Cc: Francesco Montefoschi <francesco.montefoschi@udoo.org>
Cc: Breno Lima <breno.lima@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peter Robinson 2021-04-01 21:08:13 +01:00 committed by Tom Rini
parent 9db428904f
commit d410dc8802
3 changed files with 7 additions and 69 deletions
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63
board/udoo/neo/neo.c
View file

@ -9,7 +9,6 @@
*/
#include <init.h>
#include <net.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
@ -18,6 +17,7 @@
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/iomux-v3.h>
#include <dm.h>
#include <env.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
@ -28,8 +28,6 @@
#include <linux/sizes.h>
#include <common.h>
#include <i2c.h>
#include <miiphy.h>
#include <netdev.h>
#include <power/pmic.h>
#include <power/pfuze3000_pmic.h>
#include <malloc.h>
@ -216,21 +214,6 @@ static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const fec1_pads[] = {
MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII1_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_ENET2_TX_CLK__GPIO2_IO_9 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
MX6_PAD_ENET1_CRS__GPIO2_IO_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
};
static iomux_v3_cfg_t const phy_control_pads[] = {
/* 25MHz Ethernet PHY Clock */
MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M |
@ -257,7 +240,7 @@ static void setup_iomux_uart(void)
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
}
static int setup_fec(int fec_id)
static int setup_fec(void)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
int reg;
@ -275,46 +258,7 @@ static int setup_fec(int fec_id)
reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
writel(reg, &anatop->pll_enet);
return enable_fec_anatop_clock(fec_id, ENET_25MHZ);
}
int board_eth_init(struct bd_info *bis)
{
uint32_t base = IMX_FEC_BASE;
struct mii_dev *bus = NULL;
struct phy_device *phydev = NULL;
int ret;
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
setup_fec(CONFIG_FEC_ENET_DEV);
bus = fec_get_miibus(base, CONFIG_FEC_ENET_DEV);
if (!bus)
return -EINVAL;
phydev = phy_find_by_mask(bus, (0x1 << CONFIG_FEC_MXC_PHYADDR),
PHY_INTERFACE_MODE_RMII);
if (!phydev) {
free(bus);
return -EINVAL;
}
ret = fec_probe(bis, CONFIG_FEC_ENET_DEV, base, bus, phydev);
if (ret) {
free(bus);
free(phydev);
return ret;
}
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
return enable_fec_anatop_clock(0, ENET_25MHZ);
}
int board_init(void)
@ -374,6 +318,7 @@ static int get_board_value(void)
int board_early_init_f(void)
{
setup_iomux_uart();
setup_fec();
return 0;
}

3
configs/udoo_neo_defconfig
View file

@ -37,6 +37,8 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_BOUNCE_BUFFER=y
CONFIG_DM=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
@ -46,6 +48,7 @@ CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_RGMII=y
CONFIG_MXC_UART=y
CONFIG_IMX_THERMAL=y
CONFIG_OF_LIBFDT=y

10
include/configs/udoo_neo.h
View file

@ -83,14 +83,4 @@
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
#define PFUZE3000_I2C_BUS 0
/* Network */
#define CONFIG_FEC_MXC
#define CONFIG_FEC_ENET_DEV 0
#define IMX_FEC_BASE ENET_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0x0
#define CONFIG_FEC_XCV_TYPE RMII
#define CONFIG_ETHPRIME "FEC0"
#endif /* __CONFIG_H */