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- drop old CFB code

Browse source 
- drop CONFIG_LCD_BMP_RLE8
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Merge tag 'next-20220328' of https://source.denx.de/u-boot/custodians/u-boot-video into next

 - drop old CFB code
 - drop CONFIG_LCD_BMP_RLE8
This commit is contained in:
Tom Rini 2022-03-28 17:04:45 -04:00
commit d2e5250be4
98 changed files with 29 additions and 6669 deletions
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22
README
View file

@ -970,24 +970,6 @@ The following options need to be configured:
- Keyboard Support:
See Kconfig help for available keyboard drivers.
- Video support:
CONFIG_FSL_DIU_FB
Enable the Freescale DIU video driver. Reference boards for
SOCs that have a DIU should define this macro to enable DIU
support, and should also define these other macros:
CONFIG_SYS_DIU_ADDR
CONFIG_VIDEO
CONFIG_CFB_CONSOLE
CONFIG_VIDEO_SW_CURSOR
CONFIG_VGA_AS_SINGLE_DEVICE
CONFIG_VIDEO_BMP_LOGO
The DIU driver will look for the 'video-mode' environment
variable, and if defined, enable the DIU as a console during
boot. See the documentation file doc/README.video for a
description of this variable.
- LCD Support: CONFIG_LCD
Define this to enable LCD support (for output to LCD
@ -1062,10 +1044,6 @@ The following options need to be configured:
If CONFIG_LCD_ROTATION is not defined, the console will be
initialized with 0degree rotation.
CONFIG_LCD_BMP_RLE8
Support drawing of RLE8-compressed bitmaps on the LCD.
- MII/PHY support:
CONFIG_PHY_CLOCK_FREQ (ppc4xx)

4
arch/arm/cpu/armv7/ls102xa/soc.c
View file

@ -174,10 +174,6 @@ int arch_soc_init(void)
out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
#endif
#ifdef CONFIG_VIDEO_FSL_DCU_FB
out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
#endif
/* Configure Little endian for SAI, ASRC and SPDIF */
out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);

1
arch/arm/include/asm/arch-ls102xa/config.h
View file

@ -88,7 +88,6 @@
#define CONFIG_SYS_FSL_ESDHC_BE
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
#define CONFIG_SYS_FSL_DCU_BE
#define CONFIG_SYS_FSL_SEC_MON_LE
#define CONFIG_SYS_FSL_SFP_VER_3_2
#define CONFIG_SYS_FSL_SFP_BE

5
arch/arm/include/asm/mach-imx/mx5_video.h
View file

@ -6,12 +6,7 @@
#ifndef __MX5_VIDEO_H
#define __MX5_VIDEO_H
#ifdef CONFIG_VIDEO
void lcd_enable(void);
void setup_iomux_lcd(void);
#else
static inline void lcd_enable(void) { }
static inline void setup_iomux_lcd(void) { }
#endif
#endif

8
arch/arm/mach-nexell/include/mach/display_dev.h
View file

@ -8,16 +8,12 @@
#ifndef _NX__DISPLAY_DEV_H_
#define _NX__DISPLAY_DEV_H_
#if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO
#include <video_fb.h>
#elif defined CONFIG_LCD
#if !defined(CONFIG_DM_VIDEO) && defined(CONFIG_LCD)
#include <lcd.h>
#endif
struct nx_display_dev {
#if defined CONFIG_VIDEO || defined CONFIG_DM_VIDEO
GraphicDevice graphic_device;
#elif defined CONFIG_LCD
#if !defined(CONFIG_DM_VIDEO) && defined(CONFIG_LCD)
vidinfo_t *panel_info;
#endif
unsigned long base;

1
board/aristainetos/aristainetos.c
View file

@ -39,7 +39,6 @@
#include <power/regulator.h>
#include <power/da9063_pmic.h>
#include <splash.h>
#include <video_fb.h>
DECLARE_GLOBAL_DATA_PTR;

4
board/freescale/common/Makefile
View file

@ -44,16 +44,12 @@ ifndef CONFIG_RAMBOOT_PBL
obj-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o
endif
obj-$(CONFIG_FSL_DIU_CH7301) += diu_ch7301.o
ifdef CONFIG_ARM
obj-$(CONFIG_DEEP_SLEEP) += arm_sleep.o
else
obj-$(CONFIG_DEEP_SLEEP) += mpc85xx_sleep.o
endif
obj-$(CONFIG_FSL_DCU_SII9022A) += dcu_sii9022a.o
obj-$(CONFIG_TARGET_MPC8548CDS) += cds_pci_ft.o
obj-$(CONFIG_TARGET_MPC8536DS) += ics307_clk.o

248
board/freescale/common/dcu_sii9022a.c
View file

@ -1,248 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*/
#include <asm/io.h>
#include <common.h>
#include <fsl_dcu_fb.h>
#include <i2c.h>
#include <linux/fb.h>
#define PIXEL_CLK_LSB_REG 0x00
#define PIXEL_CLK_MSB_REG 0x01
#define VERT_FREQ_LSB_REG 0x02
#define VERT_FREQ_MSB_REG 0x03
#define TOTAL_PIXELS_LSB_REG 0x04
#define TOTAL_PIXELS_MSB_REG 0x05
#define TOTAL_LINES_LSB_REG 0x06
#define TOTAL_LINES_MSB_REG 0x07
#define TPI_INBUS_FMT_REG 0x08
#define TPI_INPUT_FMT_REG 0x09
#define TPI_OUTPUT_FMT_REG 0x0A
#define TPI_SYS_CTRL_REG 0x1A
#define TPI_PWR_STAT_REG 0x1E
#define TPI_AUDIO_HANDING_REG 0x25
#define TPI_AUDIO_INTF_REG 0x26
#define TPI_AUDIO_FREQ_REG 0x27
#define TPI_SET_PAGE_REG 0xBC
#define TPI_SET_OFFSET_REG 0xBD
#define TPI_RW_ACCESS_REG 0xBE
#define TPI_TRANS_MODE_REG 0xC7
#define TPI_INBUS_CLOCK_RATIO_1 (1 << 6)
#define TPI_INBUS_FULL_PIXEL_WIDE (1 << 5)
#define TPI_INBUS_RISING_EDGE (1 << 4)
#define TPI_INPUT_CLR_DEPTH_8BIT (0 << 6)
#define TPI_INPUT_VRANGE_EXPAN_AUTO (0 << 2)
#define TPI_INPUT_CLR_RGB (0 << 0)
#define TPI_OUTPUT_CLR_DEPTH_8BIT (0 << 6)
#define TPI_OUTPUT_VRANGE_COMPRE_AUTO (0 << 2)
#define TPI_OUTPUT_CLR_HDMI_RGB (0 << 0)
#define TPI_SYS_TMDS_OUTPUT (0 << 4)
#define TPI_SYS_AV_NORAML (0 << 3)
#define TPI_SYS_AV_MUTE (1 << 3)
#define TPI_SYS_DVI_MODE (0 << 0)
#define TPI_SYS_HDMI_MODE (1 << 0)
#define TPI_PWR_STAT_MASK (3 << 0)
#define TPI_PWR_STAT_D0 (0 << 0)
#define TPI_AUDIO_PASS_BASIC (0 << 0)
#define TPI_AUDIO_INTF_I2S (2 << 6)
#define TPI_AUDIO_INTF_NORMAL (0 << 4)
#define TPI_AUDIO_TYPE_PCM (1 << 0)
#define TPI_AUDIO_SAMP_SIZE_16BIT (1 << 6)
#define TPI_AUDIO_SAMP_FREQ_44K (2 << 3)
#define TPI_SET_PAGE_SII9022A 0x01
#define TPI_SET_OFFSET_SII9022A 0x82
#define TPI_RW_EN_SRC_TERMIN (1 << 0)
#define TPI_TRANS_MODE_ENABLE (0 << 7)
/* Programming of Silicon SIi9022a HDMI Transmitter */
int dcu_set_dvi_encoder(struct fb_videomode *videomode)
{
u8 temp;
u16 temp1, temp2;
u32 temp3;
#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
int ret;
ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM,
CONFIG_SYS_I2C_DVI_ADDR,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
CONFIG_SYS_I2C_DVI_BUS_NUM);
return ret;
}
/* Enable TPI transmitter mode */
temp = TPI_TRANS_MODE_ENABLE;
dm_i2c_write(dev, TPI_TRANS_MODE_REG, &temp, 1);
/* Enter into D0 state, full operation */
dm_i2c_read(dev, TPI_PWR_STAT_REG, &temp, 1);
temp &= ~TPI_PWR_STAT_MASK;
temp |= TPI_PWR_STAT_D0;
dm_i2c_write(dev, TPI_PWR_STAT_REG, &temp, 1);
/* Enable source termination */
temp = TPI_SET_PAGE_SII9022A;
dm_i2c_write(dev, TPI_SET_PAGE_REG, &temp, 1);
temp = TPI_SET_OFFSET_SII9022A;
dm_i2c_write(dev, TPI_SET_OFFSET_REG, &temp, 1);
dm_i2c_read(dev, TPI_RW_ACCESS_REG, &temp, 1);
temp |= TPI_RW_EN_SRC_TERMIN;
dm_i2c_write(dev, TPI_RW_ACCESS_REG, &temp, 1);
/* Set TPI system control */
temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE;
dm_i2c_write(dev, TPI_SYS_CTRL_REG, &temp, 1);
/* Set pixel clock */
temp1 = PICOS2KHZ(videomode->pixclock) / 10;
temp = (u8)(temp1 & 0xFF);
dm_i2c_write(dev, PIXEL_CLK_LSB_REG, &temp, 1);
temp = (u8)(temp1 >> 8);
dm_i2c_write(dev, PIXEL_CLK_MSB_REG, &temp, 1);
/* Set total pixels per line */
temp1 = videomode->hsync_len + videomode->left_margin +
videomode->xres + videomode->right_margin;
temp = (u8)(temp1 & 0xFF);
dm_i2c_write(dev, TOTAL_PIXELS_LSB_REG, &temp, 1);
temp = (u8)(temp1 >> 8);
dm_i2c_write(dev, TOTAL_PIXELS_MSB_REG, &temp, 1);
/* Set total lines */
temp2 = videomode->vsync_len + videomode->upper_margin +
videomode->yres + videomode->lower_margin;
temp = (u8)(temp2 & 0xFF);
dm_i2c_write(dev, TOTAL_LINES_LSB_REG, &temp, 1);
temp = (u8)(temp2 >> 8);
dm_i2c_write(dev, TOTAL_LINES_MSB_REG, &temp, 1);
/* Set vertical frequency in Hz */
temp3 = temp1 * temp2;
temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3;
temp1 = (u16)temp3 * 100;
temp = (u8)(temp1 & 0xFF);
dm_i2c_write(dev, VERT_FREQ_LSB_REG, &temp, 1);
temp = (u8)(temp1 >> 8);
dm_i2c_write(dev, VERT_FREQ_MSB_REG, &temp, 1);
/* Set TPI input bus and pixel repetition data */
temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE |
TPI_INBUS_RISING_EDGE;
dm_i2c_write(dev, TPI_INBUS_FMT_REG, &temp, 1);
/* Set TPI AVI Input format data */
temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO |
TPI_INPUT_CLR_RGB;
dm_i2c_write(dev, TPI_INPUT_FMT_REG, &temp, 1);
/* Set TPI AVI Output format data */
temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO |
TPI_OUTPUT_CLR_HDMI_RGB;
dm_i2c_write(dev, TPI_OUTPUT_FMT_REG, &temp, 1);
/* Set TPI audio configuration write data */
temp = TPI_AUDIO_PASS_BASIC;
dm_i2c_write(dev, TPI_AUDIO_HANDING_REG, &temp, 1);
temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL |
TPI_AUDIO_TYPE_PCM;
dm_i2c_write(dev, TPI_AUDIO_INTF_REG, &temp, 1);
temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K;
dm_i2c_write(dev, TPI_AUDIO_FREQ_REG, &temp, 1);
#else
i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
/* Enable TPI transmitter mode */
temp = TPI_TRANS_MODE_ENABLE;
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_TRANS_MODE_REG, 1, &temp, 1);
/* Enter into D0 state, full operation */
i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1);
temp &= ~TPI_PWR_STAT_MASK;
temp |= TPI_PWR_STAT_D0;
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_PWR_STAT_REG, 1, &temp, 1);
/* Enable source termination */
temp = TPI_SET_PAGE_SII9022A;
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_PAGE_REG, 1, &temp, 1);
temp = TPI_SET_OFFSET_SII9022A;
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SET_OFFSET_REG, 1, &temp, 1);
i2c_read(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1);
temp |= TPI_RW_EN_SRC_TERMIN;
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_RW_ACCESS_REG, 1, &temp, 1);
/* Set TPI system control */
temp = TPI_SYS_TMDS_OUTPUT | TPI_SYS_AV_NORAML | TPI_SYS_DVI_MODE;
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_SYS_CTRL_REG, 1, &temp, 1);
/* Set pixel clock */
temp1 = PICOS2KHZ(videomode->pixclock) / 10;
temp = (u8)(temp1 & 0xFF);
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_LSB_REG, 1, &temp, 1);
temp = (u8)(temp1 >> 8);
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, PIXEL_CLK_MSB_REG, 1, &temp, 1);
/* Set total pixels per line */
temp1 = videomode->hsync_len + videomode->left_margin +
videomode->xres + videomode->right_margin;
temp = (u8)(temp1 & 0xFF);
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_LSB_REG, 1, &temp, 1);
temp = (u8)(temp1 >> 8);
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_PIXELS_MSB_REG, 1, &temp, 1);
/* Set total lines */
temp2 = videomode->vsync_len + videomode->upper_margin +
videomode->yres + videomode->lower_margin;
temp = (u8)(temp2 & 0xFF);
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_LSB_REG, 1, &temp, 1);
temp = (u8)(temp2 >> 8);
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TOTAL_LINES_MSB_REG, 1, &temp, 1);
/* Set vertical frequency in Hz */
temp3 = temp1 * temp2;
temp3 = (PICOS2KHZ(videomode->pixclock) * 1000) / temp3;
temp1 = (u16)temp3 * 100;
temp = (u8)(temp1 & 0xFF);
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_LSB_REG, 1, &temp, 1);
temp = (u8)(temp1 >> 8);
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, VERT_FREQ_MSB_REG, 1, &temp, 1);
/* Set TPI input bus and pixel repetition data */
temp = TPI_INBUS_CLOCK_RATIO_1 | TPI_INBUS_FULL_PIXEL_WIDE |
TPI_INBUS_RISING_EDGE;
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INBUS_FMT_REG, 1, &temp, 1);
/* Set TPI AVI Input format data */
temp = TPI_INPUT_CLR_DEPTH_8BIT | TPI_INPUT_VRANGE_EXPAN_AUTO |
TPI_INPUT_CLR_RGB;
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_INPUT_FMT_REG, 1, &temp, 1);
/* Set TPI AVI Output format data */
temp = TPI_OUTPUT_CLR_DEPTH_8BIT | TPI_OUTPUT_VRANGE_COMPRE_AUTO |
TPI_OUTPUT_CLR_HDMI_RGB;
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_OUTPUT_FMT_REG, 1, &temp, 1);
/* Set TPI audio configuration write data */
temp = TPI_AUDIO_PASS_BASIC;
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_HANDING_REG, 1, &temp, 1);
temp = TPI_AUDIO_INTF_I2S | TPI_AUDIO_INTF_NORMAL |
TPI_AUDIO_TYPE_PCM;
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_INTF_REG, 1, &temp, 1);
temp = TPI_AUDIO_SAMP_SIZE_16BIT | TPI_AUDIO_SAMP_FREQ_44K;
i2c_write(CONFIG_SYS_I2C_DVI_ADDR, TPI_AUDIO_FREQ_REG, 1, &temp, 1);
#endif
return 0;
}

12
board/freescale/common/dcu_sii9022a.h
View file

@ -1,12 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*/
#ifndef __DCU_HDMI_SII9022A__
#define __DCU_HDMI_SII9022A__
/* Programming of Silicon SII9022A connector HDMI Transmitter*/
int dcu_set_dvi_encoder(struct fb_videomode *videomode);
#endif

217
board/freescale/common/diu_ch7301.c
View file

@ -1,217 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
* Authors: Priyanka Jain <Priyanka.Jain@freescale.com>
* Wang Dongsheng <dongsheng.wang@freescale.com>
*
* This file is copied and modified from the original t1040qds/diu.c.
* Encoder can be used in T104x and LSx Platform.
*/
#include <common.h>
#include <stdio_dev.h>
#include <i2c.h>
#include <linux/delay.h>
#define I2C_DVI_INPUT_DATA_FORMAT_REG 0x1F
#define I2C_DVI_PLL_CHARGE_CNTL_REG 0x33
#define I2C_DVI_PLL_DIVIDER_REG 0x34
#define I2C_DVI_PLL_SUPPLY_CNTL_REG 0x35
#define I2C_DVI_PLL_FILTER_REG 0x36
#define I2C_DVI_TEST_PATTERN_REG 0x48
#define I2C_DVI_POWER_MGMT_REG 0x49
#define I2C_DVI_LOCK_STATE_REG 0x4D
#define I2C_DVI_SYNC_POLARITY_REG 0x56
/*
* Set VSYNC/HSYNC to active high. This is polarity of sync signals
* from DIU->DVI. The DIU default is active igh, so DVI is set to
* active high.
*/
#define I2C_DVI_INPUT_DATA_FORMAT_VAL 0x98
#define I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL 0x06
#define I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL 0x26
#define I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL 0xA0
#define I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL 0x08
#define I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL 0x16
#define I2C_DVI_PLL_FILTER_LOW_SPEED_VAL 0x60
/* Clear test pattern */
#define I2C_DVI_TEST_PATTERN_VAL 0x18
/* Exit Power-down mode */
#define I2C_DVI_POWER_MGMT_VAL 0xC0
/* Monitor polarity is handled via DVI Sync Polarity Register */
#define I2C_DVI_SYNC_POLARITY_VAL 0x00
/* Programming of HDMI Chrontel CH7301 connector */
int diu_set_dvi_encoder(unsigned int pixclock)
{
int ret;
u8 temp;
temp = I2C_DVI_TEST_PATTERN_VAL;
#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
ret = i2c_get_chip_for_busnum(CONFIG_SYS_I2C_DVI_BUS_NUM,
CONFIG_SYS_I2C_DVI_ADDR,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
CONFIG_SYS_I2C_DVI_BUS_NUM);
return ret;
}
ret = dm_i2c_write(dev, I2C_DVI_TEST_PATTERN_REG, &temp, 1);
if (ret) {
puts("I2C: failed to select proper dvi test pattern\n");
return ret;
}
temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
ret = dm_i2c_write(dev, I2C_DVI_INPUT_DATA_FORMAT_REG, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi input data format\n");
return ret;
}
/* Set Sync polarity register */
temp = I2C_DVI_SYNC_POLARITY_VAL;
ret = dm_i2c_write(dev, I2C_DVI_SYNC_POLARITY_REG, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi syc polarity\n");
return ret;
}
/* Set PLL registers based on pixel clock rate*/
if (pixclock > 65000000) {
temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll charge_cntl\n");
return ret;
}
temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll divider\n");
return ret;
}
temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll filter\n");
return ret;
}
} else {
temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
ret = dm_i2c_write(dev, I2C_DVI_PLL_CHARGE_CNTL_REG, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll charge_cntl\n");
return ret;
}
temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
ret = dm_i2c_write(dev, I2C_DVI_PLL_DIVIDER_REG, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll divider\n");
return ret;
}
temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
ret = dm_i2c_write(dev, I2C_DVI_PLL_FILTER_REG, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll filter\n");
return ret;
}
}
temp = I2C_DVI_POWER_MGMT_VAL;
ret = dm_i2c_write(dev, I2C_DVI_POWER_MGMT_REG, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi power mgmt\n");
return ret;
}
#else
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_TEST_PATTERN_REG, 1,
&temp, 1);
if (ret) {
puts("I2C: failed to select proper dvi test pattern\n");
return ret;
}
temp = I2C_DVI_INPUT_DATA_FORMAT_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_INPUT_DATA_FORMAT_REG,
1, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi input data format\n");
return ret;
}
/* Set Sync polarity register */
temp = I2C_DVI_SYNC_POLARITY_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_SYNC_POLARITY_REG, 1,
&temp, 1);
if (ret) {
puts("I2C: failed to select dvi syc polarity\n");
return ret;
}
/* Set PLL registers based on pixel clock rate*/
if (pixclock > 65000000) {
temp = I2C_DVI_PLL_CHARGE_CNTL_HIGH_SPEED_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll charge_cntl\n");
return ret;
}
temp = I2C_DVI_PLL_DIVIDER_HIGH_SPEED_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll divider\n");
return ret;
}
temp = I2C_DVI_PLL_FILTER_HIGH_SPEED_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll filter\n");
return ret;
}
} else {
temp = I2C_DVI_PLL_CHARGE_CNTL_LOW_SPEED_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
I2C_DVI_PLL_CHARGE_CNTL_REG, 1, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll charge_cntl\n");
return ret;
}
temp = I2C_DVI_PLL_DIVIDER_LOW_SPEED_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
I2C_DVI_PLL_DIVIDER_REG, 1, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll divider\n");
return ret;
}
temp = I2C_DVI_PLL_FILTER_LOW_SPEED_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR,
I2C_DVI_PLL_FILTER_REG, 1, &temp, 1);
if (ret) {
puts("I2C: failed to select dvi pll filter\n");
return ret;
}
}
temp = I2C_DVI_POWER_MGMT_VAL;
ret = i2c_write(CONFIG_SYS_I2C_DVI_ADDR, I2C_DVI_POWER_MGMT_REG, 1,
&temp, 1);
if (ret) {
puts("I2C: failed to select dvi power mgmt\n");
return ret;
}
#endif
udelay(500);
return 0;
}

12
board/freescale/common/diu_ch7301.h
View file

@ -1,12 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*/
#ifndef __DIU_HDMI_CH7301__
#define __DIU_HDMI_CH7301__
/* Programming of HDMI Chrontel CH7301 connector */
int diu_set_dvi_encoder(unsigned int pixclock);
#endif

1
board/freescale/ls1021aiot/Makefile
View file

@ -3,5 +3,4 @@
# Copyright 2016 Freescale Semiconductor, Inc.
obj-y += ls1021aiot.o
obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
obj-$(CONFIG_ARMV7_PSCI) += psci.o

48
board/freescale/ls1021aiot/dcu.c
View file

@ -1,48 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2016 Freescale Semiconductor, Inc.
*
* FSL DCU Framebuffer driver
*/
#include <common.h>
#include <fsl_dcu_fb.h>
#include <asm/global_data.h>
#include "div64.h"
#include "../common/dcu_sii9022a.h"
DECLARE_GLOBAL_DATA_PTR;
unsigned int dcu_set_pixel_clock(unsigned int pixclock)
{
unsigned long long div;
div = (unsigned long long)(gd->bus_clk / 1000);
div *= (unsigned long long)pixclock;
do_div(div, 1000000000);
return div;
}
int platform_dcu_init(struct fb_info *fbinfo,
unsigned int xres, unsigned int yres,
const char *port,
struct fb_videomode *dcu_fb_videomode)
{
const char *name;
unsigned int pixel_format;
if (strncmp(port, "twr_lcd", 4) == 0) {
name = "TWR_LCD_RGB card";
} else {
name = "HDMI";
dcu_set_dvi_encoder(dcu_fb_videomode);
}
printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
pixel_format = 32;
fsl_dcu_init(fbinfo, xres, yres, pixel_format);
return 0;
}

1
board/freescale/ls1021aqds/Makefile
View file

@ -7,5 +7,4 @@
obj-y += ls1021aqds.o
obj-y += ddr.o
obj-y += eth.o
obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
obj-$(CONFIG_ARMV7_PSCI) += psci.o

110
board/freescale/ls1021aqds/dcu.c
View file

@ -1,110 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2019 NXP
*
* FSL DCU Framebuffer driver
*/
#include <asm/global_data.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_dcu_fb.h>
#include <i2c.h>
#include "../common/i2c_mux.h"
#include "div64.h"
#include "../common/diu_ch7301.h"
#include "ls1021aqds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
unsigned int dcu_set_pixel_clock(unsigned int pixclock)
{
unsigned long long div;
div = (unsigned long long)(gd->bus_clk / 1000);
div *= (unsigned long long)pixclock;
do_div(div, 1000000000);
return div;
}
int platform_dcu_init(struct fb_info *fbinfo,
unsigned int xres,
unsigned int yres,
const char *port,
struct fb_videomode *dcu_fb_videomode)
{
const char *name;
unsigned int pixel_format;
int ret;
u8 ch;
/* Mux I2C3+I2C4 as HSYNC+VSYNC */
#if CONFIG_IS_ENABLED(DM_I2C)
struct udevice *dev;
/* QIXIS device mount on I2C1 bus*/
ret = i2c_get_chip_for_busnum(0, CONFIG_SYS_I2C_QIXIS_ADDR,
1, &dev);
if (ret) {
printf("%s: Cannot find udev for a bus %d\n", __func__,
0);
return ret;
}
ret = dm_i2c_read(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
if (ret) {
printf("Error: failed to read I2C @%02x\n",
CONFIG_SYS_I2C_QIXIS_ADDR);
return ret;
}
ch &= 0x1F;
ch |= 0xA0;
ret = dm_i2c_write(dev, QIXIS_DCU_BRDCFG5, &ch, 1);
#else
ret = i2c_read(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
1, &ch, 1);
if (ret) {
printf("Error: failed to read I2C @%02x\n",
CONFIG_SYS_I2C_QIXIS_ADDR);
return ret;
}
ch &= 0x1F;
ch |= 0xA0;
ret = i2c_write(CONFIG_SYS_I2C_QIXIS_ADDR, QIXIS_DCU_BRDCFG5,
1, &ch, 1);
#endif
if (ret) {
printf("Error: failed to write I2C @%02x\n",
CONFIG_SYS_I2C_QIXIS_ADDR);
return ret;
}
if (strncmp(port, "hdmi", 4) == 0) {
unsigned long pixval;
name = "HDMI";
pixval = 1000000000 / dcu_fb_videomode->pixclock;
pixval *= 1000;
#if !CONFIG_IS_ENABLED(DM_I2C)
i2c_set_bus_num(CONFIG_SYS_I2C_DVI_BUS_NUM);
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_CH7301,
CONFIG_SYS_I2C_DVI_BUS_NUM);
diu_set_dvi_encoder(pixval);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT,
CONFIG_SYS_I2C_DVI_BUS_NUM);
} else {
return 0;
}
printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
pixel_format = 32;
fsl_dcu_init(fbinfo, xres, yres, pixel_format);
return 0;
}

1
board/freescale/ls1021atwr/Makefile
View file

@ -5,5 +5,4 @@
#
obj-y += ls1021atwr.o
obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o
obj-$(CONFIG_ARMV7_PSCI) += psci.o

48
board/freescale/ls1021atwr/dcu.c
View file

@ -1,48 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* FSL DCU Framebuffer driver
*/
#include <common.h>
#include <fsl_dcu_fb.h>
#include <asm/global_data.h>
#include "div64.h"
#include "../common/dcu_sii9022a.h"
DECLARE_GLOBAL_DATA_PTR;
unsigned int dcu_set_pixel_clock(unsigned int pixclock)
{
unsigned long long div;
div = (unsigned long long)(gd->bus_clk / 1000);
div *= (unsigned long long)pixclock;
do_div(div, 1000000000);
return div;
}
int platform_dcu_init(struct fb_info *fbinfo,
unsigned int xres, unsigned int yres,
const char *port,
struct fb_videomode *dcu_fb_videomode)
{
const char *name;
unsigned int pixel_format;
if (strncmp(port, "twr_lcd", 4) == 0) {
name = "TWR_LCD_RGB card";
} else {
name = "HDMI";
dcu_set_dvi_encoder(dcu_fb_videomode);
}
printf("DCU: Switching to %s monitor @ %ux%u\n", name, xres, yres);
pixel_format = 32;
fsl_dcu_init(fbinfo, xres, yres, pixel_format);
return 0;
}

1
board/freescale/mx51evk/Makefile
View file

@ -5,4 +5,3 @@
# (C) Copyright 2009 Freescale Semiconductor, Inc.
obj-y += mx51evk.o
obj-$(CONFIG_VIDEO) += mx51evk_video.o

1
board/freescale/mx53loco/Makefile
View file

@ -4,4 +4,3 @@
# Jason Liu <r64343@freescale.com>
obj-y += mx53loco.o
obj-$(CONFIG_VIDEO) += mx53loco_video.o

1
board/freescale/t104xrdb/Makefile
View file

@ -8,7 +8,6 @@ else
obj-y += t104xrdb.o
obj-y += cpld.o
obj-y += eth.o
obj-$(CONFIG_FSL_DIU_FB)+= diu.o
endif
obj-y += ddr.o
obj-y += law.o

84
board/freescale/t104xrdb/diu.c
View file

@ -1,84 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Author: Priyanka Jain <Priyanka.Jain@freescale.com>
*/
#include <clock_legacy.h>
#include <asm/io.h>
#include <common.h>
#include <command.h>
#include <fsl_diu_fb.h>
#include <linux/ctype.h>
#include <video_fb.h>
#include "../common/diu_ch7301.h"
#include "cpld.h"
#include "t104xrdb.h"
/*
* DIU Area Descriptor
*
* Note that we need to byte-swap the value before it's written to the AD
* register. So even though the registers don't look like they're in the same
* bit positions as they are on the MPC8610, the same value is written to the
* AD register on the MPC8610 and on the P1022.
*/
#define AD_BYTE_F 0x10000000
#define AD_ALPHA_C_SHIFT 25
#define AD_BLUE_C_SHIFT 23
#define AD_GREEN_C_SHIFT 21
#define AD_RED_C_SHIFT 19
#define AD_PIXEL_S_SHIFT 16
#define AD_COMP_3_SHIFT 12
#define AD_COMP_2_SHIFT 8
#define AD_COMP_1_SHIFT 4
#define AD_COMP_0_SHIFT 0
void diu_set_pixel_clock(unsigned int pixclock)
{
unsigned long speed_ccb, temp;
u32 pixval;
int ret;
speed_ccb = get_bus_freq(0);
temp = 1000000000 / pixclock;
temp *= 1000;
pixval = speed_ccb / temp;
/* Program HDMI encoder */
ret = diu_set_dvi_encoder(temp);
if (ret) {
puts("Failed to set DVI encoder\n");
return;
}
/* Program pixel clock */
out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
((pixval << PXCK_BITS_START) & PXCK_MASK));
/* enable clock*/
out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
((pixval << PXCK_BITS_START) & PXCK_MASK));
}
int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
{
u32 pixel_format;
u8 sw;
/*Configure Display ouput port as HDMI*/
sw = CPLD_READ(sfp_ctl_status);
CPLD_WRITE(sfp_ctl_status , sw & ~(CPLD_DIU_SEL_DFP));
pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
printf("DIU: Switching to monitor DVI @ %ux%u\n", xres, yres);
return fsl_diu_init(xres, yres, pixel_format, 0);
}

23
board/kosagi/novena/novena_spl.c
View file

@ -379,30 +379,7 @@ static void novena_spl_setup_iomux_uart(void)
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
}
/*
* Video
*/
#ifdef CONFIG_VIDEO
static iomux_v3_cfg_t hdmi_pads[] = {
/* "Ghost HPD" pin */
MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* LCD_PWR_CTL */
MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* LCD_BL_ON */
MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
/* GPIO_PWM1 */
MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static void novena_spl_setup_iomux_video(void)
{
imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads));
gpio_direction_input(NOVENA_HDMI_GHOST_HPD);
}
#else
static inline void novena_spl_setup_iomux_video(void) {}
#endif
/*
* SPL boots from uSDHC card

3
board/siemens/common/board.c
View file

@ -96,9 +96,6 @@ int board_init(void)
#ifdef CONFIG_NAND_CS_INIT
board_nand_cs_init();
#endif
#ifdef CONFIG_VIDEO
board_video_init();
#endif
return 0;
}

7
board/siemens/common/factoryset.c
View file

@ -275,13 +275,6 @@ int factoryset_read_eeprom(int i2c_addr)
}
printf("DFU USB: VID = 0x%4x, PID = 0x%4x\n", factory_dat.usb_vendor_id,
factory_dat.usb_product_id);
#endif
#if defined(CONFIG_VIDEO)
if (0 <= get_factory_record_val(cp, size, (uchar *)"DISP1",
(uchar *)"name", factory_dat.disp_name,
MAX_STRING_LENGTH)) {
debug("display name: %s\n", factory_dat.disp_name);
}
#endif
if (0 <= get_factory_record_val(cp, size, (uchar *)"DEV",
(uchar *)"num", factory_dat.serial,

3
board/siemens/common/factoryset.h
View file

@ -17,9 +17,6 @@ struct factorysetcontainer {
int usb_vendor_id;
int usb_product_id;
int pxm50;
#if defined(CONFIG_VIDEO)
unsigned char disp_name[MAX_STRING_LENGTH];
#endif
unsigned char serial[MAX_STRING_LENGTH];
int version;
uchar asn[MAX_STRING_LENGTH];

189
board/siemens/pxm2/board.c
View file

@ -28,7 +28,6 @@
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include "../../../drivers/video/da8xx-fb.h"
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
@ -243,194 +242,6 @@ int board_eth_init(struct bd_info *bis)
}
#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
static struct da8xx_panel lcd_panels[] = {
/* AUO G156XW01 V1 */
[0] = {
.name = "AUO_G156XW01_V1",
.width = 1376,
.height = 768,
.hfp = 14,
.hbp = 64,
.hsw = 56,
.vfp = 1,
.vbp = 28,
.vsw = 3,
.pxl_clk = 60000000,
.invert_pxl_clk = 0,
},
/* AUO B101EVN06 V0 */
[1] = {
.name = "AUO_B101EVN06_V0",
.width = 1280,
.height = 800,
.hfp = 52,
.hbp = 84,
.hsw = 36,
.vfp = 3,
.vbp = 14,
.vsw = 6,
.pxl_clk = 60000000,
.invert_pxl_clk = 0,
},
/*
* Settings from factoryset
* stored in EEPROM
*/
[2] = {
.name = "factoryset",
.width = 0,
.height = 0,
.hfp = 0,
.hbp = 0,
.hsw = 0,
.vfp = 0,
.vbp = 0,
.vsw = 0,
.pxl_clk = 60000000,
.invert_pxl_clk = 0,
},
};
static const struct display_panel disp_panel = {
WVGA,
32,
16,
COLOR_ACTIVE,
};
static const struct lcd_ctrl_config lcd_cfg = {
&disp_panel,
.ac_bias = 255,
.ac_bias_intrpt = 0,
.dma_burst_sz = 16,
.bpp = 32,
.fdd = 0x80,
.tft_alt_mode = 0,
.stn_565_mode = 0,
.mono_8bit_mode = 0,
.invert_line_clock = 1,
.invert_frm_clock = 1,
.sync_edge = 0,
.sync_ctrl = 1,
.raster_order = 0,
};
static int set_gpio(int gpio, int state)
{
gpio_request(gpio, "temp");
gpio_direction_output(gpio, state);
gpio_set_value(gpio, state);
gpio_free(gpio);
return 0;
}
static int enable_backlight(void)
{
set_gpio(BOARD_LCD_POWER, 1);
set_gpio(BOARD_BACK_LIGHT, 1);
set_gpio(BOARD_TOUCH_POWER, 1);
return 0;
}
static int enable_pwm(void)
{
struct pwmss_regs *pwmss = (struct pwmss_regs *)PWMSS0_BASE;
struct pwmss_ecap_regs *ecap;
int ticks = PWM_TICKS;
int duty = PWM_DUTY;
ecap = (struct pwmss_ecap_regs *)AM33XX_ECAP0_BASE;
/* enable clock */
setbits_le32(&pwmss->clkconfig, ECAP_CLK_EN);
/* TimeStam Counter register */
writel(0xdb9, &ecap->tsctr);
/* config period */
writel(ticks - 1, &ecap->cap3);
writel(ticks - 1, &ecap->cap1);
setbits_le16(&ecap->ecctl2,
(ECTRL2_MDSL_ECAP | ECTRL2_SYNCOSEL_MASK | 0xd0));
/* config duty */
writel(duty, &ecap->cap2);
writel(duty, &ecap->cap4);
/* start */
setbits_le16(&ecap->ecctl2, ECTRL2_CTRSTP_FREERUN);
return 0;
}
static struct dpll_regs dpll_lcd_regs = {
.cm_clkmode_dpll = CM_WKUP + 0x98,
.cm_idlest_dpll = CM_WKUP + 0x48,
.cm_clksel_dpll = CM_WKUP + 0x54,
};
/* no console on this board */
int board_cfb_skip(void)
{
return 1;
}
#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
#define PLL_GET_N(v) (v & 0x7f)
static int get_clk(struct dpll_regs *dpll_regs)
{
unsigned int val;
unsigned int m, n;
int f = 0;
val = readl(dpll_regs->cm_clksel_dpll);
m = PLL_GET_M(val);
n = PLL_GET_N(val);
f = (m * V_OSCK) / n;
return f;
};
int clk_get(int clk)
{
return get_clk(&dpll_lcd_regs);
};
static int conf_disp_pll(int m, int n)
{
struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL;
struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
u32 *const clk_domains[] = {
&cmper->lcdclkctrl,
0
};
u32 *const clk_modules_explicit_en[] = {
&cmper->lcdclkctrl,
&cmper->lcdcclkstctrl,
&cmper->epwmss0clkctrl,
0
};
do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
writel(0x0, &cmdpll->clklcdcpixelclk);
do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
return 0;
}
static int board_video_init(void)
{
conf_disp_pll(24, 1);
if (factory_dat.pxm50)
da8xx_video_init(&lcd_panels[0], &lcd_cfg, lcd_cfg.bpp);
else
da8xx_video_init(&lcd_panels[1], &lcd_cfg, lcd_cfg.bpp);
enable_pwm();
enable_backlight();
return 0;
}
#endif
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{

247
board/siemens/rut/board.c
View file

@ -37,7 +37,6 @@
#include <linux/delay.h>
#include "board.h"
#include "../common/factoryset.h"
#include "../../../drivers/video/da8xx-fb.h"
/*
* Read header information from EEPROM into global structure.
@ -224,252 +223,6 @@ void hw_watchdog_init(void)
}
#endif /* defined(CONFIG_HW_WATCHDOG) */
#if defined(CONFIG_VIDEO) && !defined(CONFIG_SPL_BUILD)
static struct da8xx_panel lcd_panels[] = {
/* FORMIKE, 4.3", 480x800, KWH043MC17-F01 */
[0] = {
.name = "KWH043MC17-F01",
.width = 480,
.height = 800,
.hfp = 50, /* no spec, "don't care" values */
.hbp = 50,
.hsw = 50,
.vfp = 50,
.vbp = 50,
.vsw = 50,
.pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
.invert_pxl_clk = 1,
},
/* FORMIKE, 4.3", 480x800, KWH043ST20-F01 */
[1] = {
.name = "KWH043ST20-F01",
.width = 480,
.height = 800,
.hfp = 50, /* no spec, "don't care" values */
.hbp = 50,
.hsw = 50,
.vfp = 50,
.vbp = 50,
.vsw = 50,
.pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
.invert_pxl_clk = 1,
},
/* Multi-Inno, 4.3", 480x800, MI0430VT-1 */
[2] = {
.name = "MI0430VT-1",
.width = 480,
.height = 800,
.hfp = 50, /* no spec, "don't care" values */
.hbp = 50,
.hsw = 50,
.vfp = 50,
.vbp = 50,
.vsw = 50,
.pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
.invert_pxl_clk = 1,
},
};
static const struct display_panel disp_panels[] = {
[0] = {
WVGA,
16, /* RGB 888 */
16,
COLOR_ACTIVE,
},
[1] = {
WVGA,
16, /* RGB 888 */
16,
COLOR_ACTIVE,
},
[2] = {
WVGA,
24, /* RGB 888 */
16,
COLOR_ACTIVE,
},
};
static const struct lcd_ctrl_config lcd_cfgs[] = {
[0] = {
&disp_panels[0],
.ac_bias = 255,
.ac_bias_intrpt = 0,
.dma_burst_sz = 16,
.bpp = 16,
.fdd = 0x80,
.tft_alt_mode = 0,
.stn_565_mode = 0,
.mono_8bit_mode = 0,
.invert_line_clock = 1,
.invert_frm_clock = 1,
.sync_edge = 0,
.sync_ctrl = 1,
.raster_order = 0,
},
[1] = {
&disp_panels[1],
.ac_bias = 255,
.ac_bias_intrpt = 0,
.dma_burst_sz = 16,
.bpp = 16,
.fdd = 0x80,
.tft_alt_mode = 0,
.stn_565_mode = 0,
.mono_8bit_mode = 0,
.invert_line_clock = 1,
.invert_frm_clock = 1,
.sync_edge = 0,
.sync_ctrl = 1,
.raster_order = 0,
},
[2] = {
&disp_panels[2],
.ac_bias = 255,
.ac_bias_intrpt = 0,
.dma_burst_sz = 16,
.bpp = 24,
.fdd = 0x80,
.tft_alt_mode = 0,
.stn_565_mode = 0,
.mono_8bit_mode = 0,
.invert_line_clock = 1,
.invert_frm_clock = 1,
.sync_edge = 0,
.sync_ctrl = 1,
.raster_order = 0,
},
};
/* no console on this board */
int board_cfb_skip(void)
{
return 1;
}
#define PLL_GET_M(v) ((v >> 8) & 0x7ff)
#define PLL_GET_N(v) (v & 0x7f)
static struct dpll_regs dpll_lcd_regs = {
.cm_clkmode_dpll = CM_WKUP + 0x98,
.cm_idlest_dpll = CM_WKUP + 0x48,
.cm_clksel_dpll = CM_WKUP + 0x54,
};
static int get_clk(struct dpll_regs *dpll_regs)
{
unsigned int val;
unsigned int m, n;
int f = 0;
val = readl(dpll_regs->cm_clksel_dpll);
m = PLL_GET_M(val);
n = PLL_GET_N(val);
f = (m * V_OSCK) / n;
return f;
};
int clk_get(int clk)
{
return get_clk(&dpll_lcd_regs);
};
static int conf_disp_pll(int m, int n)
{
struct cm_perpll *cmper = (struct cm_perpll *)CM_PER;
struct dpll_params dpll_lcd = {m, n, -1, -1, -1, -1, -1};
#if defined(DISPL_PLL_SPREAD_SPECTRUM)
struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP;
#endif
u32 *const clk_domains[] = {
&cmper->lcdclkctrl,
0
};
u32 *const clk_modules_explicit_en[] = {
&cmper->lcdclkctrl,
&cmper->lcdcclkstctrl,
&cmper->spi1clkctrl,
0
};
do_enable_clocks(clk_domains, clk_modules_explicit_en, 1);
do_setup_dpll(&dpll_lcd_regs, &dpll_lcd);
#if defined(DISPL_PLL_SPREAD_SPECTRUM)
writel(0x64, &cmwkup->resv6[3]); /* 0x50 */
writel(0x800, &cmwkup->resv6[2]); /* 0x4c */
writel(readl(&cmwkup->clkmoddplldisp) | CM_CLKMODE_DPLL_SSC_EN_MASK,
&cmwkup->clkmoddplldisp); /* 0x98 */
#endif
return 0;
}
static int set_gpio(int gpio, int state)
{
gpio_request(gpio, "temp");
gpio_direction_output(gpio, state);
gpio_set_value(gpio, state);
gpio_free(gpio);
return 0;
}
static int enable_lcd(void)
{
unsigned char buf[1];
set_gpio(BOARD_LCD_RESET, 0);
mdelay(1);
set_gpio(BOARD_LCD_RESET, 1);
mdelay(1);
/* spi lcd init */
kwh043st20_f01_spi_startup(1, 0, 5000000, SPI_MODE_0);
/* backlight on */
buf[0] = 0xf;
i2c_write(0x24, 0x7, 1, buf, 1);
buf[0] = 0x3f;
i2c_write(0x24, 0x8, 1, buf, 1);
return 0;
}
int arch_early_init_r(void)
{
enable_lcd();
return 0;
}
static int board_video_init(void)
{
int i;
int anzdisp = ARRAY_SIZE(lcd_panels);
int display = 1;
for (i = 0; i < anzdisp; i++) {
if (strncmp((const char *)factory_dat.disp_name,
lcd_panels[i].name,
strlen((const char *)factory_dat.disp_name)) == 0) {
printf("DISPLAY: %s\n", factory_dat.disp_name);
break;
}
}
if (i == anzdisp) {
i = 1;
printf("%s: %s not found, using default %s\n", __func__,
factory_dat.disp_name, lcd_panels[i].name);
}
conf_disp_pll(24, 1);
da8xx_video_init(&lcd_panels[display], &lcd_cfgs[display],
lcd_cfgs[display].bpp);
return 0;
}
#endif /* ifdef CONFIG_VIDEO */
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{

1
board/socrates/socrates.c
View file

@ -26,7 +26,6 @@
#include <fdt_support.h>
#include <asm/io.h>
#include <i2c.h>
#include <video_fb.h>
#include "upm_table.h"
DECLARE_GLOBAL_DATA_PTR;

1
board/toradex/colibri_vf/Makefile
View file

@ -3,4 +3,3 @@
# Copyright 2013 Freescale Semiconductor, Inc.
obj-y := colibri_vf.o
obj-$(CONFIG_VIDEO_FSL_DCU_FB) += dcu.o

62
board/toradex/colibri_vf/colibri_vf.c
View file

@ -19,7 +19,6 @@
#include <asm/io.h>
#include <env.h>
#include <fdt_support.h>
#include <fsl_dcu_fb.h>
#include <g_dnl.h>
#include <jffs2/load_kernel.h>
#include <mtd_node.h>
@ -205,49 +204,6 @@ static void setup_iomux_gpio(void)
}
#endif
#ifdef CONFIG_VIDEO_FSL_DCU_FB
static void setup_iomux_fsl_dcu(void)
{
static const iomux_v3_cfg_t dcu0_pads[] = {
VF610_PAD_PTE0__DCU0_HSYNC,
VF610_PAD_PTE1__DCU0_VSYNC,
VF610_PAD_PTE2__DCU0_PCLK,
VF610_PAD_PTE4__DCU0_DE,
VF610_PAD_PTE5__DCU0_R0,
VF610_PAD_PTE6__DCU0_R1,
VF610_PAD_PTE7__DCU0_R2,
VF610_PAD_PTE8__DCU0_R3,
VF610_PAD_PTE9__DCU0_R4,
VF610_PAD_PTE10__DCU0_R5,
VF610_PAD_PTE11__DCU0_R6,
VF610_PAD_PTE12__DCU0_R7,
VF610_PAD_PTE13__DCU0_G0,
VF610_PAD_PTE14__DCU0_G1,
VF610_PAD_PTE15__DCU0_G2,
VF610_PAD_PTE16__DCU0_G3,
VF610_PAD_PTE17__DCU0_G4,
VF610_PAD_PTE18__DCU0_G5,
VF610_PAD_PTE19__DCU0_G6,
VF610_PAD_PTE20__DCU0_G7,
VF610_PAD_PTE21__DCU0_B0,
VF610_PAD_PTE22__DCU0_B1,
VF610_PAD_PTE23__DCU0_B2,
VF610_PAD_PTE24__DCU0_B3,
VF610_PAD_PTE25__DCU0_B4,
VF610_PAD_PTE26__DCU0_B5,
VF610_PAD_PTE27__DCU0_B6,
VF610_PAD_PTE28__DCU0_B7,
};
imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads));
}
static void setup_tcon(void)
{
setbits_le32(TCON0_BASE_ADDR, (1 << 29));
}
#endif
static inline int is_colibri_vf61(void)
{
struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
@ -353,11 +309,6 @@ static void clock_init(void)
CCM_CSCDR3_NFC_PRE_DIV(3));
clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
CCM_CSCMR2_RMII_CLK_SEL(2));
#ifdef CONFIG_VIDEO_FSL_DCU_FB
setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK);
setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK);
#endif
}
static void mscm_init(void)
@ -378,11 +329,6 @@ int board_early_init_f(void)
setup_iomux_gpio();
#endif
#ifdef CONFIG_VIDEO_FSL_DCU_FB
setup_tcon();
setup_iomux_fsl_dcu();
#endif
return 0;
}
@ -433,9 +379,6 @@ int checkboard(void)
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
#if defined(CONFIG_VIDEO_FSL_DCU_FB) && !defined(CONFIG_DM_VIDEO)
int ret = 0;
#endif
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
static const struct node_info nodes[] = {
{ "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */
@ -445,11 +388,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
puts(" Updating MTD partitions...\n");
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
#if defined(CONFIG_VIDEO_FSL_DCU_FB) && !defined(CONFIG_DM_VIDEO)
ret = fsl_dcu_fixedfb_setup(blob);
if (ret)
return ret;
#endif
return ft_common_board_setup(blob, bd);
}

38
board/toradex/colibri_vf/dcu.c
View file

@ -1,38 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017 Toradex AG
*
* FSL DCU platform driver
*/
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <common.h>
#include <fsl_dcu_fb.h>
#include "div64.h"
unsigned int dcu_set_pixel_clock(unsigned int pixclock)
{
struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
unsigned long long div;
clrbits_le32(&ccm->cscmr1, CCM_CSCMR1_DCU0_CLK_SEL);
clrsetbits_le32(&ccm->cscdr3,
CCM_CSCDR3_DCU0_DIV_MASK | CCM_CSCDR3_DCU0_EN,
CCM_CSCDR3_DCU0_DIV(0) | CCM_CSCDR3_DCU0_EN);
div = (unsigned long long)(PLL1_PFD2_FREQ / 1000);
do_div(div, pixclock);
return div;
}
int platform_dcu_init(struct fb_info *fbinfo,
unsigned int xres,
unsigned int yres,
const char *port,
struct fb_videomode *dcu_fb_videomode)
{
fsl_dcu_init(fbinfo, xres, yres, 32);
return 0;
}

2
cmd/Kconfig
View file

@ -1786,7 +1786,7 @@ config CMD_CONITRACE
config CMD_CLS
bool "Enable clear screen command 'cls'"
depends on CFB_CONSOLE || DM_VIDEO || LCD || VIDEO
depends on DM_VIDEO || LCD || VIDEO
default y if LCD
help
Enable the 'cls' command which clears the screen contents

2
cmd/bdinfo.c
View file

@ -117,7 +117,7 @@ int do_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
bdinfo_print_num_l("fdt_size", (ulong)gd->fdt_size);
if (IS_ENABLED(CONFIG_DM_VIDEO))
show_video_info();
#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
#if defined(CONFIG_LCD)
bdinfo_print_num_l("FB base ", gd->fb_base);
#endif
#if CONFIG_IS_ENABLED(MULTI_DTB_FIT)

4
cmd/bmp.c
View file

@ -268,10 +268,8 @@ int bmp_display(ulong addr, int x, int y)
}
#elif defined(CONFIG_LCD)
ret = lcd_display_bitmap(addr, x, y);
#elif defined(CONFIG_VIDEO)
ret = video_display_bitmap(addr, x, y);
#else
# error bmp_display() requires CONFIG_LCD or CONFIG_VIDEO
# error bmp_display() requires CONFIG_LCD
#endif
if (bmp_alloc_addr)

2
cmd/cls.c
View file

@ -28,8 +28,6 @@ static int do_video_clear(struct cmd_tbl *cmdtp, int flag, int argc,
if (video_clear(dev))
return CMD_RET_FAILURE;
#endif
#elif defined(CONFIG_CFB_CONSOLE)
video_clear();
#elif defined(CONFIG_LCD)
lcd_clear();
#else

2
common/fdt_support.c
View file

@ -1725,7 +1725,7 @@ int fdt_set_status_by_pathf(void *fdt, enum fdt_status status, const char *fmt,
return fdt_set_node_status(fdt, offset, status);
}
#if defined(CONFIG_VIDEO) || defined(CONFIG_LCD)
#if defined(CONFIG_LCD)
int fdt_add_edid(void *blob, const char *compat, unsigned char *edid_buf)
{
int noff;

142
common/lcd.c
View file

@ -347,135 +347,6 @@ static void splash_align_axis(int *axis, unsigned long panel_size,
}
#endif
#ifdef CONFIG_LCD_BMP_RLE8
#define BMP_RLE8_ESCAPE 0
#define BMP_RLE8_EOL 0
#define BMP_RLE8_EOBMP 1
#define BMP_RLE8_DELTA 2
static void draw_unencoded_bitmap(ushort **fbp, uchar *bmap, ushort *cmap,
int cnt)
{
while (cnt > 0) {
*(*fbp)++ = cmap[*bmap++];
cnt--;
}
}
static void draw_encoded_bitmap(ushort **fbp, ushort c, int cnt)
{
ushort *fb = *fbp;
int cnt_8copy = cnt >> 3;
cnt -= cnt_8copy << 3;
while (cnt_8copy > 0) {
*fb++ = c;
*fb++ = c;
*fb++ = c;
*fb++ = c;
*fb++ = c;
*fb++ = c;
*fb++ = c;
*fb++ = c;
cnt_8copy--;
}
while (cnt > 0) {
*fb++ = c;
cnt--;
}
*fbp = fb;
}
/*
* Do not call this function directly, must be called from lcd_display_bitmap.
*/
static void lcd_display_rle8_bitmap(struct bmp_image *bmp, ushort *cmap,
uchar *fb, int x_off, int y_off)
{
uchar *bmap;
ulong width, height;
ulong cnt, runlen;
int x, y;
int decode = 1;
width = get_unaligned_le32(&bmp->header.width);
height = get_unaligned_le32(&bmp->header.height);
bmap = (uchar *)bmp + get_unaligned_le32(&bmp->header.data_offset);
x = 0;
y = height - 1;
while (decode) {
if (bmap[0] == BMP_RLE8_ESCAPE) {
switch (bmap[1]) {
case BMP_RLE8_EOL:
/* end of line */
bmap += 2;
x = 0;
y--;
/* 16bpix, 2-byte per pixel, width should *2 */
fb -= (width * 2 + lcd_line_length);
break;
case BMP_RLE8_EOBMP:
/* end of bitmap */
decode = 0;
break;
case BMP_RLE8_DELTA:
/* delta run */
x += bmap[2];
y -= bmap[3];
/* 16bpix, 2-byte per pixel, x should *2 */
fb = (uchar *) (lcd_base + (y + y_off - 1)
* lcd_line_length + (x + x_off) * 2);
bmap += 4;
break;
default:
/* unencoded run */
runlen = bmap[1];
bmap += 2;
if (y < height) {
if (x < width) {
if (x + runlen > width)
cnt = width - x;
else
cnt = runlen;
draw_unencoded_bitmap(
(ushort **)&fb,
bmap, cmap, cnt);
}
x += runlen;
}
bmap += runlen;
if (runlen & 1)
bmap++;
}
} else {
/* encoded run */
if (y < height) {
runlen = bmap[0];
if (x < width) {
/* aggregate the same code */
while (bmap[0] == 0xff &&
bmap[2] != BMP_RLE8_ESCAPE &&
bmap[1] == bmap[3]) {
runlen += bmap[2];
bmap += 2;
}
if (x + runlen > width)
cnt = width - x;
else
cnt = runlen;
draw_encoded_bitmap((ushort **)&fb,
cmap[bmap[1]], cnt);
}
x += runlen;
}
bmap += 2;
}
}
}
#endif
__weak void fb_put_byte(uchar **fb, uchar **from)
{
*(*fb)++ = *(*from)++;
@ -581,19 +452,6 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
case 1:
case 8: {
cmap_base = configuration_get_cmap();
#ifdef CONFIG_LCD_BMP_RLE8
u32 compression = get_unaligned_le32(&bmp->header.compression);
debug("compressed %d %d\n", compression, BMP_BI_RLE8);
if (compression == BMP_BI_RLE8) {
if (bpix != 16) {
/* TODO implement render code for bpix != 16 */
printf("Error: only support 16 bpix");
return 1;
}
lcd_display_rle8_bitmap(bmp, cmap_base, fb, x, y);
break;
}
#endif
if (bpix != 16)
byte_width = width;

4
common/stdio.c
View file

@ -367,9 +367,7 @@ int stdio_add_devices(void)
} else {
if (IS_ENABLED(CONFIG_LCD))
drv_lcd_init();
if (IS_ENABLED(CONFIG_VIDEO) ||
IS_ENABLED(CONFIG_CFB_CONSOLE) ||
IS_ENABLED(CONFIG_VIDEO_VCXK))
if (IS_ENABLED(CONFIG_VIDEO_VCXK))
drv_video_init();
}

1
configs/colibri_vf_defconfig
View file

@ -101,7 +101,6 @@ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
# CONFIG_VIDEO_BPP16 is not set
CONFIG_VIDEO_FSL_DCU_FB=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_FDT_FIXUP_PARTITIONS=y

1
configs/rpi_0_w_defconfig
View file

@ -41,6 +41,7 @@ CONFIG_DM_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
# CONFIG_VIDEO_BPP16 is not set
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_BCM2835=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
CONFIG_OF_LIBFDT_OVERLAY=y

1
configs/rpi_2_defconfig
View file

@ -42,6 +42,7 @@ CONFIG_DM_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
# CONFIG_VIDEO_BPP16 is not set
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_BCM2835=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
CONFIG_OF_LIBFDT_OVERLAY=y

1
configs/rpi_3_32b_defconfig
View file

@ -45,6 +45,7 @@ CONFIG_DM_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
# CONFIG_VIDEO_BPP16 is not set
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_BCM2835=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
CONFIG_OF_LIBFDT_OVERLAY=y

1
configs/rpi_3_b_plus_defconfig
View file

@ -44,6 +44,7 @@ CONFIG_DM_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
# CONFIG_VIDEO_BPP16 is not set
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_BCM2835=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
CONFIG_OF_LIBFDT_OVERLAY=y

1
configs/rpi_3_defconfig
View file

@ -44,6 +44,7 @@ CONFIG_DM_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
# CONFIG_VIDEO_BPP16 is not set
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_BCM2835=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
CONFIG_OF_LIBFDT_OVERLAY=y

1
configs/rpi_4_32b_defconfig
View file

@ -59,6 +59,7 @@ CONFIG_DM_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
# CONFIG_VIDEO_BPP16 is not set
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_BCM2835=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
CONFIG_ADDR_MAP=y

1
configs/rpi_4_defconfig
View file

@ -59,6 +59,7 @@ CONFIG_DM_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
# CONFIG_VIDEO_BPP16 is not set
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_BCM2835=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
CONFIG_OF_LIBFDT_OVERLAY=y

1
configs/rpi_arm64_defconfig
View file

@ -51,6 +51,7 @@ CONFIG_DM_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
# CONFIG_VIDEO_BPP16 is not set
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_BCM2835=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
CONFIG_OF_LIBFDT_OVERLAY=y

1
configs/rpi_defconfig
View file

@ -41,6 +41,7 @@ CONFIG_DM_VIDEO=y
# CONFIG_VIDEO_BPP8 is not set
# CONFIG_VIDEO_BPP16 is not set
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_BCM2835=y
CONFIG_CONSOLE_SCROLL_LINES=10
CONFIG_PHYS_TO_BUS=y
CONFIG_OF_LIBFDT_OVERLAY=y

5
doc/usage/bootmenu.rst
View file

@ -88,8 +88,3 @@ To run the bootmenu at startup add these additional settings::
CONFIG_AUTOBOOT_KEYED=y
CONFIG_BOOTDELAY=30
CONFIG_AUTOBOOT_MENU_SHOW=y
When you intend to use the bootmenu on a color frame buffer console,
make sure to additionally define::
CONFIG_CFB_CONSOLE_ANSI=y

1
drivers/pci/pci_rom.c
View file

@ -36,7 +36,6 @@
#include <pci_rom.h>
#include <vbe.h>
#include <video.h>
#include <video_fb.h>
#include <acpi/acpi_s3.h>
#include <asm/global_data.h>
#include <linux/screen_info.h>

129
drivers/video/Kconfig
View file

@ -430,6 +430,14 @@ config ATMEL_LCD_BGR555
help
Use the BGR555 output mode. Otherwise RGB565 is used.
config VIDEO_BCM2835
bool "Display support for BCM2835"
help
The graphics processor already sets up the display so this driver
simply checks the resolution and then sets up the frame buffer with
that same resolution (or as near as possible) and 32bpp depth, so
that U-Boot can access it with full colour depth.
config VIDEO_LCD_ORISETECH_OTM8009A
bool "OTM8009A DSI LCD panel support"
depends on DM_VIDEO
@ -610,21 +618,6 @@ config VIDEO_IVYBRIDGE_IGD
a special tool which configures the VGA ROM, but the graphics
resolution can be selected in U-Boot.
config VIDEO_FSL_DCU_FB
bool "Enable Freescale Display Control Unit"
depends on VIDEO || DM_VIDEO
help
This enables support for Freescale Display Control Unit (DCU4)
module found on Freescale Vybrid and QorIQ family of SoCs.
config VIDEO_FSL_DCU_MAX_FB_SIZE_MB
int "Freescale DCU framebuffer size"
depends on VIDEO_FSL_DCU_FB
default 4194304
help
Set maximum framebuffer size to be used for Freescale Display
Controller Unit (DCU4).
source "drivers/video/rockchip/Kconfig"
config VIDEO_ARM_MALIDP
@ -708,89 +701,9 @@ config VIDEO
model. Video drivers typically provide a colour text console and
cursor.
config CFB_CONSOLE
bool "Enable colour frame buffer console"
depends on VIDEO || ARCH_OMAP2PLUS
default y if VIDEO
help
Enables the colour frame buffer driver. This supports colour
output on a bitmap display from an in-memory frame buffer.
Several colour devices are supported along with various options to
adjust the supported features. The driver is implemented in
cfb_console.c
The following defines are needed (cf. smiLynxEM, i8042)
VIDEO_FB_LITTLE_ENDIAN graphic memory organisation
(default big endian)
VIDEO_HW_RECTFILL graphic chip supports
rectangle fill (cf. smiLynxEM)
VIDEO_HW_BITBLT graphic chip supports
bit-blit (cf. smiLynxEM)
VIDEO_VISIBLE_COLS visible pixel columns (cols=pitch)
VIDEO_VISIBLE_ROWS visible pixel rows
VIDEO_PIXEL_SIZE bytes per pixel
VIDEO_DATA_FORMAT graphic data format
(0-5, cf. cfb_console.c)
VIDEO_FB_ADRS framebuffer address
VIDEO_KBD_INIT_FCT keyboard int fct (i.e. rx51_kp_init())
VIDEO_TSTC_FCT test char fct (i.e. rx51_kp_tstc)
VIDEO_GETC_FCT get char fct (i.e. rx51_kp_getc)
CONFIG_VIDEO_LOGO display Linux logo in upper left corner
CONFIG_VIDEO_BMP_LOGO use bmp_logo.h instead of linux_logo.h
for logo. Requires CONFIG_VIDEO_LOGO
CONFIG_CONSOLE_EXTRA_INFO
additional board info beside
the logo
CONFIG_HIDE_LOGO_VERSION
do not display bootloader
version string
When CONFIG_CFB_CONSOLE is defined, the video console is the
default console. The serial console can be forced by setting the
environment 'console=serial'.
config CFB_CONSOLE_ANSI
bool "Support ANSI escape sequences"
depends on CFB_CONSOLE
help
This allows the colour buffer frame buffer driver to support
a limited number of ANSI escape sequences (cursor control,
erase functions and limited graphics rendition control). Normal
output from U-Boot will pass through this filter.
config VGA_AS_SINGLE_DEVICE
bool "Set the video as an output-only device"
depends on CFB_CONSOLE
default y
help
If enable the framebuffer device will be initialized as an
output-only device. The Keyboard driver will not be set up. This
may be used if you have no keyboard device, or more than one
(USB Keyboard, AT Keyboard).
config VIDEO_SW_CURSOR
bool "Enable a software cursor"
depends on CFB_CONSOLE
default y if CFB_CONSOLE
help
This draws a cursor after the last character. No blinking is
provided. This makes it possible to see the current cursor
position when entering text on the console. It is recommended to
enable this.
config CONSOLE_EXTRA_INFO
bool "Display additional board information"
depends on CFB_CONSOLE
help
Display additional board information strings that normally go to
the serial port. When this option is enabled, a board-specific
function video_get_info_str() is called to get the string for
each line of the display. The function should return the string,
which can be empty if there is nothing to display for that line.
config CONSOLE_SCROLL_LINES
int "Number of lines to scroll the console by"
depends on CFB_CONSOLE || DM_VIDEO || LCD
depends on DM_VIDEO || LCD
default 1
help
When the console need to be scrolled, this is the number of
@ -798,28 +711,6 @@ config CONSOLE_SCROLL_LINES
console jump but can help speed up operation when scrolling
is slow.
config SYS_CONSOLE_BG_COL
hex "Background colour"
depends on CFB_CONSOLE
default 0x00
help
Defines the background colour for the console. The value is from
0x00 to 0xff and the meaning depends on the graphics card.
Typically, 0x00 means black and 0xff means white. Do not set
the background and foreground to the same colour or you will see
nothing.
config SYS_CONSOLE_FG_COL
hex "Foreground colour"
depends on CFB_CONSOLE
default 0xa0
help
Defines the foreground colour for the console. The value is from
0x00 to 0xff and the meaning depends on the graphics card.
Typically, 0x00 means black and 0xff means white. Do not set
the background and foreground to the same colour or you will see
nothing.
config LCD
bool "Enable legacy LCD support"
help
@ -1017,7 +908,7 @@ config VIDEO_BMP_GZIP
config VIDEO_BMP_RLE8
bool "Run length encoded BMP image (RLE8) support"
depends on DM_VIDEO || CFB_CONSOLE
depends on DM_VIDEO
help
If this option is set, the 8-bit RLE compressed BMP images
is supported.

5
drivers/video/Makefile
View file

@ -30,9 +30,6 @@ obj-y += ti/
obj-$(CONFIG_ATMEL_HLCD) += atmel_hlcdfb.o
obj-$(CONFIG_ATMEL_LCD) += atmel_lcdfb.o
obj-$(CONFIG_CFB_CONSOLE) += cfb_console.o
obj-$(CONFIG_FORMIKE) += formike.o
obj-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o videomodes.o
obj-$(CONFIG_IHS_VIDEO_OUT) += ihs_video_out.o
obj-$(CONFIG_LD9040) += ld9040.o
obj-$(CONFIG_LG4573) += lg4573.o
@ -47,11 +44,9 @@ obj-$(CONFIG_VIDEO_ARM_MALIDP) += mali_dp.o
obj-$(CONFIG_VIDEO_BCM2835) += bcm2835.o
obj-$(CONFIG_VIDEO_BROADWELL_IGD) += broadwell_igd.o
obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
obj-$(CONFIG_VIDEO_DW_MIPI_DSI) += dw_mipi_dsi.o
obj-$(CONFIG_VIDEO_EFI) += efi.o
obj-$(CONFIG_VIDEO_FSL_DCU_FB) += fsl_dcu_fb.o videomodes.o
obj-$(CONFIG_VIDEO_IPUV3) += imx/
obj-$(CONFIG_VIDEO_IVYBRIDGE_IGD) += ivybridge_igd.o
obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o

1865
drivers/video/cfb_console.c
View file

File diff suppressed because it is too large Load diff

1048
drivers/video/da8xx-fb.c
View file

File diff suppressed because it is too large Load diff

115
drivers/video/da8xx-fb.h
View file

@ -1,115 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Porting to u-boot:
*
* (C) Copyright 2011
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*
* Copyright (C) 2008-2009 MontaVista Software Inc.
* Copyright (C) 2008-2009 Texas Instruments Inc
*
* Based on the LCD driver for TI Avalanche processors written by
* Ajay Singh and Shalom Hai.
*/
#ifndef DA8XX_FB_H
#define DA8XX_FB_H
enum panel_type {
QVGA = 0,
WVGA
};
enum panel_shade {
MONOCHROME = 0,
COLOR_ACTIVE,
COLOR_PASSIVE,
};
enum raster_load_mode {
LOAD_DATA = 1,
LOAD_PALETTE,
};
struct display_panel {
enum panel_type panel_type; /* QVGA */
int max_bpp;
int min_bpp;
enum panel_shade panel_shade;
};
struct da8xx_panel {
const char name[25]; /* Full name <vendor>_<model> */
unsigned short width;
unsigned short height;
int hfp; /* Horizontal front porch */
int hbp; /* Horizontal back porch */
int hsw; /* Horizontal Sync Pulse Width */
int vfp; /* Vertical front porch */
int vbp; /* Vertical back porch */
int vsw; /* Vertical Sync Pulse Width */
unsigned int pxl_clk; /* Pixel clock */
unsigned char invert_pxl_clk; /* Invert Pixel clock */
};
struct da8xx_lcdc_platform_data {
const char manu_name[10];
void *controller_data;
const char type[25];
void (*panel_power_ctrl)(int);
};
struct lcd_ctrl_config {
const struct display_panel *p_disp_panel;
/* AC Bias Pin Frequency */
int ac_bias;
/* AC Bias Pin Transitions per Interrupt */
int ac_bias_intrpt;
/* DMA burst size */
int dma_burst_sz;
/* Bits per pixel */
int bpp;
/* FIFO DMA Request Delay */
int fdd;
/* TFT Alternative Signal Mapping (Only for active) */
unsigned char tft_alt_mode;
/* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
unsigned char stn_565_mode;
/* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
unsigned char mono_8bit_mode;
/* Invert line clock */
unsigned char invert_line_clock;
/* Invert frame clock */
unsigned char invert_frm_clock;
/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
unsigned char sync_edge;
/* Horizontal and Vertical Sync: Control: 0=ignore */
unsigned char sync_ctrl;
/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
unsigned char raster_order;
};
struct lcd_sync_arg {
int back_porch;
int front_porch;
int pulse_width;
};
void da8xx_video_init(const struct da8xx_panel *panel,
const struct lcd_ctrl_config *lcd_cfg,
int bits_pixel);
#endif /* ifndef DA8XX_FB_H */

513
drivers/video/formike.c
View file

@ -1,513 +0,0 @@
// SPDX-License-Identifier: GPL-2.0
/*
* LCD: Formike, TFT 4.3", 480x800, RGB24, KWH043ST20-F01, DriverIC NT35510-16
* LCD initialization via SPI
* Based on:
*
*/
#include <common.h>
#include <errno.h>
#include <log.h>
#include <spi.h>
#include <linux/delay.h>
#define TAG_READ 0x80
#define TAG_WRITE 0x00
#define TAG_DATA 0x40
#define TAG_COMMAND 0x00
#define TAG_ADDR_H 0x20
#define TAG_ADDR_L 0x00
static int spi_write_tag_val(struct spi_slave *spi, unsigned char tag,
unsigned char val)
{
unsigned long flags = SPI_XFER_BEGIN;
u8 buf[2];
int ret;
buf[0] = tag;
ret = spi_xfer(spi, 8, buf, NULL, flags);
buf[0] = val;
flags = SPI_XFER_END;
ret = spi_xfer(spi, 8, buf, NULL, flags);
#ifdef KWH043ST20_F01_SPI_DEBUG
printf("spi_write_tag_val: tag=%02X, val=%02X ret: %d\n",
tag, val, ret);
#endif /* KWH043ST20_F01_SPI_DEBUG */
if (ret)
debug("%s: Failed to send: %d\n", __func__, ret);
return ret;
}
static void spi_write_dat(struct spi_slave *spi, unsigned int val)
{
spi_write_tag_val(spi, TAG_WRITE|TAG_DATA, val);
}
static void spi_write_com(struct spi_slave *spi, unsigned int addr)
{
spi_write_tag_val(spi, TAG_WRITE|TAG_COMMAND|TAG_ADDR_H,
(addr & 0xff00) >> 8);
spi_write_tag_val(spi, TAG_WRITE|TAG_COMMAND|TAG_ADDR_L,
(addr & 0x00ff) >> 0);
}
int kwh043st20_f01_spi_startup(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode)
{
struct spi_slave *spi;
int ret;
spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
if (!spi) {
debug("%s: Failed to set up slave\n", __func__);
return -1;
}
ret = spi_claim_bus(spi);
if (ret) {
debug("%s: Failed to claim SPI bus: %d\n", __func__, ret);
goto err_claim_bus;
}
/* LV2 Page 1 enable */
spi_write_com(spi, 0xF000); spi_write_dat(spi, 0x55);
spi_write_com(spi, 0xF001); spi_write_dat(spi, 0xAA);
spi_write_com(spi, 0xF002); spi_write_dat(spi, 0x52);
spi_write_com(spi, 0xF003); spi_write_dat(spi, 0x08);
spi_write_com(spi, 0xF004); spi_write_dat(spi, 0x01);
/* AVDD Set AVDD 5.2V */
spi_write_com(spi, 0xB000); spi_write_dat(spi, 0x0D);
spi_write_com(spi, 0xB001); spi_write_dat(spi, 0x0D);
spi_write_com(spi, 0xB002); spi_write_dat(spi, 0x0D);
/* AVDD ratio */
spi_write_com(spi, 0xB600); spi_write_dat(spi, 0x34);
spi_write_com(spi, 0xB601); spi_write_dat(spi, 0x34);
spi_write_com(spi, 0xB602); spi_write_dat(spi, 0x34);
/* AVEE -5.2V */
spi_write_com(spi, 0xB100); spi_write_dat(spi, 0x0D);
spi_write_com(spi, 0xB101); spi_write_dat(spi, 0x0D);
spi_write_com(spi, 0xB102); spi_write_dat(spi, 0x0D);
/* AVEE ratio */
spi_write_com(spi, 0xB700); spi_write_dat(spi, 0x35);
spi_write_com(spi, 0xB701); spi_write_dat(spi, 0x35);
spi_write_com(spi, 0xB702); spi_write_dat(spi, 0x35);
/* VCL -2.5V */
spi_write_com(spi, 0xB200); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xB201); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xB202); spi_write_dat(spi, 0x00);
/* VCL ratio */
spi_write_com(spi, 0xB800); spi_write_dat(spi, 0x24);
spi_write_com(spi, 0xB801); spi_write_dat(spi, 0x24);
spi_write_com(spi, 0xB802); spi_write_dat(spi, 0x24);
/* VGH 15V */
spi_write_com(spi, 0xBF00); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xB300); spi_write_dat(spi, 0x08);
spi_write_com(spi, 0xB301); spi_write_dat(spi, 0x08);
spi_write_com(spi, 0xB302); spi_write_dat(spi, 0x08);
/* VGH ratio */
spi_write_com(spi, 0xB900); spi_write_dat(spi, 0x34);
spi_write_com(spi, 0xB901); spi_write_dat(spi, 0x34);
spi_write_com(spi, 0xB902); spi_write_dat(spi, 0x34);
/* VGLX ratio */
spi_write_com(spi, 0xBA00); spi_write_dat(spi, 0x24);
spi_write_com(spi, 0xBA01); spi_write_dat(spi, 0x24);
spi_write_com(spi, 0xBA02); spi_write_dat(spi, 0x24);
/* VGMP/VGSP 4.7V/0V */
spi_write_com(spi, 0xBC00); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xBC01); spi_write_dat(spi, 0x88);
spi_write_com(spi, 0xBC02); spi_write_dat(spi, 0x00);
/* VGMN/VGSN -4.7V/0V */
spi_write_com(spi, 0xBD00); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xBD01); spi_write_dat(spi, 0x88);
spi_write_com(spi, 0xBD02); spi_write_dat(spi, 0x00);
/* VCOM 1.525V */
spi_write_com(spi, 0xBE00); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xBE01); spi_write_dat(spi, 0x7A);
/* Gamma Setting */
spi_write_com(spi, 0xD100); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD101); spi_write_dat(spi, 0x05);
spi_write_com(spi, 0xD102); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD103); spi_write_dat(spi, 0x15);
spi_write_com(spi, 0xD104); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD105); spi_write_dat(spi, 0x30);
spi_write_com(spi, 0xD106); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD107); spi_write_dat(spi, 0x47);
spi_write_com(spi, 0xD108); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD109); spi_write_dat(spi, 0x5B);
spi_write_com(spi, 0xD10A); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD10B); spi_write_dat(spi, 0x7D);
spi_write_com(spi, 0xD10C); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD10D); spi_write_dat(spi, 0x9D);
spi_write_com(spi, 0xD10E); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD10F); spi_write_dat(spi, 0xCC);
spi_write_com(spi, 0xD110); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD111); spi_write_dat(spi, 0xF3);
spi_write_com(spi, 0xD112); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD113); spi_write_dat(spi, 0x32);
spi_write_com(spi, 0xD114); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD115); spi_write_dat(spi, 0x63);
spi_write_com(spi, 0xD116); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD117); spi_write_dat(spi, 0xB1);
spi_write_com(spi, 0xD118); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD119); spi_write_dat(spi, 0xF0);
spi_write_com(spi, 0xD11A); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD11B); spi_write_dat(spi, 0xF2);
spi_write_com(spi, 0xD11C); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD11D); spi_write_dat(spi, 0x2A);
spi_write_com(spi, 0xD11E); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD11F); spi_write_dat(spi, 0x67);
spi_write_com(spi, 0xD120); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD121); spi_write_dat(spi, 0x90);
spi_write_com(spi, 0xD122); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD123); spi_write_dat(spi, 0xCB);
spi_write_com(spi, 0xD124); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD125); spi_write_dat(spi, 0xF2);
spi_write_com(spi, 0xD126); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD127); spi_write_dat(spi, 0x2A);
spi_write_com(spi, 0xD128); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD129); spi_write_dat(spi, 0x51);
spi_write_com(spi, 0xD12A); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD12B); spi_write_dat(spi, 0x80);
spi_write_com(spi, 0xD12C); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD12D); spi_write_dat(spi, 0x9F);
spi_write_com(spi, 0xD12E); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD12F); spi_write_dat(spi, 0xBE);
spi_write_com(spi, 0xD130); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD131); spi_write_dat(spi, 0xF9);
spi_write_com(spi, 0xD132); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD133); spi_write_dat(spi, 0xFF);
spi_write_com(spi, 0xD200); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD201); spi_write_dat(spi, 0x05);
spi_write_com(spi, 0xD202); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD203); spi_write_dat(spi, 0x15);
spi_write_com(spi, 0xD204); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD205); spi_write_dat(spi, 0x30);
spi_write_com(spi, 0xD206); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD207); spi_write_dat(spi, 0x47);
spi_write_com(spi, 0xD208); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD209); spi_write_dat(spi, 0x5B);
spi_write_com(spi, 0xD20A); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD20B); spi_write_dat(spi, 0x7D);
spi_write_com(spi, 0xD20C); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD20D); spi_write_dat(spi, 0x9D);
spi_write_com(spi, 0xD20E); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD20F); spi_write_dat(spi, 0xCC);
spi_write_com(spi, 0xD210); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD211); spi_write_dat(spi, 0xF3);
spi_write_com(spi, 0xD212); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD213); spi_write_dat(spi, 0x32);
spi_write_com(spi, 0xD214); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD215); spi_write_dat(spi, 0x63);
spi_write_com(spi, 0xD216); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD217); spi_write_dat(spi, 0xB1);
spi_write_com(spi, 0xD218); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD219); spi_write_dat(spi, 0xF0);
spi_write_com(spi, 0xD21A); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD21B); spi_write_dat(spi, 0xF2);
spi_write_com(spi, 0xD21C); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD21D); spi_write_dat(spi, 0x2A);
spi_write_com(spi, 0xD21E); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD21F); spi_write_dat(spi, 0x67);
spi_write_com(spi, 0xD220); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD221); spi_write_dat(spi, 0x90);
spi_write_com(spi, 0xD222); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD223); spi_write_dat(spi, 0xCB);
spi_write_com(spi, 0xD224); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD225); spi_write_dat(spi, 0xF2);
spi_write_com(spi, 0xD226); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD227); spi_write_dat(spi, 0x2A);
spi_write_com(spi, 0xD228); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD229); spi_write_dat(spi, 0x51);
spi_write_com(spi, 0xD22A); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD22B); spi_write_dat(spi, 0x80);
spi_write_com(spi, 0xD22C); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD22D); spi_write_dat(spi, 0x9F);
spi_write_com(spi, 0xD22E); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD22F); spi_write_dat(spi, 0xBE);
spi_write_com(spi, 0xD230); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD231); spi_write_dat(spi, 0xF9);
spi_write_com(spi, 0xD232); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD233); spi_write_dat(spi, 0xFF);
spi_write_com(spi, 0xD300); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD301); spi_write_dat(spi, 0x05);
spi_write_com(spi, 0xD302); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD303); spi_write_dat(spi, 0x15);
spi_write_com(spi, 0xD304); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD305); spi_write_dat(spi, 0x30);
spi_write_com(spi, 0xD306); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD307); spi_write_dat(spi, 0x47);
spi_write_com(spi, 0xD308); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD309); spi_write_dat(spi, 0x5B);
spi_write_com(spi, 0xD30A); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD30B); spi_write_dat(spi, 0x7D);
spi_write_com(spi, 0xD30C); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD30D); spi_write_dat(spi, 0x9D);
spi_write_com(spi, 0xD30E); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD30F); spi_write_dat(spi, 0xCC);
spi_write_com(spi, 0xD310); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD311); spi_write_dat(spi, 0xF3);
spi_write_com(spi, 0xD312); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD313); spi_write_dat(spi, 0x32);
spi_write_com(spi, 0xD314); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD315); spi_write_dat(spi, 0x63);
spi_write_com(spi, 0xD316); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD317); spi_write_dat(spi, 0xB1);
spi_write_com(spi, 0xD318); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD319); spi_write_dat(spi, 0xF0);
spi_write_com(spi, 0xD31A); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD31B); spi_write_dat(spi, 0xF2);
spi_write_com(spi, 0xD31C); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD31D); spi_write_dat(spi, 0x2A);
spi_write_com(spi, 0xD31E); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD31F); spi_write_dat(spi, 0x67);
spi_write_com(spi, 0xD320); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD321); spi_write_dat(spi, 0x90);
spi_write_com(spi, 0xD322); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD323); spi_write_dat(spi, 0xCB);
spi_write_com(spi, 0xD324); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD325); spi_write_dat(spi, 0xF2);
spi_write_com(spi, 0xD326); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD327); spi_write_dat(spi, 0x2A);
spi_write_com(spi, 0xD328); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD329); spi_write_dat(spi, 0x51);
spi_write_com(spi, 0xD32A); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD32B); spi_write_dat(spi, 0x80);
spi_write_com(spi, 0xD32C); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD32D); spi_write_dat(spi, 0x9F);
spi_write_com(spi, 0xD32E); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD32F); spi_write_dat(spi, 0xBE);
spi_write_com(spi, 0xD330); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD331); spi_write_dat(spi, 0xF9);
spi_write_com(spi, 0xD332); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD333); spi_write_dat(spi, 0xFF);
spi_write_com(spi, 0xD400); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD401); spi_write_dat(spi, 0x05);
spi_write_com(spi, 0xD402); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD403); spi_write_dat(spi, 0x15);
spi_write_com(spi, 0xD404); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD405); spi_write_dat(spi, 0x30);
spi_write_com(spi, 0xD406); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD407); spi_write_dat(spi, 0x47);
spi_write_com(spi, 0xD408); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD409); spi_write_dat(spi, 0x5B);
spi_write_com(spi, 0xD40A); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD40B); spi_write_dat(spi, 0x7D);
spi_write_com(spi, 0xD40C); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD40D); spi_write_dat(spi, 0x9D);
spi_write_com(spi, 0xD40E); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD40F); spi_write_dat(spi, 0xCC);
spi_write_com(spi, 0xD410); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD411); spi_write_dat(spi, 0xF3);
spi_write_com(spi, 0xD412); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD413); spi_write_dat(spi, 0x32);
spi_write_com(spi, 0xD414); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD415); spi_write_dat(spi, 0x63);
spi_write_com(spi, 0xD416); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD417); spi_write_dat(spi, 0xB1);
spi_write_com(spi, 0xD418); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD419); spi_write_dat(spi, 0xF0);
spi_write_com(spi, 0xD41A); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD41B); spi_write_dat(spi, 0xF2);
spi_write_com(spi, 0xD41C); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD41D); spi_write_dat(spi, 0x2A);
spi_write_com(spi, 0xD41E); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD41F); spi_write_dat(spi, 0x67);
spi_write_com(spi, 0xD420); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD421); spi_write_dat(spi, 0x90);
spi_write_com(spi, 0xD422); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD423); spi_write_dat(spi, 0xCB);
spi_write_com(spi, 0xD424); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD425); spi_write_dat(spi, 0xF2);
spi_write_com(spi, 0xD426); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD427); spi_write_dat(spi, 0x2A);
spi_write_com(spi, 0xD428); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD429); spi_write_dat(spi, 0x51);
spi_write_com(spi, 0xD42A); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD42B); spi_write_dat(spi, 0x80);
spi_write_com(spi, 0xD42C); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD42D); spi_write_dat(spi, 0x9F);
spi_write_com(spi, 0xD42E); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD42F); spi_write_dat(spi, 0xBE);
spi_write_com(spi, 0xD430); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD431); spi_write_dat(spi, 0xF9);
spi_write_com(spi, 0xD432); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD433); spi_write_dat(spi, 0xFF);
spi_write_com(spi, 0xD500); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD501); spi_write_dat(spi, 0x05);
spi_write_com(spi, 0xD502); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD503); spi_write_dat(spi, 0x15);
spi_write_com(spi, 0xD504); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD505); spi_write_dat(spi, 0x30);
spi_write_com(spi, 0xD506); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD507); spi_write_dat(spi, 0x47);
spi_write_com(spi, 0xD508); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD509); spi_write_dat(spi, 0x5B);
spi_write_com(spi, 0xD50A); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD50B); spi_write_dat(spi, 0x7D);
spi_write_com(spi, 0xD50C); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD50D); spi_write_dat(spi, 0x9D);
spi_write_com(spi, 0xD50E); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD50F); spi_write_dat(spi, 0xCC);
spi_write_com(spi, 0xD510); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD511); spi_write_dat(spi, 0xF3);
spi_write_com(spi, 0xD512); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD513); spi_write_dat(spi, 0x32);
spi_write_com(spi, 0xD514); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD515); spi_write_dat(spi, 0x63);
spi_write_com(spi, 0xD516); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD517); spi_write_dat(spi, 0xB1);
spi_write_com(spi, 0xD518); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD519); spi_write_dat(spi, 0xF0);
spi_write_com(spi, 0xD51A); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD51B); spi_write_dat(spi, 0xF2);
spi_write_com(spi, 0xD51C); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD51D); spi_write_dat(spi, 0x2A);
spi_write_com(spi, 0xD51E); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD51F); spi_write_dat(spi, 0x67);
spi_write_com(spi, 0xD520); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD521); spi_write_dat(spi, 0x90);
spi_write_com(spi, 0xD522); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD523); spi_write_dat(spi, 0xCB);
spi_write_com(spi, 0xD524); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD525); spi_write_dat(spi, 0xF2);
spi_write_com(spi, 0xD526); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD527); spi_write_dat(spi, 0x2A);
spi_write_com(spi, 0xD528); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD529); spi_write_dat(spi, 0x51);
spi_write_com(spi, 0xD52A); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD52B); spi_write_dat(spi, 0x80);
spi_write_com(spi, 0xD52C); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD52D); spi_write_dat(spi, 0x9F);
spi_write_com(spi, 0xD52E); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD52F); spi_write_dat(spi, 0xBE);
spi_write_com(spi, 0xD530); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD531); spi_write_dat(spi, 0xF9);
spi_write_com(spi, 0xD532); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD533); spi_write_dat(spi, 0xFF);
spi_write_com(spi, 0xD600); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD601); spi_write_dat(spi, 0x05);
spi_write_com(spi, 0xD602); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD603); spi_write_dat(spi, 0x15);
spi_write_com(spi, 0xD604); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD605); spi_write_dat(spi, 0x30);
spi_write_com(spi, 0xD606); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD607); spi_write_dat(spi, 0x47);
spi_write_com(spi, 0xD608); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD609); spi_write_dat(spi, 0x5B);
spi_write_com(spi, 0xD60A); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD60B); spi_write_dat(spi, 0x7D);
spi_write_com(spi, 0xD60C); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD60D); spi_write_dat(spi, 0x9D);
spi_write_com(spi, 0xD60E); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD60F); spi_write_dat(spi, 0xCC);
spi_write_com(spi, 0xD610); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xD611); spi_write_dat(spi, 0xF3);
spi_write_com(spi, 0xD612); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD613); spi_write_dat(spi, 0x32);
spi_write_com(spi, 0xD614); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD615); spi_write_dat(spi, 0x63);
spi_write_com(spi, 0xD616); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD617); spi_write_dat(spi, 0xB1);
spi_write_com(spi, 0xD618); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD619); spi_write_dat(spi, 0xF0);
spi_write_com(spi, 0xD61A); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xD61B); spi_write_dat(spi, 0xF2);
spi_write_com(spi, 0xD61C); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD61D); spi_write_dat(spi, 0x2A);
spi_write_com(spi, 0xD61E); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD61F); spi_write_dat(spi, 0x67);
spi_write_com(spi, 0xD620); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD621); spi_write_dat(spi, 0x90);
spi_write_com(spi, 0xD622); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD623); spi_write_dat(spi, 0xCB);
spi_write_com(spi, 0xD624); spi_write_dat(spi, 0x02);
spi_write_com(spi, 0xD625); spi_write_dat(spi, 0xF2);
spi_write_com(spi, 0xD626); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD627); spi_write_dat(spi, 0x2A);
spi_write_com(spi, 0xD628); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD629); spi_write_dat(spi, 0x51);
spi_write_com(spi, 0xD62A); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD62B); spi_write_dat(spi, 0x80);
spi_write_com(spi, 0xD62C); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD62D); spi_write_dat(spi, 0x9F);
spi_write_com(spi, 0xD62E); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD62F); spi_write_dat(spi, 0xBE);
spi_write_com(spi, 0xD630); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD631); spi_write_dat(spi, 0xF9);
spi_write_com(spi, 0xD632); spi_write_dat(spi, 0x03);
spi_write_com(spi, 0xD633); spi_write_dat(spi, 0xFF);
/* LV2 Page 0 enable */
spi_write_com(spi, 0xF000); spi_write_dat(spi, 0x55);
spi_write_com(spi, 0xF001); spi_write_dat(spi, 0xAA);
spi_write_com(spi, 0xF002); spi_write_dat(spi, 0x52);
spi_write_com(spi, 0xF003); spi_write_dat(spi, 0x08);
spi_write_com(spi, 0xF004); spi_write_dat(spi, 0x00);
/* Display control */
spi_write_com(spi, 0xB100); spi_write_dat(spi, 0xFC);
spi_write_com(spi, 0xB101); spi_write_dat(spi, 0x00);
/* Source hold time */
spi_write_com(spi, 0xB600); spi_write_dat(spi, 0x05);
/* Gate EQ control */
spi_write_com(spi, 0xB700); spi_write_dat(spi, 0x70);
spi_write_com(spi, 0xB701); spi_write_dat(spi, 0x70);
/* Source EQ control (Mode 2) */
spi_write_com(spi, 0xB800); spi_write_dat(spi, 0x01);
spi_write_com(spi, 0xB801); spi_write_dat(spi, 0x05);
spi_write_com(spi, 0xB802); spi_write_dat(spi, 0x05);
spi_write_com(spi, 0xB803); spi_write_dat(spi, 0x05);
/* Inversion mode (Column) */
spi_write_com(spi, 0xBC00); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xBC01); spi_write_dat(spi, 0x00);
spi_write_com(spi, 0xBC02); spi_write_dat(spi, 0x00);
/* Timing control 8phase dual side/4H/4delay/RST_EN */
spi_write_com(spi, 0xC900); spi_write_dat(spi, 0xD0);
spi_write_com(spi, 0xC901); spi_write_dat(spi, 0x82);
spi_write_com(spi, 0xC902); spi_write_dat(spi, 0x50);
spi_write_com(spi, 0xC903); spi_write_dat(spi, 0x50);
spi_write_com(spi, 0xC904); spi_write_dat(spi, 0x50);
spi_write_com(spi, 0x3A00); spi_write_dat(spi, 0x55);
mdelay(120);
spi_write_com(spi, 0x1100);
mdelay(120);
spi_write_com(spi, 0x2900);
mdelay(120);
/* spi_write_com(spi, 0x2100); spi_write_dat(spi, 0x00); */
spi_write_com(spi, 0x2C00);
return 0;
err_claim_bus:
spi_free_slave(spi);
return -1;
}

549
drivers/video/fsl_dcu_fb.c
View file

@ -1,549 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2019 Toradex AG
*
* FSL DCU Framebuffer driver
*/
#include <init.h>
#include <asm/cache.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <common.h>
#include <dm.h>
#include <fdt_support.h>
#include <fsl_dcu_fb.h>
#include <linux/fb.h>
#include <malloc.h>
#include <video.h>
#include <video_fb.h>
#include "videomodes.h"
/* Convert the X,Y resolution pair into a single number */
#define RESOLUTION(x, y) (((u32)(x) << 16) | (y))
#ifdef CONFIG_SYS_FSL_DCU_LE
#define dcu_read32 in_le32
#define dcu_write32 out_le32
#elif defined(CONFIG_SYS_FSL_DCU_BE)
#define dcu_read32 in_be32
#define dcu_write32 out_be32
#endif
#define DCU_MODE_BLEND_ITER(x) ((x) << 20)
#define DCU_MODE_RASTER_EN (1 << 14)
#define DCU_MODE_NORMAL 1
#define DCU_MODE_COLORBAR 3
#define DCU_BGND_R(x) ((x) << 16)
#define DCU_BGND_G(x) ((x) << 8)
#define DCU_BGND_B(x) (x)
#define DCU_DISP_SIZE_DELTA_Y(x) ((x) << 16)
#define DCU_DISP_SIZE_DELTA_X(x) (x)
#define DCU_HSYN_PARA_BP(x) ((x) << 22)
#define DCU_HSYN_PARA_PW(x) ((x) << 11)
#define DCU_HSYN_PARA_FP(x) (x)
#define DCU_VSYN_PARA_BP(x) ((x) << 22)
#define DCU_VSYN_PARA_PW(x) ((x) << 11)
#define DCU_VSYN_PARA_FP(x) (x)
#define DCU_SYN_POL_INV_PXCK_FALL (1 << 6)
#define DCU_SYN_POL_NEG_REMAIN (0 << 5)
#define DCU_SYN_POL_INV_VS_LOW (1 << 1)
#define DCU_SYN_POL_INV_HS_LOW (1)
#define DCU_THRESHOLD_LS_BF_VS(x) ((x) << 16)
#define DCU_THRESHOLD_OUT_BUF_HIGH(x) ((x) << 8)
#define DCU_THRESHOLD_OUT_BUF_LOW(x) (x)
#define DCU_UPDATE_MODE_MODE (1 << 31)
#define DCU_UPDATE_MODE_READREG (1 << 30)
#define DCU_CTRLDESCLN_1_HEIGHT(x) ((x) << 16)
#define DCU_CTRLDESCLN_1_WIDTH(x) (x)
#define DCU_CTRLDESCLN_2_POSY(x) ((x) << 16)
#define DCU_CTRLDESCLN_2_POSX(x) (x)
#define DCU_CTRLDESCLN_4_EN (1 << 31)
#define DCU_CTRLDESCLN_4_TILE_EN (1 << 30)
#define DCU_CTRLDESCLN_4_DATA_SEL_CLUT (1 << 29)
#define DCU_CTRLDESCLN_4_SAFETY_EN (1 << 28)
#define DCU_CTRLDESCLN_4_TRANS(x) ((x) << 20)
#define DCU_CTRLDESCLN_4_BPP(x) ((x) << 16)
#define DCU_CTRLDESCLN_4_RLE_EN (1 << 15)
#define DCU_CTRLDESCLN_4_LUOFFS(x) ((x) << 4)
#define DCU_CTRLDESCLN_4_BB_ON (1 << 2)
#define DCU_CTRLDESCLN_4_AB(x) (x)
#define DCU_CTRLDESCLN_5_CKMAX_R(x) ((x) << 16)
#define DCU_CTRLDESCLN_5_CKMAX_G(x) ((x) << 8)
#define DCU_CTRLDESCLN_5_CKMAX_B(x) (x)
#define DCU_CTRLDESCLN_6_CKMIN_R(x) ((x) << 16)
#define DCU_CTRLDESCLN_6_CKMIN_G(x) ((x) << 8)
#define DCU_CTRLDESCLN_6_CKMIN_B(x) (x)
#define DCU_CTRLDESCLN_7_TILE_VER(x) ((x) << 16)
#define DCU_CTRLDESCLN_7_TILE_HOR(x) (x)
#define DCU_CTRLDESCLN_8_FG_FCOLOR(x) (x)
#define DCU_CTRLDESCLN_9_BG_BCOLOR(x) (x)
#define BPP_16_RGB565 4
#define BPP_24_RGB888 5
#define BPP_32_ARGB8888 6
DECLARE_GLOBAL_DATA_PTR;
/*
* This setting is used for the TWR_LCD_RGB card
*/
static struct fb_videomode fsl_dcu_mode_480_272 = {
.name = "480x272-60",
.refresh = 60,
.xres = 480,
.yres = 272,
.pixclock = 91996,
.left_margin = 2,
.right_margin = 2,
.upper_margin = 1,
.lower_margin = 1,
.hsync_len = 41,
.vsync_len = 2,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
/*
* This setting is used for Siliconimage SiI9022A HDMI
*/
static struct fb_videomode fsl_dcu_cea_mode_640_480 = {
.name = "640x480-60",
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 39722,
.left_margin = 48,
.right_margin = 16,
.upper_margin = 33,
.lower_margin = 10,
.hsync_len = 96,
.vsync_len = 2,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
};
static struct fb_videomode fsl_dcu_mode_640_480 = {
.name = "640x480-60",
.refresh = 60,
.xres = 640,
.yres = 480,
.pixclock = 25175,
.left_margin = 40,
.right_margin = 24,
.upper_margin = 32,
.lower_margin = 11,
.hsync_len = 96,
.vsync_len = 2,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
};
static struct fb_videomode fsl_dcu_mode_800_480 = {
.name = "800x480-60",
.refresh = 60,
.xres = 800,
.yres = 480,
.pixclock = 33260,
.left_margin = 216,
.right_margin = 40,
.upper_margin = 35,
.lower_margin = 10,
.hsync_len = 128,
.vsync_len = 2,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
};
static struct fb_videomode fsl_dcu_mode_1024_600 = {
.name = "1024x600-60",
.refresh = 60,
.xres = 1024,
.yres = 600,
.pixclock = 48000,
.left_margin = 104,
.right_margin = 43,
.upper_margin = 24,
.lower_margin = 20,
.hsync_len = 5,
.vsync_len = 5,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED,
};
/*
* DCU register map
*/
struct dcu_reg {
u32 desc_cursor[4];
u32 mode;
u32 bgnd;
u32 disp_size;
u32 hsyn_para;
u32 vsyn_para;
u32 synpol;
u32 threshold;
u32 int_status;
u32 int_mask;
u32 colbar[8];
u32 div_ratio;
u32 sign_calc[2];
u32 crc_val;
u8 res_064[0x6c-0x64];
u32 parr_err_status1;
u8 res_070[0x7c-0x70];
u32 parr_err_status3;
u32 mparr_err_status1;
u8 res_084[0x90-0x84];
u32 mparr_err_status3;
u32 threshold_inp_buf[2];
u8 res_09c[0xa0-0x9c];
u32 luma_comp;
u32 chroma_red;
u32 chroma_green;
u32 chroma_blue;
u32 crc_pos;
u32 lyr_intpol_en;
u32 lyr_luma_comp;
u32 lyr_chrm_red;
u32 lyr_chrm_grn;
u32 lyr_chrm_blue;
u8 res_0c4[0xcc-0xc8];
u32 update_mode;
u32 underrun;
u8 res_0d4[0x100-0xd4];
u32 gpr;
u32 slr_l[2];
u32 slr_disp_size;
u32 slr_hvsync_para;
u32 slr_pol;
u32 slr_l_transp[2];
u8 res_120[0x200-0x120];
u32 ctrldescl[DCU_LAYER_MAX_NUM][16];
};
static void reset_total_layers(void)
{
struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
int i;
for (i = 0; i < DCU_LAYER_MAX_NUM; i++) {
dcu_write32(&regs->ctrldescl[i][0], 0);
dcu_write32(&regs->ctrldescl[i][1], 0);
dcu_write32(&regs->ctrldescl[i][2], 0);
dcu_write32(&regs->ctrldescl[i][3], 0);
dcu_write32(&regs->ctrldescl[i][4], 0);
dcu_write32(&regs->ctrldescl[i][5], 0);
dcu_write32(&regs->ctrldescl[i][6], 0);
dcu_write32(&regs->ctrldescl[i][7], 0);
dcu_write32(&regs->ctrldescl[i][8], 0);
dcu_write32(&regs->ctrldescl[i][9], 0);
dcu_write32(&regs->ctrldescl[i][10], 0);
}
}
static int layer_ctrldesc_init(struct fb_info fbinfo,
int index, u32 pixel_format)
{
struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
unsigned int bpp = BPP_24_RGB888;
dcu_write32(&regs->ctrldescl[index][0],
DCU_CTRLDESCLN_1_HEIGHT(fbinfo.var.yres) |
DCU_CTRLDESCLN_1_WIDTH(fbinfo.var.xres));
dcu_write32(&regs->ctrldescl[index][1],
DCU_CTRLDESCLN_2_POSY(0) |
DCU_CTRLDESCLN_2_POSX(0));
dcu_write32(&regs->ctrldescl[index][2],
(unsigned int)fbinfo.screen_base);
switch (pixel_format) {
case 16:
bpp = BPP_16_RGB565;
break;
case 24:
bpp = BPP_24_RGB888;
break;
case 32:
bpp = BPP_32_ARGB8888;
break;
default:
printf("unsupported color depth: %u\n", pixel_format);
}
dcu_write32(&regs->ctrldescl[index][3],
DCU_CTRLDESCLN_4_EN |
DCU_CTRLDESCLN_4_TRANS(0xff) |
DCU_CTRLDESCLN_4_BPP(bpp) |
DCU_CTRLDESCLN_4_AB(0));
dcu_write32(&regs->ctrldescl[index][4],
DCU_CTRLDESCLN_5_CKMAX_R(0xff) |
DCU_CTRLDESCLN_5_CKMAX_G(0xff) |
DCU_CTRLDESCLN_5_CKMAX_B(0xff));
dcu_write32(&regs->ctrldescl[index][5],
DCU_CTRLDESCLN_6_CKMIN_R(0) |
DCU_CTRLDESCLN_6_CKMIN_G(0) |
DCU_CTRLDESCLN_6_CKMIN_B(0));
dcu_write32(&regs->ctrldescl[index][6],
DCU_CTRLDESCLN_7_TILE_VER(0) |
DCU_CTRLDESCLN_7_TILE_HOR(0));
dcu_write32(&regs->ctrldescl[index][7], DCU_CTRLDESCLN_8_FG_FCOLOR(0));
dcu_write32(&regs->ctrldescl[index][8], DCU_CTRLDESCLN_9_BG_BCOLOR(0));
return 0;
}
int fsl_dcu_init(struct fb_info *fbinfo, unsigned int xres,
unsigned int yres, unsigned int pixel_format)
{
struct dcu_reg *regs = (struct dcu_reg *)CONFIG_SYS_DCU_ADDR;
unsigned int div, mode;
/*
* When DM_VIDEO is enabled reservation of framebuffer is done
* in advance during bind() call.
*/
#if !CONFIG_IS_ENABLED(DM_VIDEO)
fbinfo->screen_size = fbinfo->var.xres * fbinfo->var.yres *
(fbinfo->var.bits_per_pixel / 8);
if (fbinfo->screen_size > CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB) {
fbinfo->screen_size = 0;
return -ENOMEM;
}
/* Reserve framebuffer at the end of memory */
gd->fb_base = gd->bd->bi_dram[0].start +
gd->bd->bi_dram[0].size - fbinfo->screen_size;
fbinfo->screen_base = (char *)gd->fb_base;
memset(fbinfo->screen_base, 0, fbinfo->screen_size);
#endif
reset_total_layers();
dcu_write32(&regs->disp_size,
DCU_DISP_SIZE_DELTA_Y(fbinfo->var.yres) |
DCU_DISP_SIZE_DELTA_X(fbinfo->var.xres / 16));
dcu_write32(&regs->hsyn_para,
DCU_HSYN_PARA_BP(fbinfo->var.left_margin) |
DCU_HSYN_PARA_PW(fbinfo->var.hsync_len) |
DCU_HSYN_PARA_FP(fbinfo->var.right_margin));
dcu_write32(&regs->vsyn_para,
DCU_VSYN_PARA_BP(fbinfo->var.upper_margin) |
DCU_VSYN_PARA_PW(fbinfo->var.vsync_len) |
DCU_VSYN_PARA_FP(fbinfo->var.lower_margin));
dcu_write32(&regs->synpol,
DCU_SYN_POL_INV_PXCK_FALL |
DCU_SYN_POL_NEG_REMAIN |
DCU_SYN_POL_INV_VS_LOW |
DCU_SYN_POL_INV_HS_LOW);
dcu_write32(&regs->bgnd,
DCU_BGND_R(0) | DCU_BGND_G(0) | DCU_BGND_B(0));
dcu_write32(&regs->mode,
DCU_MODE_BLEND_ITER(2) |
DCU_MODE_RASTER_EN);
dcu_write32(&regs->threshold,
DCU_THRESHOLD_LS_BF_VS(0x3) |
DCU_THRESHOLD_OUT_BUF_HIGH(0x78) |
DCU_THRESHOLD_OUT_BUF_LOW(0));
mode = dcu_read32(&regs->mode);
dcu_write32(&regs->mode, mode | DCU_MODE_NORMAL);
layer_ctrldesc_init(*fbinfo, 0, pixel_format);
div = dcu_set_pixel_clock(fbinfo->var.pixclock);
dcu_write32(&regs->div_ratio, (div - 1));
dcu_write32(&regs->update_mode, DCU_UPDATE_MODE_READREG);
return 0;
}
ulong board_get_usable_ram_top(ulong total_size)
{
return gd->ram_top - CONFIG_VIDEO_FSL_DCU_MAX_FB_SIZE_MB;
}
int fsl_probe_common(struct fb_info *fbinfo, unsigned int *win_x,
unsigned int *win_y)
{
const char *options;
unsigned int depth = 0, freq = 0;
struct fb_videomode *fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
if (!video_get_video_mode(win_x, win_y, &depth, &freq,
&options))
return -EINVAL;
/* Find the monitor port, which is a required option */
if (!options)
return -EINVAL;
if (strncmp(options, "monitor=", 8) != 0)
return -EINVAL;
switch (RESOLUTION(*win_x, *win_y)) {
case RESOLUTION(480, 272):
fsl_dcu_mode_db = &fsl_dcu_mode_480_272;
break;
case RESOLUTION(640, 480):
if (!strncmp(options, "monitor=hdmi", 12))
fsl_dcu_mode_db = &fsl_dcu_cea_mode_640_480;
else
fsl_dcu_mode_db = &fsl_dcu_mode_640_480;
break;
case RESOLUTION(800, 480):
fsl_dcu_mode_db = &fsl_dcu_mode_800_480;
break;
case RESOLUTION(1024, 600):
fsl_dcu_mode_db = &fsl_dcu_mode_1024_600;
break;
default:
printf("unsupported resolution %ux%u\n",
*win_x, *win_y);
}
fbinfo->var.xres = fsl_dcu_mode_db->xres;
fbinfo->var.yres = fsl_dcu_mode_db->yres;
fbinfo->var.bits_per_pixel = 32;
fbinfo->var.pixclock = fsl_dcu_mode_db->pixclock;
fbinfo->var.left_margin = fsl_dcu_mode_db->left_margin;
fbinfo->var.right_margin = fsl_dcu_mode_db->right_margin;
fbinfo->var.upper_margin = fsl_dcu_mode_db->upper_margin;
fbinfo->var.lower_margin = fsl_dcu_mode_db->lower_margin;
fbinfo->var.hsync_len = fsl_dcu_mode_db->hsync_len;
fbinfo->var.vsync_len = fsl_dcu_mode_db->vsync_len;
fbinfo->var.sync = fsl_dcu_mode_db->sync;
fbinfo->var.vmode = fsl_dcu_mode_db->vmode;
fbinfo->fix.line_length = fbinfo->var.xres *
fbinfo->var.bits_per_pixel / 8;
return platform_dcu_init(fbinfo, *win_x, *win_y,
options + 8, fsl_dcu_mode_db);
}
#ifndef CONFIG_DM_VIDEO
static struct fb_info info;
#if defined(CONFIG_OF_BOARD_SETUP)
int fsl_dcu_fixedfb_setup(void *blob)
{
u64 start, size;
int ret;
start = gd->bd->bi_dram[0].start;
size = gd->bd->bi_dram[0].size - info.screen_size;
/*
* Align size on section size (1 MiB).
*/
size &= 0xfff00000;
ret = fdt_fixup_memory_banks(blob, &start, &size, 1);
if (ret) {
eprintf("Cannot setup fb: Error reserving memory\n");
return ret;
}
return 0;
}
#endif
void *video_hw_init(void)
{
static GraphicDevice ctfb;
if (fsl_probe_common(&info, &ctfb.winSizeX, &ctfb.winSizeY) < 0)
return NULL;
ctfb.frameAdrs = (unsigned int)info.screen_base;
ctfb.plnSizeX = ctfb.winSizeX;
ctfb.plnSizeY = ctfb.winSizeY;
ctfb.gdfBytesPP = 4;
ctfb.gdfIndex = GDF_32BIT_X888RGB;
ctfb.memSize = info.screen_size;
return &ctfb;
}
#else /* ifndef CONFIG_DM_VIDEO */
static int fsl_dcu_video_probe(struct udevice *dev)
{
struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct fb_info fbinfo = { 0 };
unsigned int win_x;
unsigned int win_y;
u32 fb_start, fb_end;
int ret = 0;
fb_start = plat->base & ~(MMU_SECTION_SIZE - 1);
fb_end = plat->base + plat->size;
fb_end = ALIGN(fb_end, 1 << MMU_SECTION_SHIFT);
fbinfo.screen_base = (char *)fb_start;
fbinfo.screen_size = plat->size;
ret = fsl_probe_common(&fbinfo, &win_x, &win_y);
if (ret < 0)
return ret;
uc_priv->bpix = VIDEO_BPP32;
uc_priv->xsize = win_x;
uc_priv->ysize = win_y;
/* Enable dcache for the frame buffer */
mmu_set_region_dcache_behaviour(fb_start, fb_end - fb_start,
DCACHE_WRITEBACK);
video_set_flush_dcache(dev, true);
return ret;
}
static int fsl_dcu_video_bind(struct udevice *dev)
{
struct video_uc_plat *plat = dev_get_uclass_plat(dev);
unsigned int win_x;
unsigned int win_y;
unsigned int depth = 0, freq = 0;
const char *options;
int ret = 0;
ret = video_get_video_mode(&win_x, &win_y, &depth, &freq, &options);
if (ret < 0)
return ret;
plat->size = win_x * win_y * 32;
return 0;
}
static const struct udevice_id fsl_dcu_video_ids[] = {
{ .compatible = "fsl,vf610-dcu" },
{ /* sentinel */ }
};
U_BOOT_DRIVER(fsl_dcu_video) = {
.name = "fsl_dcu_video",
.id = UCLASS_VIDEO,
.of_match = fsl_dcu_video_ids,
.bind = fsl_dcu_video_bind,
.probe = fsl_dcu_video_probe,
.flags = DM_FLAG_PRE_RELOC,
};
#endif /* ifndef CONFIG_DM_VIDEO */

416
drivers/video/fsl_diu_fb.c
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@ -1,416 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
* Authors: York Sun <yorksun@freescale.com>
* Timur Tabi <timur@freescale.com>
*
* FSL DIU Framebuffer driver
*/
#include <common.h>
#include <malloc.h>
#include <asm/io.h>
#include "videomodes.h"
#include <video_fb.h>
#include <fsl_diu_fb.h>
#include <linux/list.h>
#include <linux/fb.h>
/* This setting is used for the ifm pdm360ng with PRIMEVIEW PM070WL3 */
static struct fb_videomode fsl_diu_mode_800_480 = {
.name = "800x480-60",
.refresh = 60,
.xres = 800,
.yres = 480,
.pixclock = 31250,
.left_margin = 86,
.right_margin = 42,
.upper_margin = 33,
.lower_margin = 10,
.hsync_len = 128,
.vsync_len = 2,
.sync = 0,
.vmode = FB_VMODE_NONINTERLACED
};
/* For the SHARP LQ084S3LG01, used on the P1022DS board */
static struct fb_videomode fsl_diu_mode_800_600 = {
.name = "800x600-60",
.refresh = 60,
.xres = 800,
.yres = 600,
.pixclock = 25000,
.left_margin = 88,
.right_margin = 40,
.upper_margin = 23,
.lower_margin = 1,
.hsync_len = 128,
.vsync_len = 4,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
/*
* These parameters give default parameters
* for video output 1024x768,
* FIXME - change timing to proper amounts
* hsync 31.5kHz, vsync 60Hz
*/
static struct fb_videomode fsl_diu_mode_1024_768 = {
.name = "1024x768-60",
.refresh = 60,
.xres = 1024,
.yres = 768,
.pixclock = 15385,
.left_margin = 160,
.right_margin = 24,
.upper_margin = 29,
.lower_margin = 3,
.hsync_len = 136,
.vsync_len = 6,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
static struct fb_videomode fsl_diu_mode_1280_1024 = {
.name = "1280x1024-60",
.refresh = 60,
.xres = 1280,
.yres = 1024,
.pixclock = 9375,
.left_margin = 38,
.right_margin = 128,
.upper_margin = 2,
.lower_margin = 7,
.hsync_len = 216,
.vsync_len = 37,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
static struct fb_videomode fsl_diu_mode_1280_720 = {
.name = "1280x720-60",
.refresh = 60,
.xres = 1280,
.yres = 720,
.pixclock = 13426,
.left_margin = 192,
.right_margin = 64,
.upper_margin = 22,
.lower_margin = 1,
.hsync_len = 136,
.vsync_len = 3,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
static struct fb_videomode fsl_diu_mode_1920_1080 = {
.name = "1920x1080-60",
.refresh = 60,
.xres = 1920,
.yres = 1080,
.pixclock = 5787,
.left_margin = 328,
.right_margin = 120,
.upper_margin = 34,
.lower_margin = 1,
.hsync_len = 208,
.vsync_len = 3,
.sync = FB_SYNC_COMP_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
.vmode = FB_VMODE_NONINTERLACED
};
/*
* These are the fields of area descriptor(in DDR memory) for every plane
*/
struct diu_ad {
/* Word 0(32-bit) in DDR memory */
__le32 pix_fmt; /* hard coding pixel format */
/* Word 1(32-bit) in DDR memory */
__le32 addr;
/* Word 2(32-bit) in DDR memory */
__le32 src_size_g_alpha;
/* Word 3(32-bit) in DDR memory */
__le32 aoi_size;
/* Word 4(32-bit) in DDR memory */
__le32 offset_xyi;
/* Word 5(32-bit) in DDR memory */
__le32 offset_xyd;
/* Word 6(32-bit) in DDR memory */
__le32 ckmax_r:8;
__le32 ckmax_g:8;
__le32 ckmax_b:8;
__le32 res9:8;
/* Word 7(32-bit) in DDR memory */
__le32 ckmin_r:8;
__le32 ckmin_g:8;
__le32 ckmin_b:8;
__le32 res10:8;
/* Word 8(32-bit) in DDR memory */
__le32 next_ad;
/* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
__le32 res[3];
} __attribute__ ((packed));
/*
* DIU register map
*/
struct diu {
__be32 desc[3];
__be32 gamma;
__be32 pallete;
__be32 cursor;
__be32 curs_pos;
__be32 diu_mode;
__be32 bgnd;
__be32 bgnd_wb;
__be32 disp_size;
__be32 wb_size;
__be32 wb_mem_addr;
__be32 hsyn_para;
__be32 vsyn_para;
__be32 syn_pol;
__be32 thresholds;
__be32 int_status;
__be32 int_mask;
__be32 colorbar[8];
__be32 filling;
__be32 plut;
} __attribute__ ((packed));
struct diu_addr {
void *vaddr; /* Virtual address */
u32 paddr; /* 32-bit physical address */
unsigned int offset; /* Alignment offset */
};
static struct fb_info info;
/*
* Align to 64-bit(8-byte), 32-byte, etc.
*/
static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align)
{
u32 offset, ssize;
u32 mask;
ssize = size + bytes_align;
buf->vaddr = malloc(ssize);
if (!buf->vaddr)
return -1;
memset(buf->vaddr, 0, ssize);
mask = bytes_align - 1;
offset = (u32)buf->vaddr & mask;
if (offset) {
buf->offset = bytes_align - offset;
buf->vaddr += offset;
} else
buf->offset = 0;
buf->paddr = virt_to_phys(buf->vaddr);
return 0;
}
/*
* Allocate a framebuffer and an Area Descriptor that points to it. Both
* are created in the same memory block. The Area Descriptor is updated to
* point to the framebuffer memory. Memory is aligned as needed.
*/
static struct diu_ad *allocate_fb(unsigned int xres, unsigned int yres,
unsigned int depth, char **fb)
{
unsigned long size = xres * yres * depth;
struct diu_addr addr;
struct diu_ad *ad;
size_t ad_size = roundup(sizeof(struct diu_ad), 32);
/*
* Allocate a memory block that holds the Area Descriptor and the
* frame buffer right behind it. To keep the code simple, everything
* is aligned on a 32-byte address.
*/
if (allocate_buf(&addr, ad_size + size, 32) < 0)
return NULL;
ad = addr.vaddr;
ad->addr = cpu_to_le32(addr.paddr + ad_size);
ad->aoi_size = cpu_to_le32((yres << 16) | xres);
ad->src_size_g_alpha = cpu_to_le32((yres << 12) | xres);
ad->offset_xyi = 0;
ad->offset_xyd = 0;
if (fb)
*fb = addr.vaddr + ad_size;
return ad;
}
int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix)
{
struct fb_videomode *fsl_diu_mode_db;
struct diu_ad *ad;
struct diu *hw = (struct diu *)CONFIG_SYS_DIU_ADDR;
u8 *gamma_table_base;
unsigned int i, j;
struct diu_addr gamma;
struct diu_addr cursor;
/* Convert the X,Y resolution pair into a single number */
#define RESOLUTION(x, y) (((u32)(x) << 16) | (y))
switch (RESOLUTION(xres, yres)) {
case RESOLUTION(800, 480):
fsl_diu_mode_db = &fsl_diu_mode_800_480;
break;
case RESOLUTION(800, 600):
fsl_diu_mode_db = &fsl_diu_mode_800_600;
break;
case RESOLUTION(1024, 768):
fsl_diu_mode_db = &fsl_diu_mode_1024_768;
break;
case RESOLUTION(1280, 1024):
fsl_diu_mode_db = &fsl_diu_mode_1280_1024;
break;
case RESOLUTION(1280, 720):
fsl_diu_mode_db = &fsl_diu_mode_1280_720;
break;
case RESOLUTION(1920, 1080):
fsl_diu_mode_db = &fsl_diu_mode_1920_1080;
break;
default:
printf("DIU: Unsupported resolution %ux%u\n", xres, yres);
return -1;
}
/* read mode info */
info.var.xres = fsl_diu_mode_db->xres;
info.var.yres = fsl_diu_mode_db->yres;
info.var.bits_per_pixel = 32;
info.var.pixclock = fsl_diu_mode_db->pixclock;
info.var.left_margin = fsl_diu_mode_db->left_margin;
info.var.right_margin = fsl_diu_mode_db->right_margin;
info.var.upper_margin = fsl_diu_mode_db->upper_margin;
info.var.lower_margin = fsl_diu_mode_db->lower_margin;
info.var.hsync_len = fsl_diu_mode_db->hsync_len;
info.var.vsync_len = fsl_diu_mode_db->vsync_len;
info.var.sync = fsl_diu_mode_db->sync;
info.var.vmode = fsl_diu_mode_db->vmode;
info.fix.line_length = info.var.xres * info.var.bits_per_pixel / 8;
/* Memory allocation for framebuffer */
info.screen_size =
info.var.xres * info.var.yres * (info.var.bits_per_pixel / 8);
ad = allocate_fb(info.var.xres, info.var.yres,
info.var.bits_per_pixel / 8, &info.screen_base);
if (!ad) {
printf("DIU: Out of memory\n");
return -1;
}
ad->pix_fmt = pixel_format;
/* Disable chroma keying function */
ad->ckmax_r = 0;
ad->ckmax_g = 0;
ad->ckmax_b = 0;
ad->ckmin_r = 255;
ad->ckmin_g = 255;
ad->ckmin_b = 255;
/* Initialize the gamma table */
if (allocate_buf(&gamma, 256 * 3, 32) < 0) {
printf("DIU: Out of memory\n");
return -1;
}
gamma_table_base = gamma.vaddr;
for (i = 0; i <= 2; i++)
for (j = 0; j < 256; j++)
*gamma_table_base++ = j;
if (gamma_fix == 1) { /* fix the gamma */
gamma_table_base = gamma.vaddr;
for (i = 0; i < 256 * 3; i++) {
gamma_table_base[i] = (gamma_table_base[i] << 2)
| ((gamma_table_base[i] >> 6) & 0x03);
}
}
/* Initialize the cursor */
if (allocate_buf(&cursor, 32 * 32 * 2, 32) < 0) {
printf("DIU: Can't alloc cursor data\n");
return -1;
}
/* Program DIU registers */
out_be32(&hw->diu_mode, 0); /* Temporarily disable the DIU */
out_be32(&hw->gamma, gamma.paddr);
out_be32(&hw->cursor, cursor.paddr);
out_be32(&hw->bgnd, 0x007F7F7F);
out_be32(&hw->disp_size, info.var.yres << 16 | info.var.xres);
out_be32(&hw->hsyn_para, info.var.left_margin << 22 |
info.var.hsync_len << 11 |
info.var.right_margin);
out_be32(&hw->vsyn_para, info.var.upper_margin << 22 |
info.var.vsync_len << 11 |
info.var.lower_margin);
/* Pixel Clock configuration */
diu_set_pixel_clock(info.var.pixclock);
/* Set the frame buffers */
out_be32(&hw->desc[0], virt_to_phys(ad));
out_be32(&hw->desc[1], 0);
out_be32(&hw->desc[2], 0);
/* Enable the DIU, set display to all three planes */
out_be32(&hw->diu_mode, 1);
return 0;
}
void *video_hw_init(void)
{
static GraphicDevice ctfb;
const char *options;
unsigned int depth = 0, freq = 0;
if (!video_get_video_mode(&ctfb.winSizeX, &ctfb.winSizeY, &depth, &freq,
&options))
return NULL;
/* Find the monitor port, which is a required option */
if (!options)
return NULL;
if (strncmp(options, "monitor=", 8) != 0)
return NULL;
if (platform_diu_init(ctfb.winSizeX, ctfb.winSizeY, options + 8) < 0)
return NULL;
/* fill in Graphic device struct */
sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz",
ctfb.winSizeX, ctfb.winSizeY, depth, 64, freq);
ctfb.frameAdrs = (unsigned int)info.screen_base;
ctfb.plnSizeX = ctfb.winSizeX;
ctfb.plnSizeY = ctfb.winSizeY;
ctfb.gdfBytesPP = 4;
ctfb.gdfIndex = GDF_32BIT_X888RGB;
ctfb.isaBase = 0;
ctfb.pciBase = 0;
ctfb.memSize = info.screen_size;
/* Cursor Start Address */
ctfb.dprBase = 0;
ctfb.vprBase = 0;
ctfb.cprBase = 0;
return &ctfb;
}

1
drivers/video/imx/mxc_ipuv3_fb.c
View file

@ -22,7 +22,6 @@
#include <asm/io.h>
#include <asm/mach-imx/video.h>
#include <malloc.h>
#include <video_fb.h>
#include "../videomodes.h"
#include "ipu.h"
#include "mxcfb.h"

90
drivers/video/mxsfb.c
View file

@ -15,7 +15,6 @@
#include <linux/errno.h>
#include <malloc.h>
#include <video.h>
#include <video_fb.h>
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
@ -253,94 +252,6 @@ static int mxs_remove_common(u32 fb)
return 0;
}
#ifndef CONFIG_DM_VIDEO
static GraphicDevice panel;
void lcdif_power_down(void)
{
mxs_remove_common(panel.frameAdrs);
}
void *video_hw_init(void)
{
int bpp = -1;
int ret = 0;
char *penv;
void *fb = NULL;
struct ctfb_res_modes mode;
struct display_timing timings;
puts("Video: ");
/* Suck display configuration from "videomode" variable */
penv = env_get("videomode");
if (!penv) {
puts("MXSFB: 'videomode' variable not set!\n");
return NULL;
}
bpp = video_get_params(&mode, penv);
/* fill in Graphic device struct */
sprintf(panel.modeIdent, "%dx%dx%d", mode.xres, mode.yres, bpp);
panel.winSizeX = mode.xres;
panel.winSizeY = mode.yres;
panel.plnSizeX = mode.xres;
panel.plnSizeY = mode.yres;
switch (bpp) {
case 24:
case 18:
panel.gdfBytesPP = 4;
panel.gdfIndex = GDF_32BIT_X888RGB;
break;
case 16:
panel.gdfBytesPP = 2;
panel.gdfIndex = GDF_16BIT_565RGB;
break;
case 8:
panel.gdfBytesPP = 1;
panel.gdfIndex = GDF__8BIT_INDEX;
break;
default:
printf("MXSFB: Invalid BPP specified! (bpp = %i)\n", bpp);
return NULL;
}
panel.memSize = mode.xres * mode.yres * panel.gdfBytesPP;
/* Allocate framebuffer */
fb = memalign(ARCH_DMA_MINALIGN,
roundup(panel.memSize, ARCH_DMA_MINALIGN));
if (!fb) {
printf("MXSFB: Error allocating framebuffer!\n");
return NULL;
}
/* Wipe framebuffer */
memset(fb, 0, panel.memSize);
panel.frameAdrs = (u32)fb;
printf("%s\n", panel.modeIdent);
video_ctfb_mode_to_display_timing(&mode, &timings);
ret = mxs_probe_common(NULL, &timings, bpp, (u32)fb);
if (ret)
goto dealloc_fb;
return (void *)&panel;
dealloc_fb:
free(fb);
return NULL;
}
#else /* ifndef CONFIG_DM_VIDEO */
static int mxs_of_get_timings(struct udevice *dev,
struct display_timing *timings,
u32 *bpp)
@ -490,4 +401,3 @@ U_BOOT_DRIVER(mxs_video) = {
.remove = mxs_video_remove,
.flags = DM_FLAG_PRE_RELOC | DM_FLAG_OS_PREPARE,
};
#endif /* ifndef CONFIG_DM_VIDEO */

17
drivers/video/nexell_display.c
View file

@ -16,7 +16,6 @@
#include <linux/compat.h>
#include <linux/err.h>
#include <video.h> /* For struct video_uc_plat */
#include <video_fb.h>
#include <lcd.h>
#include <asm/global_data.h>
#include <asm/io.h>
@ -537,7 +536,6 @@ static int nx_display_probe(struct udevice *dev)
struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct nx_display_plat *plat = dev_get_plat(dev);
static GraphicDevice *graphic_device;
char addr[64];
debug("%s()\n", __func__);
@ -564,7 +562,6 @@ static int nx_display_probe(struct udevice *dev)
}
struct nx_display_dev *dp;
unsigned int pp_index = 0;
dp = nx_display_setup();
if (!dp) {
@ -575,7 +572,6 @@ static int nx_display_probe(struct udevice *dev)
switch (dp->depth) {
case 2:
pp_index = GDF_16BIT_565RGB;
uc_priv->bpix = VIDEO_BPP16;
break;
case 3:
@ -583,7 +579,6 @@ static int nx_display_probe(struct udevice *dev)
* type video_log2_bpp
*/
case 4:
pp_index = GDF_32BIT_X888RGB;
uc_priv->bpix = VIDEO_BPP32;
break;
default:
@ -596,19 +591,9 @@ static int nx_display_probe(struct udevice *dev)
uc_priv->ysize = dp->fb_plane->height;
uc_priv->rot = 0;
graphic_device = &dp->graphic_device;
graphic_device->frameAdrs = dp->fb_addr;
graphic_device->gdfIndex = pp_index;
graphic_device->gdfBytesPP = dp->depth;
graphic_device->winSizeX = dp->fb_plane->width;
graphic_device->winSizeY = dp->fb_plane->height;
graphic_device->plnSizeX =
graphic_device->winSizeX * graphic_device->gdfBytesPP;
/*
* set environment variable "fb_addr" (frame buffer address), required
* for splash image. Because drv_video_init() in common/stdio.c is only
* called when CONFIG_VIDEO is set (and not if CONFIG_DM_VIDEO is set).
* for splash image, which is not set if CONFIG_DM_VIDEO is enabled).
*/
sprintf(addr, "0x%x", dp->fb_addr);
debug("%s(): env_set(\"fb_addr\", %s) ...\n", __func__, addr);

29
drivers/video/omap3_dss.c
View file

@ -28,7 +28,6 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/dss.h>
#include <video_fb.h>
/* Configure VENC for a given Mode (NTSC / PAL) */
void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
@ -137,31 +136,3 @@ void omap3_dss_enable(void)
l |= LCD_ENABLE | GO_LCD | DIG_ENABLE | GO_DIG | GP_OUT0 | GP_OUT1;
writel(l, &dispc->control);
}
#ifdef CONFIG_CFB_CONSOLE
int __board_video_init(void)
{
return -1;
}
int board_video_init(void)
__attribute__((weak, alias("__board_video_init")));
void *video_hw_init(void)
{
static GraphicDevice dssfb;
GraphicDevice *pGD = &dssfb;
struct dispc_regs *dispc = (struct dispc_regs *) OMAP3_DISPC_BASE;
if (board_video_init() || !readl(&dispc->gfx_ba0))
return NULL;
pGD->winSizeX = (readl(&dispc->size_lcd) & 0x7FF) + 1;
pGD->winSizeY = ((readl(&dispc->size_lcd) >> 16) & 0x7FF) + 1;
pGD->gdfBytesPP = 4;
pGD->gdfIndex = GDF_32BIT_X888RGB;
pGD->frameAdrs = readl(&dispc->gfx_ba0);
return pGD;
}
#endif

1
drivers/video/sunxi/sunxi_display.c
View file

@ -30,7 +30,6 @@
#include <i2c.h>
#include <malloc.h>
#include <video.h>
#include <video_fb.h>
#include <dm/uclass-internal.h>
#include "../videomodes.h"
#include "../anx9804.h"

2
include/asm-generic/global_data.h
View file

@ -67,7 +67,7 @@ struct global_data {
* @mem_clk: memory clock rate in Hz
*/
unsigned long mem_clk;
#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO)
#if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO)
/**
* @fb_base: base address of frame buffer memory
*/

12
include/configs/T102xRDB.h
View file

@ -365,18 +365,6 @@
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
/* Video */
#undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
#define CONFIG_VIDEO_BMP_LOGO
/*
* With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
* disable empty flash sector detection, which is I/O-intensive.
*/
#undef CONFIG_SYS_FLASH_EMPTY_INFO
#endif
/* I2C */
#define I2C_PCA6408_BUS_NUM 1

20
include/configs/T104xRDB.h
View file

@ -345,19 +345,6 @@
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
#if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB)
/* Video */
#define CONFIG_FSL_DIU_FB
#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_FSL_DIU_CH7301
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
#define CONFIG_VIDEO_BMP_LOGO
#endif
#endif
/* I2C */
/* I2C bus multiplexer */
#define I2C_MUX_PCA_ADDR 0x70
#define I2C_MUX_CH_DEFAULT 0x8
@ -559,18 +546,11 @@
#define FDTFILE "t1042rdb/t1042d4rdb.dtb"
#endif
#ifdef CONFIG_FSL_DIU_FB
#define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
#else
#define DIU_ENVIRONMENT
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
"video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \

1
include/configs/apalis_imx6.h
View file

@ -45,7 +45,6 @@
#define CONFIG_USBD_HS
/* Framebuffer and LCD */
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP

1
include/configs/aristainetos2.h
View file

@ -438,7 +438,6 @@
/* Framebuffer */
/* check this console not needed, after test remove it */
#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX6_PWM_PER_CLK 66000000

2
include/configs/cm_fx6.h
View file

@ -171,8 +171,6 @@
/* Display */
#define CONFIG_IMX_HDMI
#define CONFIG_VIDEO_BMP_LOGO
/* EEPROM */
#endif /* __CONFIG_CM_FX6_H */

1
include/configs/colibri-imx6ull.h
View file

@ -165,7 +165,6 @@
#if defined(CONFIG_DM_VIDEO)
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#define CONFIG_VIDEO_BMP_LOGO
#endif
#endif /* __COLIBRI_IMX6ULL_CONFIG_H */

1
include/configs/colibri_imx6.h
View file

@ -35,7 +35,6 @@
#define CONFIG_USBD_HS
/* Framebuffer and LCD */
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP

4
include/configs/colibri_imx7.h
View file

@ -201,8 +201,4 @@
#define CONFIG_USBD_HS
#if defined(CONFIG_DM_VIDEO)
#define CONFIG_VIDEO_BMP_LOGO
#endif
#endif

8
include/configs/colibri_vf.h
View file

@ -14,14 +14,6 @@
#include <asm/arch/imx-regs.h>
#include <linux/sizes.h>
#ifdef CONFIG_VIDEO_FSL_DCU_FB
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_SYS_FSL_DCU_LE
#define CONFIG_SYS_DCU_ADDR DCU0_BASE_ADDR
#define DCU_LAYER_MAX_NUM 64
#endif
/* NAND support */
#define CONFIG_SYS_MAX_NAND_DEVICE 1

1
include/configs/embestmx6boards.h
View file

@ -50,7 +50,6 @@
#endif
/* Framebuffer */
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP

1
include/configs/gw_ventana.h
View file

@ -72,7 +72,6 @@
/* Framebuffer and LCD */
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_HIDE_LOGO_VERSION /* Custom config to hide U-boot version */
/* Miscellaneous configurable options */

2
include/configs/imx6-engicam.h
View file

@ -152,8 +152,6 @@
/* Framebuffer */
#ifdef CONFIG_VIDEO_IPUV3
# define CONFIG_IMX_VIDEO_SKIP
# define CONFIG_VIDEO_BMP_LOGO
#endif
/* SPL */

2
include/configs/imxrt1050-evk.h
View file

@ -21,8 +21,6 @@
DMAMEM_SZ_ALL)
#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_EXTRA_ENV_SETTINGS \
"stdin=serial\0" \
"stdout=serial,vidconsole\0" \

12
include/configs/ls1021aqds.h
View file

@ -299,18 +299,6 @@
* MMC
*/
/*
* Video
*/
#ifdef CONFIG_VIDEO_FSL_DCU_FB
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_FSL_DIU_CH7301
#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
#define CONFIG_SYS_I2C_DVI_ADDR 0x75
#endif
/*
* eTSEC
*/

15
include/configs/ls1021atwr.h
View file

@ -185,21 +185,6 @@
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 1
/*
* MMC
*/
/*
* Video
*/
#ifdef CONFIG_VIDEO_FSL_DCU_FB
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_FSL_DCU_SII9022A
#define CONFIG_SYS_I2C_DVI_BUS_NUM 1
#define CONFIG_SYS_I2C_DVI_ADDR 0x39
#endif
/* PCIe */
#define CONFIG_PCIE1 /* PCIE controller 1 */
#define CONFIG_PCIE2 /* PCIE controller 2 */

1
include/configs/mx6cuboxi.h
View file

@ -24,7 +24,6 @@
#endif
/* Framebuffer */
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP

1
include/configs/mx6sabre_common.h
View file

@ -151,7 +151,6 @@
/* Environment organization */
/* Framebuffer */
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP

1
include/configs/mx6sxsabresd.h
View file

@ -145,7 +145,6 @@
#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR
#endif
#endif

1
include/configs/mx6ul_14x14_evk.h
View file

@ -145,7 +145,6 @@
#ifndef CONFIG_SPL_BUILD
#if defined(CONFIG_DM_VIDEO)
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#endif
#endif

4
include/configs/mx7dsabresd.h
View file

@ -122,8 +122,4 @@
#define CONFIG_USBD_HS
#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_BMP_LOGO
#endif
#endif /* __CONFIG_H */

1
include/configs/opos6uldev.h
View file

@ -41,7 +41,6 @@
/* LCD */
#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#endif
#endif

1
include/configs/pico-imx6.h
View file

@ -133,7 +133,6 @@
#define CONFIG_FEC_MXC_PHYADDR 1
/* Framebuffer */
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP

1
include/configs/pico-imx6ul.h
View file

@ -129,7 +129,6 @@
#define CONFIG_BOARD_SIZE_LIMIT 715776
#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_BMP_LOGO
#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR
#endif

4
include/configs/pico-imx7d.h
View file

@ -119,10 +119,6 @@
#define CONFIG_POWER_PFUZE3000
#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08
#ifdef CONFIG_DM_VIDEO
#define CONFIG_VIDEO_BMP_LOGO
#endif
/* FLASH and environment organization */
/* Environment starts at 768k = 768 * 1024 = 786432 */

8
include/configs/pxm2.h
View file

@ -74,12 +74,4 @@
#endif
#endif /* CONFIG_SPL_BUILD */
#if defined(CONFIG_VIDEO)
#define CONFIG_VIDEO_DA8XX
#define CONFIG_VIDEO_BMP_LOGO
#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE
#define PWM_TICKS 0x1388
#define PWM_DUTY 0x200
#endif
#endif /* ! __CONFIG_PXM2_H */

1
include/configs/rpi.h
View file

@ -44,7 +44,6 @@
/* GPIO */
#define CONFIG_BCM2835_GPIO
/* LCD */
#define CONFIG_VIDEO_BCM2835
/* DFU over USB/UDC */
#ifdef CONFIG_CMD_DFU

10
include/configs/rut.h
View file

@ -67,14 +67,4 @@
#endif /* CONFIG_SPL_BUILD */
#if defined(CONFIG_VIDEO)
#define CONFIG_VIDEO_DA8XX
#define CONFIG_VIDEO_BMP_LOGO
#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE
#define BOARD_LCD_RESET 115 /* Bank 3 pin 19 */
#define CONFIG_FORMIKE
#define DISPL_PLL_SPREAD_SPECTRUM
#endif
#endif /* ! __CONFIG_RUT_H */

1
include/configs/wandboard.h
View file

@ -31,7 +31,6 @@
#define CONFIG_MXC_USB_FLAGS 0
/* Framebuffer */
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_IMX_HDMI
#define CONFIG_IMX_VIDEO_SKIP

22
include/fsl_dcu_fb.h
View file

@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* FSL DCU Framebuffer driver
*/
#include <linux/fb.h>
int fsl_dcu_init(struct fb_info *fbinfo,
unsigned int xres,
unsigned int yres,
unsigned int pixel_format);
int fsl_dcu_fixedfb_setup(void *blob);
/* Prototypes for external board-specific functions */
int platform_dcu_init(struct fb_info *fbinfo,
unsigned int xres,
unsigned int yres,
const char *port,
struct fb_videomode *dcu_fb_videomode);
unsigned int dcu_set_pixel_clock(unsigned int pixclock);

14
include/fsl_diu_fb.h
View file

@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2007, 2011 Freescale Semiconductor, Inc.
* Authors: York Sun <yorksun@freescale.com>
* Timur Tabi <timur@freescale.com>
*
* FSL DIU Framebuffer driver
*/
int fsl_diu_init(u16 xres, u16 yres, u32 pixel_format, int gamma_fix);
/* Prototypes for external board-specific functions */
int platform_diu_init(unsigned int xres, unsigned int yres, const char *port);
void diu_set_pixel_clock(unsigned int pixclock);

84
include/video.h
View file

@ -1,13 +1,7 @@
/*
* Video uclass and legacy implementation
* Video uclass to support displays (see also vidconsole for text)
*
* Copyright (c) 2015 Google, Inc
*
* MPC823 Video Controller
* =======================
* (C) 2000 by Paolo Scaffardi (arsenio@tin.it)
* AIRVENT SAM s.p.a - RIMINI(ITALY)
*
*/
#ifndef _VIDEO_H_
@ -155,7 +149,6 @@ struct video_ops {
*/
int video_reserve(ulong *addrp);
#ifdef CONFIG_DM_VIDEO
/**
* video_clear() - Clear a device's frame buffer to background color.
*
@ -163,7 +156,6 @@ int video_reserve(ulong *addrp);
* Return: 0
*/
int video_clear(struct udevice *dev);
#endif /* CONFIG_DM_VIDEO */
/**
* video_sync() - Sync a device's frame buffer with its hardware
@ -283,78 +275,4 @@ static inline int video_sync_copy_all(struct udevice *dev)
*/
bool video_is_active(void);
#ifndef CONFIG_DM_VIDEO
/* Video functions */
/**
* Display a BMP format bitmap on the screen
*
* @param bmp_image Address of BMP image
* @param x X position to draw image
* @param y Y position to draw image
*/
int video_display_bitmap(ulong bmp_image, int x, int y);
/**
* Get the width of the screen in pixels
*
* Return: width of screen in pixels
*/
int video_get_pixel_width(void);
/**
* Get the height of the screen in pixels
*
* Return: height of screen in pixels
*/
int video_get_pixel_height(void);
/**
* Get the number of text lines/rows on the screen
*
* Return: number of rows
*/
int video_get_screen_rows(void);
/**
* Get the number of text columns on the screen
*
* Return: number of columns
*/
int video_get_screen_columns(void);
/**
* Set the position of the text cursor
*
* @param col Column to place cursor (0 = left side)
* @param row Row to place cursor (0 = top line)
*/
void video_position_cursor(unsigned col, unsigned row);
/* Clear the display */
void video_clear(void);
#if defined(CONFIG_FORMIKE)
int kwh043st20_f01_spi_startup(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode);
#endif
#if defined(CONFIG_LG4573)
int lg4573_spi_startup(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode);
#endif
/*
* video_get_info_str() - obtain a board string: type, speed, etc.
*
* This is called if CONFIG_CONSOLE_EXTRA_INFO is enabled.
*
* line_number: location to place info string beside logo
* info: buffer for info string (empty if nothing to display on this
* line)
*/
void video_get_info_str(int line_number, char *info);
#endif /* !CONFIG_DM_VIDEO */
#endif

91
include/video_fb.h
View file

@ -1,91 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 1997-2002 ELTEC Elektronik AG
* Frank Gottschling <fgottschling@eltec.de>
*/
/*
* smiLynxEM.h
* Silicon Motion graphic interface for sm810/sm710/sm712 accelerator
*
*
* modification history
* --------------------
* 04-18-2002 Rewritten for U-Boot <fgottschling@eltec.de>.
*/
#ifndef _VIDEO_FB_H_
#define _VIDEO_FB_H_
/*
* Graphic Data Format (GDF) bits for VIDEO_DATA_FORMAT
*/
#define GDF__8BIT_INDEX 0
#define GDF_15BIT_555RGB 1
#define GDF_16BIT_565RGB 2
#define GDF_32BIT_X888RGB 3
#define GDF_24BIT_888RGB 4
#define GDF__8BIT_332RGB 5
/******************************************************************************/
/* Export Graphic Driver Control */
/******************************************************************************/
typedef struct graphic_device {
unsigned int isaBase;
unsigned int pciBase;
unsigned int dprBase;
unsigned int vprBase;
unsigned int cprBase;
unsigned int frameAdrs;
unsigned int memSize;
unsigned int mode;
unsigned int gdfIndex;
unsigned int gdfBytesPP;
unsigned int fg;
unsigned int bg;
unsigned int plnSizeX;
unsigned int plnSizeY;
unsigned int winSizeX;
unsigned int winSizeY;
char modeIdent[80];
} GraphicDevice;
/******************************************************************************/
/* Export Graphic Functions */
/******************************************************************************/
void *video_hw_init (void); /* returns GraphicDevice struct or NULL */
#ifdef VIDEO_HW_BITBLT
void video_hw_bitblt (
unsigned int bpp, /* bytes per pixel */
unsigned int src_x, /* source pos x */
unsigned int src_y, /* source pos y */
unsigned int dst_x, /* dest pos x */
unsigned int dst_y, /* dest pos y */
unsigned int dim_x, /* frame width */
unsigned int dim_y /* frame height */
);
#endif
#ifdef VIDEO_HW_RECTFILL
void video_hw_rectfill (
unsigned int bpp, /* bytes per pixel */
unsigned int dst_x, /* dest pos x */
unsigned int dst_y, /* dest pos y */
unsigned int dim_x, /* frame width */
unsigned int dim_y, /* frame height */
unsigned int color /* fill color */
);
#endif
void video_set_lut (
unsigned int index, /* color number */
unsigned char r, /* red */
unsigned char g, /* green */
unsigned char b /* blue */
);
#endif /*_VIDEO_FB_H_ */

1
lib/efi_loader/Kconfig
View file

@ -18,7 +18,6 @@ config EFI_LOADER
select PARTITION_UUIDS
select HAVE_BLOCK_DEVICE
select REGEX
imply CFB_CONSOLE_ANSI
imply FAT
imply FAT_WRITE
imply USB_KEYBOARD_FN_KEYS

10
scripts/config_whitelist.txt
View file

@ -151,16 +151,12 @@ CONFIG_FLASH_SHOW_PROGRESS
CONFIG_FLASH_SPANSION_S29WS_N
CONFIG_FLASH_VERIFY
CONFIG_FM_PLAT_CLK_DIV
CONFIG_FORMIKE
CONFIG_FPGA_COUNT
CONFIG_FPGA_STRATIX_V
CONFIG_FSL_CADMUS
CONFIG_FSL_CORENET
CONFIG_FSL_CPLD
CONFIG_FSL_DCU_SII9022A
CONFIG_FSL_DEVICE_DISABLE
CONFIG_FSL_DIU_CH7301
CONFIG_FSL_DIU_FB
CONFIG_FSL_DSPI1
CONFIG_FSL_ESDHC_PIN_MUX
CONFIG_FSL_FIXED_MMC_LOCATION
@ -989,7 +985,6 @@ CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
CONFIG_SYS_DIALOG_PMIC_I2C_ADDR
CONFIG_SYS_DIRECT_FLASH_TFTP
CONFIG_SYS_DISCOVER_PHY
CONFIG_SYS_DIU_ADDR
CONFIG_SYS_DPAA_DCE
CONFIG_SYS_DPAA_FMAN
CONFIG_SYS_DPAA_PME
@ -1131,8 +1126,6 @@ CONFIG_SYS_FSL_DCSR_DDR2_ADDR
CONFIG_SYS_FSL_DCSR_DDR3_ADDR
CONFIG_SYS_FSL_DCSR_DDR4_ADDR
CONFIG_SYS_FSL_DCSR_DDR_ADDR
CONFIG_SYS_FSL_DCU_BE
CONFIG_SYS_FSL_DCU_LE
CONFIG_SYS_FSL_DDR2_ADDR
CONFIG_SYS_FSL_DDR3_ADDR
CONFIG_SYS_FSL_DDR_ADDR
@ -2008,9 +2001,6 @@ CONFIG_USE_ONENAND_BOARD_INIT
CONFIG_U_BOOT_HDR_SIZE
CONFIG_VAR_SIZE_SPL
CONFIG_VERY_BIG_RAM
CONFIG_VIDEO_BCM2835
CONFIG_VIDEO_BMP_LOGO
CONFIG_VIDEO_DA8XX
CONFIG_VSC7385_ENET
CONFIG_VSC7385_IMAGE
CONFIG_VSC7385_IMAGE_SIZE