mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
ColdFire: MCF5445x header files cleanup
Signed-off-by: TsiChungLiew <Tsi-Chung.Liew@freescale.com> Signed-off by: John Rigby <jrigby@freescale.com>
This commit is contained in:
TsiChungLiew
parent
d9aae62609
commit
d2b1649348
2 changed files with 44 additions and 775 deletions
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@ -33,6 +33,7 @@
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#define MMAP_FEC0 0xFC030000
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#define MMAP_FEC1 0xFC034000
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#define MMAP_RTC 0xFC03C000
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#define MMAP_SCM2 0xFC040000
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#define MMAP_EDMA 0xFC044000
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#define MMAP_INTC0 0xFC048000
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#define MMAP_INTC1 0xFC04C000
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@ -63,11 +64,18 @@
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#define MMAP_SSI 0xFC0BC000
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#define MMAP_PLL 0xFC0C4000
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#define MMAP_ATA 0x90000000
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#define MMAP_USBHW 0xFC0B0000
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#define MMAP_USBCAPS 0xFC0B0100
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#define MMAP_USBEHCI 0xFC0B0140
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#define MMAP_USBOTG 0xFC0B01A0
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/*********************************************************************
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* ATA
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*********************************************************************/
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#include <asm/coldfire/crossbar.h>
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#include <asm/coldfire/dspi.h>
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#include <asm/coldfire/edma.h>
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#include <asm/coldfire/flexbus.h>
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#include <asm/coldfire/ssi.h>
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/* ATA */
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typedef struct atac {
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/* PIO */
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u8 toff; /* 0x00 */
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@ -117,379 +125,7 @@ typedef struct atac {
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u8 rsvd6[106];
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} atac_t;
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/*********************************************************************
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* Cross-bar switch (XBS)
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*********************************************************************/
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typedef struct xbs {
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u8 resv0[0x100];
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u32 prs1; /* XBS Priority Register */
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u8 resv1[0xC];
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u32 crs1; /* XBS Control Register */
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u8 resv2[0xEC];
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u32 prs2; /* XBS Priority Register */
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u8 resv3[0xC];
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u32 crs2; /* XBS Control Register */
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u8 resv4[0xEC];
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u32 prs3; /* XBS Priority Register */
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u8 resv5[0xC];
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u32 crs3; /* XBS Control Register */
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u8 resv6[0xEC];
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u32 prs4; /* XBS Priority Register */
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u8 resv7[0xC];
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u32 crs4; /* XBS Control Register */
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u8 resv8[0xEC];
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u32 prs5; /* XBS Priority Register */
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u8 resv9[0xC];
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u32 crs5; /* XBS Control Register */
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u8 resv10[0xEC];
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u32 prs6; /* XBS Priority Register */
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u8 resv11[0xC];
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u32 crs6; /* XBS Control Register */
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u8 resv12[0xEC];
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u32 prs7; /* XBS Priority Register */
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u8 resv13[0xC];
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u32 crs7; /* XBS Control Register */
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} xbs_t;
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/*********************************************************************
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* FlexBus Chip Selects (FBCS)
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*********************************************************************/
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typedef struct fbcs {
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u32 csar0; /* Chip-select Address Register */
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u32 csmr0; /* Chip-select Mask Register */
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u32 cscr0; /* Chip-select Control Register */
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u32 csar1; /* Chip-select Address Register */
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u32 csmr1; /* Chip-select Mask Register */
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u32 cscr1; /* Chip-select Control Register */
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u32 csar2; /* Chip-select Address Register */
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u32 csmr2; /* Chip-select Mask Register */
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u32 cscr2; /* Chip-select Control Register */
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u32 csar3; /* Chip-select Address Register */
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u32 csmr3; /* Chip-select Mask Register */
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u32 cscr3; /* Chip-select Control Register */
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} fbcs_t;
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/*********************************************************************
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* Enhanced DMA (EDMA)
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*********************************************************************/
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typedef struct edma {
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u32 cr;
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u32 es;
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u8 resv0[0x6];
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u16 erq;
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u8 resv1[0x6];
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u16 eei;
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u8 serq;
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u8 cerq;
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u8 seei;
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u8 ceei;
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u8 cint;
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u8 cerr;
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u8 ssrt;
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u8 cdne;
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u8 resv2[0x6];
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u16 intr;
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u8 resv3[0x6];
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u16 err;
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u8 resv4[0xD0];
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u8 dchpri0;
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u8 dchpri1;
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u8 dchpri2;
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u8 dchpri3;
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u8 dchpri4;
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u8 dchpri5;
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u8 dchpri6;
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u8 dchpri7;
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u8 dchpri8;
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u8 dchpri9;
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u8 dchpri10;
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u8 dchpri11;
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u8 dchpri12;
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u8 dchpri13;
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u8 dchpri14;
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u8 dchpri15;
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u8 resv5[0xEF0];
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u32 tcd0_saddr;
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u16 tcd0_attr;
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u16 tcd0_soff;
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u32 tcd0_nbytes;
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u32 tcd0_slast;
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u32 tcd0_daddr;
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union {
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u16 tcd0_citer_elink;
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u16 tcd0_citer;
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};
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u16 tcd0_doff;
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u32 tcd0_dlast_sga;
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union {
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u16 tcd0_biter_elink;
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u16 tcd0_biter;
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};
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u16 tcd0_csr;
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u32 tcd1_saddr;
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u16 tcd1_attr;
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u16 tcd1_soff;
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u32 tcd1_nbytes;
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u32 tcd1_slast;
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u32 tcd1_daddr;
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union {
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u16 tcd1_citer_elink;
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u16 tcd1_citer;
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};
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u16 tcd1_doff;
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u32 tcd1_dlast_sga;
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union {
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u16 tcd1_biter;
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u16 tcd1_biter_elink;
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};
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u16 tcd1_csr;
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u32 tcd2_saddr;
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u16 tcd2_attr;
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u16 tcd2_soff;
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u32 tcd2_nbytes;
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u32 tcd2_slast;
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u32 tcd2_daddr;
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union {
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u16 tcd2_citer;
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u16 tcd2_citer_elink;
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};
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u16 tcd2_doff;
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u32 tcd2_dlast_sga;
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union {
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u16 tcd2_biter_elink;
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u16 tcd2_biter;
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};
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u16 tcd2_csr;
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u32 tcd3_saddr;
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u16 tcd3_attr;
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u16 tcd3_soff;
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u32 tcd3_nbytes;
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u32 tcd3_slast;
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u32 tcd3_daddr;
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union {
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u16 tcd3_citer;
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u16 tcd3_citer_elink;
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};
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u16 tcd3_doff;
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u32 tcd3_dlast_sga;
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union {
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u16 tcd3_biter_elink;
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u16 tcd3_biter;
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};
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u16 tcd3_csr;
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u32 tcd4_saddr;
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u16 tcd4_attr;
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u16 tcd4_soff;
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u32 tcd4_nbytes;
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u32 tcd4_slast;
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u32 tcd4_daddr;
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union {
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u16 tcd4_citer;
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u16 tcd4_citer_elink;
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};
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u16 tcd4_doff;
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u32 tcd4_dlast_sga;
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union {
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u16 tcd4_biter;
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u16 tcd4_biter_elink;
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};
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u16 tcd4_csr;
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u32 tcd5_saddr;
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u16 tcd5_attr;
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u16 tcd5_soff;
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u32 tcd5_nbytes;
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u32 tcd5_slast;
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u32 tcd5_daddr;
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union {
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u16 tcd5_citer;
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u16 tcd5_citer_elink;
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};
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u16 tcd5_doff;
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u32 tcd5_dlast_sga;
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union {
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u16 tcd5_biter_elink;
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u16 tcd5_biter;
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};
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u16 tcd5_csr;
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u32 tcd6_saddr;
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u16 tcd6_attr;
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u16 tcd6_soff;
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u32 tcd6_nbytes;
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u32 tcd6_slast;
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u32 tcd6_daddr;
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union {
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u16 tcd6_citer;
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u16 tcd6_citer_elink;
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};
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u16 tcd6_doff;
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u32 tcd6_dlast_sga;
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union {
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u16 tcd6_biter_elink;
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u16 tcd6_biter;
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};
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u16 tcd6_csr;
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u32 tcd7_saddr;
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u16 tcd7_attr;
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u16 tcd7_soff;
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u32 tcd7_nbytes;
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u32 tcd7_slast;
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u32 tcd7_daddr;
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union {
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u16 tcd7_citer;
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u16 tcd7_citer_elink;
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};
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u16 tcd7_doff;
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u32 tcd7_dlast_sga;
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union {
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u16 tcd7_biter_elink;
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u16 tcd7_biter;
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};
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u16 tcd7_csr;
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u32 tcd8_saddr;
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u16 tcd8_attr;
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u16 tcd8_soff;
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u32 tcd8_nbytes;
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u32 tcd8_slast;
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u32 tcd8_daddr;
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union {
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u16 tcd8_citer;
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u16 tcd8_citer_elink;
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};
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u16 tcd8_doff;
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u32 tcd8_dlast_sga;
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union {
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u16 tcd8_biter_elink;
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u16 tcd8_biter;
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};
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u16 tcd8_csr;
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u32 tcd9_saddr;
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u16 tcd9_attr;
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u16 tcd9_soff;
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u32 tcd9_nbytes;
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u32 tcd9_slast;
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u32 tcd9_daddr;
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union {
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u16 tcd9_citer_elink;
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u16 tcd9_citer;
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};
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u16 tcd9_doff;
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u32 tcd9_dlast_sga;
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union {
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u16 tcd9_biter_elink;
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u16 tcd9_biter;
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};
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u16 tcd9_csr;
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u32 tcd10_saddr;
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u16 tcd10_attr;
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u16 tcd10_soff;
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u32 tcd10_nbytes;
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u32 tcd10_slast;
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u32 tcd10_daddr;
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union {
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u16 tcd10_citer_elink;
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u16 tcd10_citer;
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};
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u16 tcd10_doff;
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u32 tcd10_dlast_sga;
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union {
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u16 tcd10_biter;
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u16 tcd10_biter_elink;
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};
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u16 tcd10_csr;
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u32 tcd11_saddr;
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u16 tcd11_attr;
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u16 tcd11_soff;
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u32 tcd11_nbytes;
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u32 tcd11_slast;
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u32 tcd11_daddr;
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union {
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u16 tcd11_citer;
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u16 tcd11_citer_elink;
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};
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u16 tcd11_doff;
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u32 tcd11_dlast_sga;
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union {
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u16 tcd11_biter;
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u16 tcd11_biter_elink;
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};
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u16 tcd11_csr;
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u32 tcd12_saddr;
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u16 tcd12_attr;
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u16 tcd12_soff;
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u32 tcd12_nbytes;
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u32 tcd12_slast;
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u32 tcd12_daddr;
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union {
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u16 tcd12_citer;
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u16 tcd12_citer_elink;
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};
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u16 tcd12_doff;
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u32 tcd12_dlast_sga;
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union {
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u16 tcd12_biter;
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u16 tcd12_biter_elink;
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};
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u16 tcd12_csr;
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u32 tcd13_saddr;
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u16 tcd13_attr;
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u16 tcd13_soff;
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u32 tcd13_nbytes;
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u32 tcd13_slast;
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u32 tcd13_daddr;
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union {
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u16 tcd13_citer_elink;
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u16 tcd13_citer;
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};
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u16 tcd13_doff;
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u32 tcd13_dlast_sga;
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union {
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u16 tcd13_biter_elink;
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u16 tcd13_biter;
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};
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u16 tcd13_csr;
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u32 tcd14_saddr;
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u16 tcd14_attr;
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u16 tcd14_soff;
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u32 tcd14_nbytes;
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u32 tcd14_slast;
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u32 tcd14_daddr;
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union {
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u16 tcd14_citer;
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u16 tcd14_citer_elink;
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};
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u16 tcd14_doff;
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u32 tcd14_dlast_sga;
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union {
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u16 tcd14_biter_elink;
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u16 tcd14_biter;
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};
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u16 tcd14_csr;
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u32 tcd15_saddr;
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u16 tcd15_attr;
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u16 tcd15_soff;
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u32 tcd15_nbytes;
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u32 tcd15_slast;
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u32 tcd15_daddr;
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union {
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u16 tcd15_citer_elink;
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u16 tcd15_citer;
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};
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u16 tcd15_doff;
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u32 tcd15_dlast_sga;
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union {
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u16 tcd15_biter;
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u16 tcd15_biter_elink;
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};
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u16 tcd15_csr;
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} edma_t;
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/*********************************************************************
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* Interrupt Controller (INTC)
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*********************************************************************/
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/* Interrupt Controller (INTC) */
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typedef struct int0_ctrl {
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u32 iprh0; /* 0x00 Pending Register High */
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u32 iprl0; /* 0x04 Pending Register Low */
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@ -558,10 +194,7 @@ typedef struct int1_ctrl {
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u8 resc[3]; /* 0xFD - 0xFF */
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} int1_t;
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/*********************************************************************
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* Global Interrupt Acknowledge (IACK)
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*********************************************************************/
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/* Global Interrupt Acknowledge (IACK) */
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typedef struct iack {
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u8 resv0[0xE0];
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u8 gswiack;
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@ -581,41 +214,7 @@ typedef struct iack {
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u8 gl7iack;
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} iack_t;
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/*********************************************************************
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* DMA Serial Peripheral Interface (DSPI)
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*********************************************************************/
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typedef struct dspi {
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u32 dmcr;
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u8 resv0[0x4];
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u32 dtcr;
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u32 dctar0;
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u32 dctar1;
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u32 dctar2;
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u32 dctar3;
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u32 dctar4;
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u32 dctar5;
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u32 dctar6;
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u32 dctar7;
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u32 dsr;
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u32 dirsr;
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u32 dtfr;
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u32 drfr;
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u32 dtfdr0;
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u32 dtfdr1;
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u32 dtfdr2;
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u32 dtfdr3;
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u8 resv1[0x30];
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u32 drfdr0;
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u32 drfdr1;
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u32 drfdr2;
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u32 drfdr3;
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} dspi_t;
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/*********************************************************************
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* Edge Port Module (EPORT)
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*********************************************************************/
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/* Edge Port Module (EPORT) */
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typedef struct eport {
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u16 eppar;
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u8 epddr;
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@ -625,10 +224,7 @@ typedef struct eport {
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u8 epfr;
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} eport_t;
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/*********************************************************************
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* Watchdog Timer Modules (WTM)
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*********************************************************************/
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/* Watchdog Timer Modules (WTM) */
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typedef struct wtm {
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u16 wcr;
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u16 wmr;
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@ -636,10 +232,7 @@ typedef struct wtm {
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u16 wsr;
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} wtm_t;
|
||||
|
||||
/*********************************************************************
|
||||
* Serial Boot Facility (SBF)
|
||||
*********************************************************************/
|
||||
|
||||
/* Serial Boot Facility (SBF) */
|
||||
typedef struct sbf {
|
||||
u8 resv0[0x18];
|
||||
u16 sbfsr; /* Serial Boot Facility Status Register */
|
||||
|
|
@ -647,19 +240,13 @@ typedef struct sbf {
|
|||
u16 sbfcr; /* Serial Boot Facility Control Register */
|
||||
} sbf_t;
|
||||
|
||||
/*********************************************************************
|
||||
* Reset Controller Module (RCM)
|
||||
*********************************************************************/
|
||||
|
||||
/* Reset Controller Module (RCM) */
|
||||
typedef struct rcm {
|
||||
u8 rcr;
|
||||
u8 rsr;
|
||||
} rcm_t;
|
||||
|
||||
/*********************************************************************
|
||||
* Chip Configuration Module (CCM)
|
||||
*********************************************************************/
|
||||
|
||||
/* Chip Configuration Module (CCM) */
|
||||
typedef struct ccm {
|
||||
u8 ccm_resv0[0x4];
|
||||
u16 ccr; /* Chip Configuration Register (256 TEPBGA, Read-only) */
|
||||
|
|
@ -672,10 +259,7 @@ typedef struct ccm {
|
|||
u16 uocsr; /* USB On-the-Go Controller Status Register */
|
||||
} ccm_t;
|
||||
|
||||
/*********************************************************************
|
||||
* General Purpose I/O Module (GPIO)
|
||||
*********************************************************************/
|
||||
|
||||
/* General Purpose I/O Module (GPIO) */
|
||||
typedef struct gpio {
|
||||
u8 podr_fec0h; /* FEC0 High Port Output Data Register */
|
||||
u8 podr_fec0l; /* FEC0 Low Port Output Data Register */
|
||||
|
|
@ -803,10 +387,7 @@ typedef struct gpio {
|
|||
u8 dscr_ata; /* ATA Drive Strength Control Register */
|
||||
} gpio_t;
|
||||
|
||||
/*********************************************************************
|
||||
* Random Number Generator (RNG)
|
||||
*********************************************************************/
|
||||
|
||||
/* Random Number Generator (RNG) */
|
||||
typedef struct rng {
|
||||
u32 rngcr;
|
||||
u32 rngsr;
|
||||
|
|
@ -814,10 +395,7 @@ typedef struct rng {
|
|||
u32 rngout;
|
||||
} rng_t;
|
||||
|
||||
/*********************************************************************
|
||||
* SDRAM Controller (SDRAMC)
|
||||
*********************************************************************/
|
||||
|
||||
/* SDRAM Controller (SDRAMC) */
|
||||
typedef struct sdramc {
|
||||
u32 sdmr; /* SDRAM Mode/Extended Mode Register */
|
||||
u32 sdcr; /* SDRAM Control Register */
|
||||
|
|
@ -828,36 +406,7 @@ typedef struct sdramc {
|
|||
u32 sdcs1; /* SDRAM Mode/Extended Mode Register */
|
||||
} sdramc_t;
|
||||
|
||||
/*********************************************************************
|
||||
* Synchronous Serial Interface (SSI)
|
||||
*********************************************************************/
|
||||
|
||||
typedef struct ssi {
|
||||
u32 tx0;
|
||||
u32 tx1;
|
||||
u32 rx0;
|
||||
u32 rx1;
|
||||
u32 cr;
|
||||
u32 isr;
|
||||
u32 ier;
|
||||
u32 tcr;
|
||||
u32 rcr;
|
||||
u32 ccr;
|
||||
u8 resv0[0x4];
|
||||
u32 fcsr;
|
||||
u8 resv1[0x8];
|
||||
u32 acr;
|
||||
u32 acadd;
|
||||
u32 acdat;
|
||||
u32 atag;
|
||||
u32 tmask;
|
||||
u32 rmask;
|
||||
} ssi_t;
|
||||
|
||||
/*********************************************************************
|
||||
* Phase Locked Loop (PLL)
|
||||
*********************************************************************/
|
||||
|
||||
/* Phase Locked Loop (PLL) */
|
||||
typedef struct pll {
|
||||
u32 pcr; /* PLL Control Register */
|
||||
u32 psr; /* PLL Status Register */
|
||||
|
|
@ -927,7 +476,27 @@ typedef struct scm1 {
|
|||
u32 pacrf; /* 0x44 Peripheral Access Control Register F */
|
||||
u32 pacrg; /* 0x48 Peripheral Access Control Register G */
|
||||
} scm1_t;
|
||||
/********************************************************************/
|
||||
|
||||
typedef struct scm2 {
|
||||
u8 rsvd1[19]; /* 0x00 - 0x12 */
|
||||
u8 wcr; /* 0x13 */
|
||||
u16 rsvd2; /* 0x14 - 0x15 */
|
||||
u16 cwcr; /* 0x16 */
|
||||
u8 rsvd3[3]; /* 0x18 - 0x1A */
|
||||
u8 cwsr; /* 0x1B */
|
||||
u8 rsvd4[3]; /* 0x1C - 0x1E */
|
||||
u8 scmisr; /* 0x1F */
|
||||
u32 rsvd5; /* 0x20 - 0x23 */
|
||||
u8 bcr; /* 0x24 */
|
||||
u8 rsvd6[74]; /* 0x25 - 0x6F */
|
||||
u32 cfadr; /* 0x70 */
|
||||
u8 rsvd7; /* 0x74 */
|
||||
u8 cfier; /* 0x75 */
|
||||
u8 cfloc; /* 0x76 */
|
||||
u8 cfatr; /* 0x77 */
|
||||
u32 rsvd8; /* 0x78 - 0x7B */
|
||||
u32 cfdtr; /* 0x7C */
|
||||
} scm2_t;
|
||||
|
||||
typedef struct rtcex {
|
||||
u32 rsvd1[3];
|
||||
|
|
|
|||
|
|
@ -26,84 +26,6 @@
|
|||
#ifndef __MCF5445X__
|
||||
#define __MCF5445X__
|
||||
|
||||
/*********************************************************************
|
||||
* Cross-bar switch (XBS)
|
||||
*********************************************************************/
|
||||
|
||||
/* Bit definitions and macros for PRS group */
|
||||
#define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */
|
||||
#define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */
|
||||
#define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */
|
||||
#define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */
|
||||
#define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */
|
||||
#define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */
|
||||
#define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */
|
||||
|
||||
/* Bit definitions and macros for CRS group */
|
||||
#define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */
|
||||
#define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */
|
||||
#define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */
|
||||
#define XBS_CRS_RO (0x80000000) /* Read Only */
|
||||
|
||||
#define XBS_CRS_PCTL_PARK_FIELD (0)
|
||||
#define XBS_CRS_PCTL_PARK_ON_LAST (1)
|
||||
#define XBS_CRS_PCTL_PARK_NONE (2)
|
||||
#define XBS_CRS_PCTL_PARK_CORE (0)
|
||||
#define XBS_CRS_PCTL_PARK_EDMA (1)
|
||||
#define XBS_CRS_PCTL_PARK_FEC0 (2)
|
||||
#define XBS_CRS_PCTL_PARK_FEC1 (3)
|
||||
#define XBS_CRS_PCTL_PARK_PCI (5)
|
||||
#define XBS_CRS_PCTL_PARK_USB (6)
|
||||
#define XBS_CRS_PCTL_PARK_SBF (7)
|
||||
|
||||
/*********************************************************************
|
||||
* FlexBus Chip Selects (FBCS)
|
||||
*********************************************************************/
|
||||
|
||||
/* Bit definitions and macros for CSAR group */
|
||||
#define FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
|
||||
|
||||
/* Bit definitions and macros for CSMR group */
|
||||
#define FBCS_CSMR_V (0x00000001) /* Valid bit */
|
||||
#define FBCS_CSMR_WP (0x00000100) /* Write protect */
|
||||
#define FBCS_CSMR_BAM(x) (((x)&0x0000FFFF)<<16) /* Base address mask */
|
||||
#define FBCS_CSMR_BAM_4G (0xFFFF0000)
|
||||
#define FBCS_CSMR_BAM_2G (0x7FFF0000)
|
||||
#define FBCS_CSMR_BAM_1G (0x3FFF0000)
|
||||
#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
|
||||
#define FBCS_CSMR_BAM_512M (0x1FFF0000)
|
||||
#define FBCS_CSMR_BAM_256M (0x0FFF0000)
|
||||
#define FBCS_CSMR_BAM_128M (0x07FF0000)
|
||||
#define FBCS_CSMR_BAM_64M (0x03FF0000)
|
||||
#define FBCS_CSMR_BAM_32M (0x01FF0000)
|
||||
#define FBCS_CSMR_BAM_16M (0x00FF0000)
|
||||
#define FBCS_CSMR_BAM_8M (0x007F0000)
|
||||
#define FBCS_CSMR_BAM_4M (0x003F0000)
|
||||
#define FBCS_CSMR_BAM_2M (0x001F0000)
|
||||
#define FBCS_CSMR_BAM_1M (0x000F0000)
|
||||
#define FBCS_CSMR_BAM_1024K (0x000F0000)
|
||||
#define FBCS_CSMR_BAM_512K (0x00070000)
|
||||
#define FBCS_CSMR_BAM_256K (0x00030000)
|
||||
#define FBCS_CSMR_BAM_128K (0x00010000)
|
||||
#define FBCS_CSMR_BAM_64K (0x00000000)
|
||||
|
||||
/* Bit definitions and macros for CSCR group */
|
||||
#define FBCS_CSCR_BSTW (0x00000008) /* Burst-write enable */
|
||||
#define FBCS_CSCR_BSTR (0x00000010) /* Burst-read enable */
|
||||
#define FBCS_CSCR_BEM (0x00000020) /* Byte-enable mode */
|
||||
#define FBCS_CSCR_PS(x) (((x)&0x00000003)<<6) /* Port size */
|
||||
#define FBCS_CSCR_AA (0x00000100) /* Auto-acknowledge */
|
||||
#define FBCS_CSCR_WS(x) (((x)&0x0000003F)<<10) /* Wait states */
|
||||
#define FBCS_CSCR_WRAH(x) (((x)&0x00000003)<<16) /* Write address hold or deselect */
|
||||
#define FBCS_CSCR_RDAH(x) (((x)&0x00000003)<<18) /* Read address hold or deselect */
|
||||
#define FBCS_CSCR_ASET(x) (((x)&0x00000003)<<20) /* Address setup */
|
||||
#define FBCS_CSCR_SWSEN (0x00800000) /* Secondary wait state enable */
|
||||
#define FBCS_CSCR_SWS(x) (((x)&0x0000003F)<<26) /* Secondary wait states */
|
||||
|
||||
#define FBCS_CSCR_PS_8 (0x00000040)
|
||||
#define FBCS_CSCR_PS_16 (0x00000080)
|
||||
#define FBCS_CSCR_PS_32 (0x00000000)
|
||||
|
||||
/*********************************************************************
|
||||
* Interrupt Controller (INTC)
|
||||
*********************************************************************/
|
||||
|
|
@ -421,106 +343,6 @@
|
|||
/* Bit definitions and macros for ICR group */
|
||||
#define INTC_ICR_IL(x) (((x)&0x07))
|
||||
|
||||
/*********************************************************************
|
||||
* DMA Serial Peripheral Interface (DSPI)
|
||||
*********************************************************************/
|
||||
|
||||
/* Bit definitions and macros for DMCR */
|
||||
#define DSPI_DMCR_HALT (0x00000001)
|
||||
#define DSPI_DMCR_SMPL_PT(x) (((x)&0x00000003)<<8)
|
||||
#define DSPI_DMCR_CRXF (0x00000400)
|
||||
#define DSPI_DMCR_CTXF (0x00000800)
|
||||
#define DSPI_DMCR_DRXF (0x00001000)
|
||||
#define DSPI_DMCR_DTXF (0x00002000)
|
||||
#define DSPI_DMCR_CSIS0 (0x00010000)
|
||||
#define DSPI_DMCR_CSIS2 (0x00040000)
|
||||
#define DSPI_DMCR_CSIS3 (0x00080000)
|
||||
#define DSPI_DMCR_CSIS5 (0x00200000)
|
||||
#define DSPI_DMCR_ROOE (0x01000000)
|
||||
#define DSPI_DMCR_PCSSE (0x02000000)
|
||||
#define DSPI_DMCR_MTFE (0x04000000)
|
||||
#define DSPI_DMCR_FRZ (0x08000000)
|
||||
#define DSPI_DMCR_DCONF(x) (((x)&0x00000003)<<28)
|
||||
#define DSPI_DMCR_CSCK (0x40000000)
|
||||
#define DSPI_DMCR_MSTR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for DTCR */
|
||||
#define DSPI_DTCR_SPI_TCNT(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/* Bit definitions and macros for DCTAR group */
|
||||
#define DSPI_DCTAR_BR(x) (((x)&0x0000000F))
|
||||
#define DSPI_DCTAR_DT(x) (((x)&0x0000000F)<<4)
|
||||
#define DSPI_DCTAR_ASC(x) (((x)&0x0000000F)<<8)
|
||||
#define DSPI_DCTAR_CSSCK(x) (((x)&0x0000000F)<<12)
|
||||
#define DSPI_DCTAR_PBR(x) (((x)&0x00000003)<<16)
|
||||
#define DSPI_DCTAR_PDT(x) (((x)&0x00000003)<<18)
|
||||
#define DSPI_DCTAR_PASC(x) (((x)&0x00000003)<<20)
|
||||
#define DSPI_DCTAR_PCSSCK(x) (((x)&0x00000003)<<22)
|
||||
#define DSPI_DCTAR_LSBFE (0x01000000)
|
||||
#define DSPI_DCTAR_CPHA (0x02000000)
|
||||
#define DSPI_DCTAR_CPOL (0x04000000)
|
||||
#define DSPI_DCTAR_TRSZ(x) (((x)&0x0000000F)<<27)
|
||||
#define DSPI_DCTAR_PCSSCK_1CLK (0x00000000)
|
||||
#define DSPI_DCTAR_PCSSCK_3CLK (0x00400000)
|
||||
#define DSPI_DCTAR_PCSSCK_5CLK (0x00800000)
|
||||
#define DSPI_DCTAR_PCSSCK_7CLK (0x00A00000)
|
||||
#define DSPI_DCTAR_PASC_1CLK (0x00000000)
|
||||
#define DSPI_DCTAR_PASC_3CLK (0x00100000)
|
||||
#define DSPI_DCTAR_PASC_5CLK (0x00200000)
|
||||
#define DSPI_DCTAR_PASC_7CLK (0x00300000)
|
||||
#define DSPI_DCTAR_PDT_1CLK (0x00000000)
|
||||
#define DSPI_DCTAR_PDT_3CLK (0x00040000)
|
||||
#define DSPI_DCTAR_PDT_5CLK (0x00080000)
|
||||
#define DSPI_DCTAR_PDT_7CLK (0x000A0000)
|
||||
#define DSPI_DCTAR_PBR_1CLK (0x00000000)
|
||||
#define DSPI_DCTAR_PBR_3CLK (0x00010000)
|
||||
#define DSPI_DCTAR_PBR_5CLK (0x00020000)
|
||||
#define DSPI_DCTAR_PBR_7CLK (0x00030000)
|
||||
|
||||
/* Bit definitions and macros for DSR */
|
||||
#define DSPI_DSR_RXPTR(x) (((x)&0x0000000F))
|
||||
#define DSPI_DSR_RXCTR(x) (((x)&0x0000000F)<<4)
|
||||
#define DSPI_DSR_TXPTR(x) (((x)&0x0000000F)<<8)
|
||||
#define DSPI_DSR_TXCTR(x) (((x)&0x0000000F)<<12)
|
||||
#define DSPI_DSR_RFDF (0x00020000)
|
||||
#define DSPI_DSR_RFOF (0x00080000)
|
||||
#define DSPI_DSR_TFFF (0x02000000)
|
||||
#define DSPI_DSR_TFUF (0x08000000)
|
||||
#define DSPI_DSR_EOQF (0x10000000)
|
||||
#define DSPI_DSR_TXRXS (0x40000000)
|
||||
#define DSPI_DSR_TCF (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for DIRSR */
|
||||
#define DSPI_DIRSR_RFDFS (0x00010000)
|
||||
#define DSPI_DIRSR_RFDFE (0x00020000)
|
||||
#define DSPI_DIRSR_RFOFE (0x00080000)
|
||||
#define DSPI_DIRSR_TFFFS (0x01000000)
|
||||
#define DSPI_DIRSR_TFFFE (0x02000000)
|
||||
#define DSPI_DIRSR_TFUFE (0x08000000)
|
||||
#define DSPI_DIRSR_EOQFE (0x10000000)
|
||||
#define DSPI_DIRSR_TCFE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for DTFR */
|
||||
#define DSPI_DTFR_TXDATA(x) (((x)&0x0000FFFF))
|
||||
#define DSPI_DTFR_CS0 (0x00010000)
|
||||
#define DSPI_DTFR_CS2 (0x00040000)
|
||||
#define DSPI_DTFR_CS3 (0x00080000)
|
||||
#define DSPI_DTFR_CS5 (0x00200000)
|
||||
#define DSPI_DTFR_CTCNT (0x04000000)
|
||||
#define DSPI_DTFR_EOQ (0x08000000)
|
||||
#define DSPI_DTFR_CTAS(x) (((x)&0x00000007)<<28)
|
||||
#define DSPI_DTFR_CONT (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for DRFR */
|
||||
#define DSPI_DRFR_RXDATA(x) (((x)&0x0000FFFF))
|
||||
|
||||
/* Bit definitions and macros for DTFDR group */
|
||||
#define DSPI_DTFDR_TXDATA(x) (((x)&0x0000FFFF))
|
||||
#define DSPI_DTFDR_TXCMD(x) (((x)&0x0000FFFF)<<16)
|
||||
|
||||
/* Bit definitions and macros for DRFDR group */
|
||||
#define DSPI_DRFDR_RXDATA(x) (((x)&0x0000FFFF))
|
||||
|
||||
/*********************************************************************
|
||||
* Edge Port Module (EPORT)
|
||||
*********************************************************************/
|
||||
|
|
@ -1297,127 +1119,6 @@
|
|||
#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
|
||||
#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
|
||||
|
||||
/*********************************************************************
|
||||
* Synchronous Serial Interface (SSI)
|
||||
*********************************************************************/
|
||||
|
||||
/* Bit definitions and macros for CR */
|
||||
#define SSI_CR_SSI_EN (0x00000001)
|
||||
#define SSI_CR_TE (0x00000002)
|
||||
#define SSI_CR_RE (0x00000004)
|
||||
#define SSI_CR_NET (0x00000008)
|
||||
#define SSI_CR_SYN (0x00000010)
|
||||
#define SSI_CR_I2S(x) (((x)&0x00000003)<<5)
|
||||
#define SSI_CR_MCE (0x00000080)
|
||||
#define SSI_CR_TCH (0x00000100)
|
||||
#define SSI_CR_CIS (0x00000200)
|
||||
#define SSI_CR_I2S_NORMAL (0x00000000)
|
||||
#define SSI_CR_I2S_MASTER (0x00000020)
|
||||
#define SSI_CR_I2S_SLAVE (0x00000040)
|
||||
|
||||
/* Bit definitions and macros for ISR */
|
||||
#define SSI_ISR_TFE0 (0x00000001)
|
||||
#define SSI_ISR_TFE1 (0x00000002)
|
||||
#define SSI_ISR_RFF0 (0x00000004)
|
||||
#define SSI_ISR_RFF1 (0x00000008)
|
||||
#define SSI_ISR_RLS (0x00000010)
|
||||
#define SSI_ISR_TLS (0x00000020)
|
||||
#define SSI_ISR_RFS (0x00000040)
|
||||
#define SSI_ISR_TFS (0x00000080)
|
||||
#define SSI_ISR_TUE0 (0x00000100)
|
||||
#define SSI_ISR_TUE1 (0x00000200)
|
||||
#define SSI_ISR_ROE0 (0x00000400)
|
||||
#define SSI_ISR_ROE1 (0x00000800)
|
||||
#define SSI_ISR_TDE0 (0x00001000)
|
||||
#define SSI_ISR_TDE1 (0x00002000)
|
||||
#define SSI_ISR_RDR0 (0x00004000)
|
||||
#define SSI_ISR_RDR1 (0x00008000)
|
||||
#define SSI_ISR_RXT (0x00010000)
|
||||
#define SSI_ISR_CMDDU (0x00020000)
|
||||
#define SSI_ISR_CMDAU (0x00040000)
|
||||
|
||||
/* Bit definitions and macros for IER */
|
||||
#define SSI_IER_TFE0 (0x00000001)
|
||||
#define SSI_IER_TFE1 (0x00000002)
|
||||
#define SSI_IER_RFF0 (0x00000004)
|
||||
#define SSI_IER_RFF1 (0x00000008)
|
||||
#define SSI_IER_RLS (0x00000010)
|
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#define SSI_IER_TLS (0x00000020)
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#define SSI_IER_RFS (0x00000040)
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||||
#define SSI_IER_TFS (0x00000080)
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#define SSI_IER_TUE0 (0x00000100)
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#define SSI_IER_TUE1 (0x00000200)
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||||
#define SSI_IER_ROE0 (0x00000400)
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||||
#define SSI_IER_ROE1 (0x00000800)
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||||
#define SSI_IER_TDE0 (0x00001000)
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||||
#define SSI_IER_TDE1 (0x00002000)
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||||
#define SSI_IER_RDR0 (0x00004000)
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||||
#define SSI_IER_RDR1 (0x00008000)
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||||
#define SSI_IER_RXT (0x00010000)
|
||||
#define SSI_IER_CMDU (0x00020000)
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||||
#define SSI_IER_CMDAU (0x00040000)
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||||
#define SSI_IER_TIE (0x00080000)
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||||
#define SSI_IER_TDMAE (0x00100000)
|
||||
#define SSI_IER_RIE (0x00200000)
|
||||
#define SSI_IER_RDMAE (0x00400000)
|
||||
|
||||
/* Bit definitions and macros for TCR */
|
||||
#define SSI_TCR_TEFS (0x00000001)
|
||||
#define SSI_TCR_TFSL (0x00000002)
|
||||
#define SSI_TCR_TFSI (0x00000004)
|
||||
#define SSI_TCR_TSCKP (0x00000008)
|
||||
#define SSI_TCR_TSHFD (0x00000010)
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||||
#define SSI_TCR_TXDIR (0x00000020)
|
||||
#define SSI_TCR_TFDIR (0x00000040)
|
||||
#define SSI_TCR_TFEN0 (0x00000080)
|
||||
#define SSI_TCR_TFEN1 (0x00000100)
|
||||
#define SSI_TCR_TXBIT0 (0x00000200)
|
||||
|
||||
/* Bit definitions and macros for RCR */
|
||||
#define SSI_RCR_REFS (0x00000001)
|
||||
#define SSI_RCR_RFSL (0x00000002)
|
||||
#define SSI_RCR_RFSI (0x00000004)
|
||||
#define SSI_RCR_RSCKP (0x00000008)
|
||||
#define SSI_RCR_RSHFD (0x00000010)
|
||||
#define SSI_RCR_RFEN0 (0x00000080)
|
||||
#define SSI_RCR_RFEN1 (0x00000100)
|
||||
#define SSI_RCR_RXBIT0 (0x00000200)
|
||||
#define SSI_RCR_RXEXT (0x00000400)
|
||||
|
||||
/* Bit definitions and macros for CCR */
|
||||
#define SSI_CCR_PM(x) (((x)&0x000000FF))
|
||||
#define SSI_CCR_DC(x) (((x)&0x0000001F)<<8)
|
||||
#define SSI_CCR_WL(x) (((x)&0x0000000F)<<13)
|
||||
#define SSI_CCR_PSR (0x00020000)
|
||||
#define SSI_CCR_DIV2 (0x00040000)
|
||||
|
||||
/* Bit definitions and macros for FCSR */
|
||||
#define SSI_FCSR_TFWM0(x) (((x)&0x0000000F))
|
||||
#define SSI_FCSR_RFWM0(x) (((x)&0x0000000F)<<4)
|
||||
#define SSI_FCSR_TFCNT0(x) (((x)&0x0000000F)<<8)
|
||||
#define SSI_FCSR_RFCNT0(x) (((x)&0x0000000F)<<12)
|
||||
#define SSI_FCSR_TFWM1(x) (((x)&0x0000000F)<<16)
|
||||
#define SSI_FCSR_RFWM1(x) (((x)&0x0000000F)<<20)
|
||||
#define SSI_FCSR_TFCNT1(x) (((x)&0x0000000F)<<24)
|
||||
#define SSI_FCSR_RFCNT1(x) (((x)&0x0000000F)<<28)
|
||||
|
||||
/* Bit definitions and macros for ACR */
|
||||
#define SSI_ACR_AC97EN (0x00000001)
|
||||
#define SSI_ACR_FV (0x00000002)
|
||||
#define SSI_ACR_TIF (0x00000004)
|
||||
#define SSI_ACR_RD (0x00000008)
|
||||
#define SSI_ACR_WR (0x00000010)
|
||||
#define SSI_ACR_FRDIV(x) (((x)&0x0000003F)<<5)
|
||||
|
||||
/* Bit definitions and macros for ACADD */
|
||||
#define SSI_ACADD_SSI_ACADD(x) (((x)&0x0007FFFF))
|
||||
|
||||
/* Bit definitions and macros for ACDAT */
|
||||
#define SSI_ACDAT_SSI_ACDAT(x) (((x)&0x0007FFFF))
|
||||
|
||||
/* Bit definitions and macros for ATAG */
|
||||
#define SSI_ATAG_DDI_ATAG(x) (((x)&0x0000FFFF))
|
||||
|
||||
/*********************************************************************
|
||||
* Phase Locked Loop (PLL)
|
||||
*********************************************************************/
|
||||
|
|
@ -1533,8 +1234,7 @@
|
|||
#define PCI_ICR_REE (0x04000000) /* Retry error enable */
|
||||
#define PCI_ICR_IAE (0x02000000) /* Initiator abort enable */
|
||||
#define PCI_ICR_TAE (0x01000000) /* Target abort enable */
|
||||
|
||||
#define PCI_IDR_DEVID (
|
||||
#define PCI_ICR_MAXRETRY(x) ((x) & 0x000000FF)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue