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x86: Refactor PCI to permit alternate init

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We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use early malloc() to store information about a PCI hose.

Common PCI code moves to arch/x86/cpu/pci.c and a new
board_pci_setup_hose() function is provided by boards to set up the (single)
hose used by that board.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2014-11-12 22:42:11 -07:00
parent 70a09c6c3d
commit d188b18f65
4 changed files with 46 additions and 15 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
arch/x86/cpu/Makefile
View file

@ -11,3 +11,4 @@
extra-y = start.o extra-y = start.o
obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o
obj-y += interrupts.o cpu.o call64.o obj-y += interrupts.o cpu.o call64.o
obj-$(CONFIG_PCI) += pci.o

20
arch/x86/cpu/coreboot/pci.c
View file

@ -13,8 +13,6 @@
#include <pci.h> #include <pci.h>
#include <asm/pci.h> #include <asm/pci.h>
static struct pci_controller coreboot_hose;
static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
struct pci_config_table *table) struct pci_config_table *table)
{ {
@ -31,19 +29,13 @@ static struct pci_config_table pci_coreboot_config_table[] = {
{} {}
}; };
void pci_init_board(void) void board_pci_setup_hose(struct pci_controller *hose)
{ {
coreboot_hose.config_table = pci_coreboot_config_table; hose->config_table = pci_coreboot_config_table;
coreboot_hose.first_busno = 0; hose->first_busno = 0;
coreboot_hose.last_busno = 0; hose->last_busno = 0;
pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff, pci_set_region(hose->regions + 0, 0x0, 0x0, 0xffffffff,
PCI_REGION_MEM); PCI_REGION_MEM);
coreboot_hose.region_count = 1; hose->region_count = 1;
pci_setup_type1(&coreboot_hose);
pci_register_hose(&coreboot_hose);
pci_hose_scan(&coreboot_hose);
} }

27
arch/x86/cpu/pci.c Normal file
View file

@ -0,0 +1,27 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* (C) Copyright 2008,2009
* Graeme Russ, <graeme.russ@gmail.com>
*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <pci.h>
#include <asm/pci.h>
static struct pci_controller x86_hose;
void pci_init_board(void)
{
struct pci_controller *hose = &x86_hose;
board_pci_setup_hose(hose);
pci_setup_type1(hose);
pci_register_hose(hose);
hose->last_busno = pci_hose_scan(hose);
}

11
arch/x86/include/asm/pci.h
View file

@ -12,5 +12,16 @@
#define DEFINE_PCI_DEVICE_TABLE(_table) \ #define DEFINE_PCI_DEVICE_TABLE(_table) \
const struct pci_device_id _table[] const struct pci_device_id _table[]
struct pci_controller;
void pci_setup_type1(struct pci_controller *hose); void pci_setup_type1(struct pci_controller *hose);
/**
* board_pci_setup_hose() - Set up the PCI hose
*
* This is called by the common x86 PCI code to set up the PCI controller
* hose. It may be called when no memory/BSS is available so should just
* store things in 'hose' and not in BSS variables.
*/
void board_pci_setup_hose(struct pci_controller *hose);
#endif #endif