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ppc4xx: Consolidate PPC4xx UIC defines

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This 2nd patch now removes all UIC mask bit definition. They should be
generated from the vectors by using the UIC_MASK() macro from now on.
This way only the vectors need to get defined for new PPC's.

Also only the really used interrupt vectors are now defined. This makes
definitions for new PPC versions easier and less error prone.

Another part of this patch is that the 4xx emac driver got a little
cleanup, since now the usage of the interrupts is clearer.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2008-06-26 13:40:57 +02:00
parent 4fb25a3db3
commit d1631fe1a0
9 changed files with 406 additions and 1709 deletions
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2
board/amcc/sequoia/sequoia.c
View file

@ -334,7 +334,7 @@ int checkboard(void)
*/ */
void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev) void sequoia_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{ {
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIR2); pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
} }
#endif #endif

5
common/cmd_reginfo.c
View file

@ -93,11 +93,10 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
#elif defined (CONFIG_405GP) #elif defined (CONFIG_405GP)
printf ("\n405GP registers; MSR=%08x\n",mfmsr()); printf ("\n405GP registers; MSR=%08x\n",mfmsr());
printf ("\nUniversal Interrupt Controller Regs\n" printf ("\nUniversal Interrupt Controller Regs\n"
"uicsr uicsrs uicer uiccr uicpr uictr uicmsr uicvr uicvcr" "uicsr uicer uiccr uicpr uictr uicmsr uicvr uicvcr"
"\n" "\n"
"%08x %08x %08x %08x %08x %08x %08x %08x %08x\n", "%08x %08x %08x %08x %08x %08x %08x %08x\n",
mfdcr(uicsr), mfdcr(uicsr),
mfdcr(uicsrs),
mfdcr(uicer), mfdcr(uicer),
mfdcr(uiccr), mfdcr(uiccr),
mfdcr(uicpr), mfdcr(uicpr),

414
cpu/ppc4xx/4xx_enet.c
View file

@ -121,11 +121,62 @@
* Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
* Interrupt Controller). * Interrupt Controller).
*-----------------------------------------------------------------------------*/ *-----------------------------------------------------------------------------*/
#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE) #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
#define EMAC_UIC_DEF UIC_ENET #if defined(CONFIG_HAS_ETH3)
#define EMAC_UIC_DEF1 UIC_ENET1 #if !defined(CONFIG_440GX)
#define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET ) #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
#else
/* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
#define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
#endif /* !defined(CONFIG_440GX) */
#elif defined(CONFIG_HAS_ETH2)
#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
UIC_MASK(ETH_IRQ_NUM(2)))
#elif defined(CONFIG_HAS_ETH1)
#define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
#else
#define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0))
#endif
/*
* Define a default version for UIC_ETHxB for non 440GX so that we can
* use common code for all 4xx variants
*/
#if !defined(UIC_ETHxB)
#define UIC_ETHxB 0
#endif
#define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR)
#define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE)
#define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE)
#define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB)
#define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB)
#define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
/*
* We have 3 different interrupt types:
* - MAL interrupts indicating successful transfer
* - MAL error interrupts indicating MAL related errors
* - EMAC interrupts indicating EMAC related errors
*
* All those interrupts can be on different UIC's, but since
* now at least all interrupts from one type are on the same
* UIC. Only exception is 440GX where the EMAC interrupts are
* spread over two UIC's!
*/
#define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
#define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
#define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
#if defined(CONFIG_440GX)
#define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(2)) * 0x10))
#else
#define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
#endif
#undef INFO_4XX_ENET #undef INFO_4XX_ENET
@ -165,9 +216,6 @@
/*-----------------------------------------------------------------------------+ /*-----------------------------------------------------------------------------+
* Global variables. TX and RX descriptors and buffers. * Global variables. TX and RX descriptors and buffers.
*-----------------------------------------------------------------------------*/ *-----------------------------------------------------------------------------*/
/* IER globals */
static uint32_t mal_ier;
#if !defined(CONFIG_NET_MULTI) #if !defined(CONFIG_NET_MULTI)
struct eth_device *emac0_dev = NULL; struct eth_device *emac0_dev = NULL;
#endif #endif
@ -199,12 +247,6 @@ struct eth_device *emac0_dev = NULL;
#define CONFIG_EMAC_NR_START 0 #define CONFIG_EMAC_NR_START 0
#endif #endif
#if defined(CONFIG_405EX) || defined(CONFIG_440EPX)
#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev)))
#else
#define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2))
#endif
#define MAL_RX_DESC_SIZE 2048 #define MAL_RX_DESC_SIZE 2048
#define MAL_TX_DESC_SIZE 2048 #define MAL_TX_DESC_SIZE 2048
#define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE) #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
@ -1434,59 +1476,17 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
} }
} }
#if defined (CONFIG_440) || defined(CONFIG_405EX)
#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
/*
* Hack: On 440SP all enet irq sources are located on UIC1
* Needs some cleanup. --sr
*/
#define UIC0MSR uic1msr
#define UIC0SR uic1sr
#define UIC1MSR uic1msr
#define UIC1SR uic1sr
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
/*
* Hack: On 460EX/GT all enet irq sources are located on UIC2
* Needs some cleanup. --ag
*/
#define UIC0MSR uic2msr
#define UIC0SR uic2sr
#define UIC1MSR uic2msr
#define UIC1SR uic2sr
#else
#define UIC0MSR uic0msr
#define UIC0SR uic0sr
#define UIC1MSR uic1msr
#define UIC1SR uic1sr
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define UICMSR_ETHX uic0msr
#define UICSR_ETHX uic0sr
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define UICMSR_ETHX uic2msr
#define UICSR_ETHX uic2sr
#else
#define UICMSR_ETHX uic1msr
#define UICSR_ETHX uic1sr
#endif
int enetInt (struct eth_device *dev) int enetInt (struct eth_device *dev)
{ {
int serviced; int serviced;
int rc = -1; /* default to not us */ int rc = -1; /* default to not us */
unsigned long mal_isr; u32 mal_isr;
unsigned long emac_isr = 0; u32 emac_isr = 0;
unsigned long mal_rx_eob; u32 mal_eob;
unsigned long my_uic0msr, my_uic1msr; u32 uic_mal;
unsigned long my_uicmsr_ethx; u32 uic_mal_err;
u32 uic_emac;
#if defined(CONFIG_440GX) u32 uic_emac_b;
unsigned long my_uic2msr;
#endif
EMAC_4XX_HW_PST hw_p; EMAC_4XX_HW_PST hw_p;
/* /*
@ -1505,256 +1505,79 @@ int enetInt (struct eth_device *dev)
do { do {
serviced = 0; serviced = 0;
my_uic0msr = mfdcr (UIC0MSR); uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
my_uic1msr = mfdcr (UIC1MSR); uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
#if defined(CONFIG_440GX) uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
my_uic2msr = mfdcr (uic2msr); uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);
#endif
my_uicmsr_ethx = mfdcr (UICMSR_ETHX);
if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
&& !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
&& !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) { && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
/* not for us */ /* not for us */
return (rc); return (rc);
} }
#if defined (CONFIG_440GX)
if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
&& !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
/* not for us */
return (rc);
}
#endif
/* get and clear controller status interrupts */ /* get and clear controller status interrupts */
/* look at Mal and EMAC interrupts */ /* look at MAL and EMAC error interrupts */
if ((my_uic0msr & (UIC_MRE | UIC_MTE)) if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) { /* we have a MAL error interrupt */
/* we have a MAL interrupt */ mal_isr = mfdcr(malesr);
mal_isr = mfdcr (malesr); mal_err(dev, mal_isr, uic_mal_err,
/* look for mal error */ MAL_UIC_DEF, MAL_UIC_ERR);
if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR); /* clear MAL error interrupt status bits */
serviced = 1; mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
rc = 0; UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);
}
return -1;
} }
/* port by port dispatch of emac interrupts */ /* look for EMAC errors */
if (hw_p->devnum == 0) { if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */ emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); emac_err(dev, emac_isr);
if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr);
serviced = 1;
rc = 0;
}
}
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */
return (rc); /* we had errors so get out */
}
}
#if !defined(CONFIG_440SP) /* clear EMAC error interrupt status bits */
if (hw_p->devnum == 1) { mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */ mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);
emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr);
serviced = 1;
rc = 0;
}
}
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */
return (rc); /* we had errors so get out */
}
}
#if defined (CONFIG_440GX)
if (hw_p->devnum == 2) {
if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr);
serviced = 1;
rc = 0;
}
}
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
mtdcr (uic2sr, UIC_ETH2);
return (rc); /* we had errors so get out */
}
}
if (hw_p->devnum == 3) { return -1;
if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr);
serviced = 1;
rc = 0;
}
}
if ((hw_p->emac_ier & emac_isr)
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
mtdcr (uic2sr, UIC_ETH3);
return (rc); /* we had errors so get out */
}
} }
#endif /* CONFIG_440GX */
#endif /* !CONFIG_440SP */
/* handle MAX TX EOB interrupt from a tx */ /* handle MAX TX EOB interrupt from a tx */
if (my_uic0msr & UIC_MTE) { if (uic_mal & UIC_MAL_TXEOB) {
mal_rx_eob = mfdcr (maltxeobisr); /* clear MAL interrupt status bits */
mtdcr (maltxeobisr, mal_rx_eob); mal_eob = mfdcr(maltxeobisr);
mtdcr (UIC0SR, UIC_MTE); mtdcr(maltxeobisr, mal_eob);
mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);
/* indicate that we serviced an interrupt */
serviced = 1;
rc = 0;
} }
/* handle MAL RX EOB interupt from a receive */
/* check for EOB on valid channels */ /* handle MAL RX EOB interupt from a receive */
if (my_uic0msr & UIC_MRE) { /* check for EOB on valid channels */
mal_rx_eob = mfdcr (malrxeobisr); if (uic_mal & UIC_MAL_RXEOB) {
if ((mal_rx_eob & mal_eob = mfdcr(malrxeobisr);
(0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) if (mal_eob &
!= 0) { /* call emac routine for channel x */ (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
/* clear EOB /* push packet to upper layer */
mtdcr(malrxeobisr, mal_rx_eob); */ enet_rcv(dev, emac_isr);
enet_rcv (dev, emac_isr);
/* clear MAL interrupt status bits */
mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);
/* indicate that we serviced an interrupt */ /* indicate that we serviced an interrupt */
serviced = 1; serviced = 1;
rc = 0; rc = 0;
} }
} }
mtdcr (UIC0SR, UIC_MRE); /* Clear */
mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
switch (hw_p->devnum) {
case 0:
mtdcr (UICSR_ETHX, UIC_ETH0);
break;
case 1:
mtdcr (UICSR_ETHX, UIC_ETH1);
break;
#if defined (CONFIG_440GX)
case 2:
mtdcr (uic2sr, UIC_ETH2);
break;
case 3:
mtdcr (uic2sr, UIC_ETH3);
break;
#endif /* CONFIG_440GX */
default:
break;
}
} while (serviced); } while (serviced);
return (rc); return (rc);
} }
#else /* CONFIG_440 */
int enetInt (struct eth_device *dev)
{
int serviced;
int rc = -1; /* default to not us */
unsigned long mal_isr;
unsigned long emac_isr = 0;
unsigned long mal_rx_eob;
unsigned long my_uicmsr;
EMAC_4XX_HW_PST hw_p;
/*
* Because the mal is generic, we need to get the current
* eth device
*/
#if defined(CONFIG_NET_MULTI)
dev = eth_get_dev();
#else
dev = emac0_dev;
#endif
hw_p = dev->priv;
/* enter loop that stays in interrupt code until nothing to service */
do {
serviced = 0;
my_uicmsr = mfdcr (uicmsr);
if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
return (rc);
}
/* get and clear controller status interrupts */
/* look at Mal and EMAC interrupts */
if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
mal_isr = mfdcr (malesr);
/* look for mal error */
if ((my_uicmsr & MAL_UIC_ERR) != 0) {
mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
serviced = 1;
rc = 0;
}
}
/* port by port dispatch of emac interrupts */
if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
if ((hw_p->emac_ier & emac_isr) != 0) {
emac_err (dev, emac_isr);
serviced = 1;
rc = 0;
}
}
if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
return (rc); /* we had errors so get out */
}
/* handle MAX TX EOB interrupt from a tx */
if (my_uicmsr & UIC_MAL_TXEOB) {
mal_rx_eob = mfdcr (maltxeobisr);
mtdcr (maltxeobisr, mal_rx_eob);
mtdcr (uicsr, UIC_MAL_TXEOB);
}
/* handle MAL RX EOB interupt from a receive */
/* check for EOB on valid channels */
if (my_uicmsr & UIC_MAL_RXEOB)
{
mal_rx_eob = mfdcr (malrxeobisr);
if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
/* clear EOB
mtdcr(malrxeobisr, mal_rx_eob); */
enet_rcv (dev, emac_isr);
/* indicate that we serviced an interrupt */
serviced = 1;
rc = 0;
}
}
mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
#if defined(CONFIG_405EZ)
mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
#endif /* defined(CONFIG_405EZ) */
}
while (serviced);
return (rc);
}
#endif /* CONFIG_440 */
/*-----------------------------------------------------------------------------+ /*-----------------------------------------------------------------------------+
* MAL Error Routine * MAL Error Routine
*-----------------------------------------------------------------------------*/ *-----------------------------------------------------------------------------*/
@ -1940,6 +1763,7 @@ int ppc_4xx_eth_initialize (bd_t * bis)
EMAC_4XX_HW_PST hw = NULL; EMAC_4XX_HW_PST hw = NULL;
u8 ethaddr[4 + CONFIG_EMAC_NR_START][6]; u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
u32 hw_addr[4]; u32 hw_addr[4];
u32 mal_ier;
#if defined(CONFIG_440GX) #if defined(CONFIG_440GX)
unsigned long pfc1; unsigned long pfc1;
@ -2077,19 +1901,19 @@ int ppc_4xx_eth_initialize (bd_t * bis)
mtdcr (malier, mal_ier); mtdcr (malier, mal_ier);
/* install MAL interrupt handler */ /* install MAL interrupt handler */
irq_install_handler (VECNUM_MS, irq_install_handler (VECNUM_MAL_SERR,
(interrupt_handler_t *) enetInt, (interrupt_handler_t *) enetInt,
dev); dev);
irq_install_handler (VECNUM_MTE, irq_install_handler (VECNUM_MAL_TXEOB,
(interrupt_handler_t *) enetInt, (interrupt_handler_t *) enetInt,
dev); dev);
irq_install_handler (VECNUM_MRE, irq_install_handler (VECNUM_MAL_RXEOB,
(interrupt_handler_t *) enetInt, (interrupt_handler_t *) enetInt,
dev); dev);
irq_install_handler (VECNUM_TXDE, irq_install_handler (VECNUM_MAL_TXDE,
(interrupt_handler_t *) enetInt, (interrupt_handler_t *) enetInt,
dev); dev);
irq_install_handler (VECNUM_RXDE, irq_install_handler (VECNUM_MAL_RXDE,
(interrupt_handler_t *) enetInt, (interrupt_handler_t *) enetInt,
dev); dev);
virgin = 1; virgin = 1;

75
cpu/ppc4xx/interrupts.c
View file

@ -35,24 +35,26 @@
#include <ppc_asm.tmpl> #include <ppc_asm.tmpl>
#include <commproc.h> #include <commproc.h>
DECLARE_GLOBAL_DATA_PTR; #if (UIC_MAX > 3)
#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
/* UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI) | \
* Define the number of UIC's UIC_MASK(VECNUM_UIC3CI) | UIC_MASK(VECNUM_UIC3NCI))
*/ #elif (UIC_MAX > 2)
#if defined(CONFIG_440SPE) || \ #if defined(CONFIG_440GX)
defined(CONFIG_460EX) || defined(CONFIG_460GT) #define UICB0_ALL (UIC_MASK(VECNUM_UIC0CI) | UIC_MASK(VECNUM_UIC0NCI) | \
#define UIC_MAX 4 UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
#elif defined(CONFIG_440GX) || \ UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define UIC_MAX 3
#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define UIC_MAX 2
#else #else
#define UIC_MAX 1 #define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI) | \
UIC_MASK(VECNUM_UIC2CI) | UIC_MASK(VECNUM_UIC2NCI))
#endif #endif
#elif (UIC_MAX > 1)
#define UICB0_ALL (UIC_MASK(VECNUM_UIC1CI) | UIC_MASK(VECNUM_UIC1NCI))
#else
#define UICB0_ALL 0
#endif
DECLARE_GLOBAL_DATA_PTR;
/* /*
* CPM interrupt vector functions. * CPM interrupt vector functions.
@ -158,18 +160,23 @@ int interrupt_init_cpu (unsigned *decrementer_count)
#if !defined(CONFIG_440GX) #if !defined(CONFIG_440GX)
#if (UIC_MAX > 1) #if (UIC_MAX > 1)
/* Install the UIC1 handlers */ /* Install the UIC1 handlers */
irq_install_handler(VECNUM_UIC1NC, uic_cascade_interrupt, 0); irq_install_handler(VECNUM_UIC1NCI, uic_cascade_interrupt, 0);
irq_install_handler(VECNUM_UIC1C, uic_cascade_interrupt, 0); irq_install_handler(VECNUM_UIC1CI, uic_cascade_interrupt, 0);
#endif #endif
#if (UIC_MAX > 2) #if (UIC_MAX > 2)
irq_install_handler(VECNUM_UIC2NC, uic_cascade_interrupt, 0); irq_install_handler(VECNUM_UIC2NCI, uic_cascade_interrupt, 0);
irq_install_handler(VECNUM_UIC2C, uic_cascade_interrupt, 0); irq_install_handler(VECNUM_UIC2CI, uic_cascade_interrupt, 0);
#endif #endif
#if (UIC_MAX > 3) #if (UIC_MAX > 3)
irq_install_handler(VECNUM_UIC3NC, uic_cascade_interrupt, 0); irq_install_handler(VECNUM_UIC3NCI, uic_cascade_interrupt, 0);
irq_install_handler(VECNUM_UIC3C, uic_cascade_interrupt, 0); irq_install_handler(VECNUM_UIC3CI, uic_cascade_interrupt, 0);
#endif #endif
#else /* !defined(CONFIG_440GX) */ #else /* !defined(CONFIG_440GX) */
/*
* ToDo: Remove this 440GX special handling:
* Move SDR0_MFR setup to cpu.c and use common code with UICB0
* on 440GX. 2008-06-26, sr
*/
/* Take the GX out of compatibility mode /* Take the GX out of compatibility mode
* Travis Sawyer, 9 Mar 2004 * Travis Sawyer, 9 Mar 2004
* NOTE: 440gx user manual inconsistency here * NOTE: 440gx user manual inconsistency here
@ -182,7 +189,7 @@ int interrupt_init_cpu (unsigned *decrementer_count)
/* Enable UIC interrupts via UIC Base Enable Register */ /* Enable UIC interrupts via UIC Base Enable Register */
mtdcr(uicb0sr, UICB0_ALL); mtdcr(uicb0sr, UICB0_ALL);
mtdcr(uicb0er, 0x54000000); mtdcr(uicb0er, UICB0_ALL);
/* None are critical */ /* None are critical */
mtdcr(uicb0cr, 0); mtdcr(uicb0cr, 0);
#endif /* !defined(CONFIG_440GX) */ #endif /* !defined(CONFIG_440GX) */
@ -216,8 +223,7 @@ static void uic_interrupt(u32 uic_base, int vec_base)
(*irq_vecs[vec].handler)(irq_vecs[vec].arg); (*irq_vecs[vec].handler)(irq_vecs[vec].arg);
} else { } else {
set_dcr(uic_base + UIC_ER, set_dcr(uic_base + UIC_ER,
get_dcr(uic_base + UIC_ER) & get_dcr(uic_base + UIC_ER) & ~UIC_MASK(vec));
~(0x80000000 >> (vec & 0x1f)));
printf("Masking bogus interrupt vector %d" printf("Masking bogus interrupt vector %d"
" (UIC_BASE=0x%x)\n", vec, uic_base); " (UIC_BASE=0x%x)\n", vec, uic_base);
} }
@ -226,7 +232,7 @@ static void uic_interrupt(u32 uic_base, int vec_base)
* After servicing the interrupt, we have to remove the * After servicing the interrupt, we have to remove the
* status indicator * status indicator
*/ */
set_dcr(uic_base + UIC_SR, (0x80000000 >> (vec & 0x1f))); set_dcr(uic_base + UIC_SR, UIC_MASK(vec));
} }
/* /*
@ -244,7 +250,6 @@ static void uic_cascade_interrupt(void *para)
} }
#endif #endif
#if defined(CONFIG_440)
#if defined(CONFIG_440GX) #if defined(CONFIG_440GX)
/* 440GX uses base uic register */ /* 440GX uses base uic register */
#define UIC_BMSR uicb0msr #define UIC_BMSR uicb0msr
@ -253,10 +258,6 @@ static void uic_cascade_interrupt(void *para)
#define UIC_BMSR uic0msr #define UIC_BMSR uic0msr
#define UIC_BSR uic0sr #define UIC_BSR uic0sr
#endif #endif
#else /* CONFIG_440 */
#define UIC_BMSR uicmsr
#define UIC_BSR uicsr
#endif /* CONFIG_440 */
/* /*
* Handle external interrupts * Handle external interrupts
@ -271,17 +272,20 @@ void external_interrupt(struct pt_regs *regs)
uic_msr = mfdcr(UIC_BMSR); uic_msr = mfdcr(UIC_BMSR);
#if (UIC_MAX > 1) #if (UIC_MAX > 1)
if ((UICB0_UIC1CI & uic_msr) || (UICB0_UIC1NCI & uic_msr)) if ((UIC_MASK(VECNUM_UIC1CI) & uic_msr) ||
(UIC_MASK(VECNUM_UIC1NCI) & uic_msr))
uic_interrupt(UIC1_DCR_BASE, 32); uic_interrupt(UIC1_DCR_BASE, 32);
#endif #endif
#if (UIC_MAX > 2) #if (UIC_MAX > 2)
if ((UICB0_UIC2CI & uic_msr) || (UICB0_UIC2NCI & uic_msr)) if ((UIC_MASK(VECNUM_UIC2CI) & uic_msr) ||
(UIC_MASK(VECNUM_UIC2NCI) & uic_msr))
uic_interrupt(UIC2_DCR_BASE, 64); uic_interrupt(UIC2_DCR_BASE, 64);
#endif #endif
#if (UIC_MAX > 3) #if (UIC_MAX > 3)
if ((UICB0_UIC3CI & uic_msr) || (UICB0_UIC3NCI & uic_msr)) if ((UIC_MASK(VECNUM_UIC3CI) & uic_msr) ||
(UIC_MASK(VECNUM_UIC3NCI) & uic_msr))
uic_interrupt(UIC3_DCR_BASE, 96); uic_interrupt(UIC3_DCR_BASE, 96);
#endif #endif
@ -290,7 +294,8 @@ void external_interrupt(struct pt_regs *regs)
if (uic_msr & ~(UICB0_ALL)) if (uic_msr & ~(UICB0_ALL))
uic_interrupt(UIC0_DCR_BASE, 0); uic_interrupt(UIC0_DCR_BASE, 0);
#else #else
if ((UICB0_UIC0CI & uic_msr) || (UICB0_UIC0NCI & uic_msr)) if ((UIC_MASK(VECNUM_UIC0CI) & uic_msr) ||
(UIC_MASK(VECNUM_UIC0NCI) & uic_msr))
uic_interrupt(UIC0_DCR_BASE, 0); uic_interrupt(UIC0_DCR_BASE, 0);
#endif #endif
#else /* CONFIG_440 */ #else /* CONFIG_440 */

2
cpu/ppc4xx/usbdev.c
View file

@ -197,7 +197,7 @@ void usb_dev_init()
/*enable interrupts */ /*enable interrupts */
*(unsigned char *)USB2D0_INTRUSBE_8 = 0x0f; *(unsigned char *)USB2D0_INTRUSBE_8 = 0x0f;
irq_install_handler(VECNUM_HSB2D, (interrupt_handler_t *) usbInt, irq_install_handler(VECNUM_USBDEV, (interrupt_handler_t *) usbInt,
NULL); NULL);
} }
#else #else

660
include/asm-ppc/ppc4xx-uic.h
View file

@ -26,444 +26,268 @@
#ifndef _PPC4xx_UIC_H_ #ifndef _PPC4xx_UIC_H_
#define _PPC4xx_UIC_H_ #define _PPC4xx_UIC_H_
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /*
* Define the number of UIC's
*/
#if defined(CONFIG_440SPE) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define UIC_MAX 4
#elif defined(CONFIG_440GX) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_405EX)
#define UIC_MAX 3
#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define UIC_MAX 2
#else
#define UIC_MAX 1
#endif
/* UIC 0 */ /*
#define VECNUM_U0 0 /* UART 0 */ * UIC register
#define VECNUM_U1 1 /* UART 1 */ */
#define VECNUM_IIC0 2 /* IIC */ #define UIC_SR 0x0 /* UIC status */
#define VECNUM_KRD 3 /* Kasumi Ready for data */ #define UIC_ER 0x2 /* UIC enable */
#define VECNUM_KDA 4 /* Kasumi Data Available */ #define UIC_CR 0x3 /* UIC critical */
#define VECNUM_PCRW 5 /* PCI command register write */ #define UIC_PR 0x4 /* UIC polarity */
#define VECNUM_PPM 6 /* PCI power management */ #define UIC_TR 0x5 /* UIC triggering */
#define VECNUM_IIC1 7 /* IIC */ #define UIC_MSR 0x6 /* UIC masked status */
#define VECNUM_SPI 8 /* SPI */ #define UIC_VR 0x7 /* UIC vector */
#define VECNUM_EPCISER 9 /* External PCI SERR */ #define UIC_VCR 0x8 /* UIC vector configuration */
#define VECNUM_MTE 10 /* MAL TXEOB */
#define VECNUM_MRE 11 /* MAL RXEOB */
#define VECNUM_D0 12 /* DMA channel 0 */
#define VECNUM_D1 13 /* DMA channel 1 */
#define VECNUM_D2 14 /* DMA channel 2 */
#define VECNUM_D3 15 /* DMA channel 3 */
#define VECNUM_UD0 16 /* UDMA irq 0 */
#define VECNUM_UD1 17 /* UDMA irq 1 */
#define VECNUM_UD2 18 /* UDMA irq 2 */
#define VECNUM_UD3 19 /* UDMA irq 3 */
#define VECNUM_HSB2D 20 /* USB2.0 Device */
#define VECNUM_USBDEV 20 /* USB 1.1/USB 2.0 Device */
#define VECNUM_OHCI1 21 /* USB2.0 Host OHCI irq 1 */
#define VECNUM_OHCI2 22 /* USB2.0 Host OHCI irq 2 */
#define VECNUM_EIP94 23 /* Security EIP94 */
#define VECNUM_ETH0 24 /* Emac 0 */
#define VECNUM_ETH1 25 /* Emac 1 */
#define VECNUM_EHCI 26 /* USB2.0 Host EHCI */
#define VECNUM_EIR4 27 /* External interrupt 4 */
#define VECNUM_UIC2NC 28 /* UIC2 non-critical interrupt */
#define VECNUM_UIC2C 29 /* UIC2 critical interrupt */
#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
/* UIC 1 */ #define UIC0_DCR_BASE 0xc0
#define VECNUM_MS (32 + 0) /* MAL SERR */ #define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
#define VECNUM_MTDE (32 + 1) /* MAL TXDE */ #define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
#define VECNUM_MRDE (32 + 2) /* MAL RXDE */ #define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
#define VECNUM_U2 (32 + 3) /* UART 2 */ #define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
#define VECNUM_U3 (32 + 4) /* UART 3 */ #define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
#define VECNUM_EBCO (32 + 5) /* EBCO interrupt status */ #define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
#define VECNUM_NDFC (32 + 6) /* NDFC */ #define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
#define VECNUM_KSLE (32 + 7) /* KASUMI slave error */ #define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
#define VECNUM_CT5 (32 + 8) /* GPT compare timer 5 */
#define VECNUM_CT6 (32 + 9) /* GPT compare timer 6 */
#define VECNUM_PLB34I0 (32 + 10) /* PLB3X4X MIRQ0 */
#define VECNUM_PLB34I1 (32 + 11) /* PLB3X4X MIRQ1 */
#define VECNUM_PLB34I2 (32 + 12) /* PLB3X4X MIRQ2 */
#define VECNUM_PLB34I3 (32 + 13) /* PLB3X4X MIRQ3 */
#define VECNUM_PLB34I4 (32 + 14) /* PLB3X4X MIRQ4 */
#define VECNUM_PLB34I5 (32 + 15) /* PLB3X4X MIRQ5 */
#define VECNUM_CT0 (32 + 16) /* GPT compare timer 0 */
#define VECNUM_CT1 (32 + 17) /* GPT compare timer 1 */
#define VECNUM_EIR7 (32 + 18) /* External interrupt 7 */
#define VECNUM_EIR8 (32 + 19) /* External interrupt 8 */
#define VECNUM_EIR9 (32 + 20) /* External interrupt 9 */
#define VECNUM_CT2 (32 + 21) /* GPT compare timer 2 */
#define VECNUM_CT3 (32 + 22) /* GPT compare timer 3 */
#define VECNUM_CT4 (32 + 23) /* GPT compare timer 4 */
#define VECNUM_SRE (32 + 24) /* Serial ROM error */
#define VECNUM_GPTDC (32 + 25) /* GPT decrementer pulse */
#define VECNUM_RSVD0 (32 + 26) /* Reserved */
#define VECNUM_EPCIPER (32 + 27) /* External PCI PERR */
#define VECNUM_EIR0 (32 + 28) /* External interrupt 0 */
#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */
#define VECNUM_EIR1 (32 + 30) /* External interrupt 1 */
#define VECNUM_EWU1 (32 + 31) /* Ethernet 1 wakeup */
#define VECNUM_TXDE VECNUM_MTDE #define UIC1_DCR_BASE 0xd0
#define VECNUM_RXDE VECNUM_MRDE #define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
/* UIC 2 */ #if defined(CONFIG_440GX)
#define VECNUM_EIR5 (64 + 0) /* External interrupt 5 */ #define UIC2_DCR_BASE 0x210
#define VECNUM_EIR6 (64 + 1) /* External interrupt 6 */ #else
#define VECNUM_OPB (64 + 2) /* OPB to PLB bridge int stat */ #define UIC2_DCR_BASE 0xe0
#define VECNUM_EIR2 (64 + 3) /* External interrupt 2 */ #endif
#define VECNUM_EIR3 (64 + 4) /* External interrupt 3 */ #define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
#define VECNUM_DDR2 (64 + 5) /* DDR2 sdram */ #define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
#define VECNUM_MCTX0 (64 + 6) /* MAl intp coalescence TX0 */ #define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
#define VECNUM_MCTX1 (64 + 7) /* MAl intp coalescence TX1 */ #define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
#define VECNUM_MCTR0 (64 + 8) /* MAl intp coalescence TR0 */ #define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
#define VECNUM_MCTR1 (64 + 9) /* MAl intp coalescence TR1 */ #define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) #define UIC3_DCR_BASE 0xf0
#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
/* UIC 0 */ #if defined(CONFIG_440GX)
#define VECNUM_U1 1 /* UART1 */ #define UIC_DCR_BASE 0x200
#define VECNUM_IIC0 2 /* IIC0 */ #define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */
#define VECNUM_IIC1 3 /* IIC1 */ #define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */
#define VECNUM_PIM 4 /* PCI inbound message */ #define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */
#define VECNUM_PCRW 5 /* PCI command reg write */ #define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */
#define VECNUM_PPM 6 /* PCI power management */ #define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */
#define VECNUM_MSI0 8 /* PCI MSI level 0 */ #define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */
#define VECNUM_EIR0 9 /* External interrupt 0 */ #define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */
#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */ #define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration*/
#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */ #endif /* CONFIG_440GX */
#define VECNUM_D0 12 /* DMA channel 0 */
#define VECNUM_D1 13 /* DMA channel 1 */
#define VECNUM_D2 14 /* DMA channel 2 */
#define VECNUM_D3 15 /* DMA channel 3 */
#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */
#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */
#define VECNUM_EIR1 9 /* External interrupt 1 */
#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
/* UIC 1 */ /* The following is for compatibility with 405 code */
#define VECNUM_EIR2 (32 + 0) /* External interrupt 0 */ #define uicsr uic0sr
#define VECNUM_U0 (32 + 1) /* UART0 */ #define uicer uic0er
#define VECNUM_EIR3 (32 + 20) /* External interrupt 3 */ #define uiccr uic0cr
#define VECNUM_EIR4 (32 + 21) /* External interrupt 4 */ #define uicpr uic0pr
#define VECNUM_EIR5 (32 + 26) /* External interrupt 5 */ #define uictr uic0tr
#define VECNUM_EIR6 (32 + 27) /* External interrupt 6 */ #define uicmsr uic0msr
#define VECNUM_U2 (32 + 28) /* UART2 */ #define uicvr uic0vr
#define VECNUM_U3 (32 + 29) /* UART3 */ #define uicvcr uic0vcr
#define VECNUM_EIR7 (32 + 30) /* External interrupt 7 */
#define VECNUM_EIR8 (32 + 31) /* External interrupt 8 */
/* UIC 2 */ /*
#define VECNUM_EIR9 (64 + 2) /* External interrupt 9 */ * Now the interrupt vector definitions. They are different for most of
#define VECNUM_MS (64 + 3) /* MAL SERR */ * the 4xx variants, so we need some more #ifdef's here. No mask
#define VECNUM_TXDE (64 + 4) /* MAL TXDE */ * definitions anymore here. For this please use the UIC_MASK macro below.
#define VECNUM_RXDE (64 + 5) /* MAL RXDE */ *
#define VECNUM_MTE (64 + 6) /* MAL TXEOB */ * Note: Please only define the interrupts really used in U-Boot here.
#define VECNUM_MRE (64 + 7) /* MAL RXEOB */ * Those are the cascading and EMAC/MAL related interrupt.
#define VECNUM_ETH0 (64 + 16) /* Ethernet 0 */ */
#define VECNUM_ETH1 (64 + 17) /* Ethernet 1 */
#define VECNUM_ETH2 (64 + 18) /* Ethernet 2 */
#define VECNUM_ETH3 (64 + 19) /* Ethernet 3 */
#define VECNUM_EWU0 (64 + 20) /* Emac 0 wakeup */
#define VECNUM_EWU1 (64 + 21) /* Emac 1 wakeup */
#define VECNUM_EWU2 (64 + 22) /* Emac 2 wakeup */
#define VECNUM_EWU3 (64 + 23) /* Emac 3 wakeup */
#define VECNUM_EIR10 (64 + 24) /* External interrupt 10 */
#define VECNUM_EIR11 (64 + 25) /* External interrupt 11 */
/* UIC 3 */ #if defined(CONFIG_405EP) || defined(CONFIG_405GP)
#define VECNUM_EIR12 (96 + 20) /* External interrupt 20 */ #define VECNUM_MAL_SERR 10
#define VECNUM_EIR13 (96 + 21) /* External interrupt 21 */ #define VECNUM_MAL_TXEOB 11
#define VECNUM_EIR14 (96 + 22) /* External interrupt 22 */ #define VECNUM_MAL_RXEOB 12
#define VECNUM_EIR15 (96 + 23) /* External interrupt 23 */ #define VECNUM_MAL_TXDE 13
#define VECNUM_PCIEMSI0 (96 + 24) /* PCI Express MSI level 0 */ #define VECNUM_MAL_RXDE 14
#define VECNUM_PCIEMSI1 (96 + 25) /* PCI Express MSI level 1 */ #define VECNUM_ETH0 15
#define VECNUM_PCIEMSI2 (96 + 26) /* PCI Express MSI level 2 */ #define VECNUM_ETH1_OFFS 2
#define VECNUM_PCIEMSI3 (96 + 27) /* PCI Express MSI level 3 */ #define VECNUM_EIRQ6 29
#define VECNUM_PCIEMSI4 (96 + 28) /* PCI Express MSI level 4 */ #endif /* defined(CONFIG_405EP) */
#define VECNUM_PCIEMSI5 (96 + 29) /* PCI Express MSI level 5 */
#define VECNUM_PCIEMSI6 (96 + 30) /* PCI Express MSI level 6 */
#define VECNUM_PCIEMSI7 (96 + 31) /* PCI Express MSI level 7 */
#elif defined(CONFIG_440SPE)
/* UIC 0 */
#define VECNUM_U0 0 /* UART0 */
#define VECNUM_U1 1 /* UART1 */
#define VECNUM_IIC0 2 /* IIC0 */
#define VECNUM_IIC1 3 /* IIC1 */
#define VECNUM_PIM 4 /* PCI inbound message */
#define VECNUM_PCRW 5 /* PCI command reg write */
#define VECNUM_PPM 6 /* PCI power management */
#define VECNUM_MSI0 7 /* PCI MSI level 0 */
#define VECNUM_MSI1 8 /* PCI MSI level 0 */
#define VECNUM_MSI2 9 /* PCI MSI level 0 */
#define VECNUM_UIC2NC 10 /* UIC2 non-critical interrupt */
#define VECNUM_UIC2C 11 /* UIC2 critical interrupt */
#define VECNUM_D0 12 /* DMA channel 0 */
#define VECNUM_D1 13 /* DMA channel 1 */
#define VECNUM_D2 14 /* DMA channel 2 */
#define VECNUM_D3 15 /* DMA channel 3 */
#define VECNUM_UIC3NC 16 /* UIC3 non-critical interrupt */
#define VECNUM_UIC3C 17 /* UIC3 critical interrupt */
#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
/* UIC 1 */
#define VECNUM_MS (32 + 1 ) /* MAL SERR */
#define VECNUM_TXDE (32 + 2 ) /* MAL TXDE */
#define VECNUM_RXDE (32 + 3 ) /* MAL RXDE */
#define VECNUM_MTE (32 + 6 ) /* MAL Tx EOB */
#define VECNUM_MRE (32 + 7 ) /* MAL Rx EOB */
#define VECNUM_CT0 (32 + 12 ) /* GPT compare timer 0 */
#define VECNUM_CT1 (32 + 13 ) /* GPT compare timer 1 */
#define VECNUM_CT2 (32 + 14 ) /* GPT compare timer 2 */
#define VECNUM_CT3 (32 + 15 ) /* GPT compare timer 3 */
#define VECNUM_CT4 (32 + 16 ) /* GPT compare timer 4 */
#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */
#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
/* UIC 2 */
#define VECNUM_EIR5 (64 + 24) /* External interrupt 5 */
#define VECNUM_EIR4 (64 + 25) /* External interrupt 4 */
#define VECNUM_EIR3 (64 + 26) /* External interrupt 3 */
#define VECNUM_EIR2 (64 + 27) /* External interrupt 2 */
#define VECNUM_EIR1 (64 + 28) /* External interrupt 1 */
#define VECNUM_EIR0 (64 + 29) /* External interrupt 0 */
#elif defined(CONFIG_440SP)
/* UIC 0 */
#define VECNUM_U0 0 /* UART0 */
#define VECNUM_U1 1 /* UART1 */
#define VECNUM_IIC0 2 /* IIC0 */
#define VECNUM_IIC1 3 /* IIC1 */
#define VECNUM_PIM 4 /* PCI inbound message */
#define VECNUM_PCRW 5 /* PCI command reg write */
#define VECNUM_PPM 6 /* PCI power management */
#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
/* UIC 1 */
#define VECNUM_EIR0 (32 + 0) /* External interrupt 0 */
#define VECNUM_MS (32 + 1) /* MAL SERR */
#define VECNUM_TXDE (32 + 2) /* MAL TXDE */
#define VECNUM_RXDE (32 + 3) /* MAL RXDE */
#define VECNUM_MTE (32 + 6) /* MAL Tx EOB */
#define VECNUM_MRE (32 + 7) /* MAL Rx EOB */
#define VECNUM_CT0 (32 + 12) /* GPT compare timer 0 */
#define VECNUM_CT1 (32 + 13) /* GPT compare timer 1 */
#define VECNUM_CT2 (32 + 14) /* GPT compare timer 2 */
#define VECNUM_CT3 (32 + 15) /* GPT compare timer 3 */
#define VECNUM_CT4 (32 + 16) /* GPT compare timer 4 */
#define VECNUM_ETH0 (32 + 28) /* Ethernet interrupt status */
#define VECNUM_EWU0 (32 + 29) /* Emac wakeup */
#elif defined(CONFIG_440)
/* UIC 0 */
#define VECNUM_U0 0 /* UART0 */
#define VECNUM_U1 1 /* UART1 */
#define VECNUM_IIC0 2 /* IIC0 */
#define VECNUM_IIC1 3 /* IIC1 */
#define VECNUM_PIM 4 /* PCI inbound message */
#define VECNUM_PCRW 5 /* PCI command reg write */
#define VECNUM_PPM 6 /* PCI power management */
#define VECNUM_MSI0 7 /* PCI MSI level 0 */
#define VECNUM_MSI1 8 /* PCI MSI level 0 */
#define VECNUM_MSI2 9 /* PCI MSI level 0 */
#define VECNUM_MTE 10 /* MAL TXEOB */
#define VECNUM_MRE 11 /* MAL RXEOB */
#define VECNUM_D0 12 /* DMA channel 0 */
#define VECNUM_D1 13 /* DMA channel 1 */
#define VECNUM_D2 14 /* DMA channel 2 */
#define VECNUM_D3 15 /* DMA channel 3 */
#define VECNUM_CT0 18 /* GPT compare timer 0 */
#define VECNUM_CT1 19 /* GPT compare timer 1 */
#define VECNUM_CT2 20 /* GPT compare timer 2 */
#define VECNUM_CT3 21 /* GPT compare timer 3 */
#define VECNUM_CT4 22 /* GPT compare timer 4 */
#define VECNUM_EIR0 23 /* External interrupt 0 */
#define VECNUM_EIR1 24 /* External interrupt 1 */
#define VECNUM_EIR2 25 /* External interrupt 2 */
#define VECNUM_EIR3 26 /* External interrupt 3 */
#define VECNUM_EIR4 27 /* External interrupt 4 */
#define VECNUM_EIR5 28 /* External interrupt 5 */
#define VECNUM_EIR6 29 /* External interrupt 6 */
#define VECNUM_UIC1NC 30 /* UIC1 non-critical interrupt */
#define VECNUM_UIC1C 31 /* UIC1 critical interrupt */
/* UIC 1 */
#define VECNUM_MS (32 + 0 ) /* MAL SERR */
#define VECNUM_TXDE (32 + 1 ) /* MAL TXDE */
#define VECNUM_RXDE (32 + 2 ) /* MAL RXDE */
#define VECNUM_USBDEV (32 + 23) /* USB 1.1/USB 2.0 Device */
#define VECNUM_ETH0 (32 + 28) /* Ethernet 0 interrupt status */
#define VECNUM_EWU0 (32 + 29) /* Ethernet 0 wakeup */
#else /* !defined(CONFIG_440) */
#if defined(CONFIG_405EZ) #if defined(CONFIG_405EZ)
#define VECNUM_D0 0 /* DMA channel 0 */ #define VECNUM_USBDEV 15
#define VECNUM_D1 1 /* DMA channel 1 */ #define VECNUM_ETH0 16
#define VECNUM_D2 2 /* DMA channel 2 */ #define VECNUM_MAL_SERR 18
#define VECNUM_D3 3 /* DMA channel 3 */ #define VECNUM_MAL_TXDE 18
#define VECNUM_1588 4 /* IEEE 1588 network synchronization */ #define VECNUM_MAL_RXDE 18
#define VECNUM_U0 5 /* UART0 */ #define VECNUM_MAL_TXEOB 19
#define VECNUM_U1 6 /* UART1 */ #define VECNUM_MAL_RXEOB 21
#define VECNUM_CAN0 7 /* CAN 0 */ #endif /* CONFIG_405EX */
#define VECNUM_CAN1 8 /* CAN 1 */
#define VECNUM_SPI 9 /* SPI */
#define VECNUM_IIC0 10 /* I2C */
#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */
#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */
#define VECNUM_USBH1 13 /* USB Host 1 */
#define VECNUM_USBH2 14 /* USB Host 2 */
#define VECNUM_USBDEV 15 /* USB Device */
#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */
#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */
#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */
#define VECNUM_MS 18 /* MAL_SERR_INT */
#define VECNUM_TXDE 18 /* MAL_TXDE_INT */
#define VECNUM_RXDE 18 /* MAL_RXDE_INT */
#define VECNUM_MTE 19 /* MAL TXEOB */
#define VECNUM_MTE1 20 /* MAL TXEOB1 */
#define VECNUM_MRE 21 /* MAL RXEOB */
#define VECNUM_NAND 22 /* NAND Flash controller */
#define VECNUM_ADC 23 /* ADC */
#define VECNUM_DAC 24 /* DAC */
#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */
#define VECNUM_RESERVED0 26 /* Reserved */
#define VECNUM_EIR0 27 /* External interrupt 0 */
#define VECNUM_EIR1 28 /* External interrupt 1 */
#define VECNUM_EIR2 29 /* External interrupt 2 */
#define VECNUM_EIR3 30 /* External interrupt 3 */
#define VECNUM_EIR4 31 /* External interrupt 4 */
#elif defined(CONFIG_405EX)
#if defined(CONFIG_405EX)
/* UIC 0 */ /* UIC 0 */
#define VECNUM_U0 00 #define VECNUM_MAL_TXEOB 10
#define VECNUM_U1 01 #define VECNUM_MAL_RXEOB 11
#define VECNUM_IIC0 02
#define VECNUM_PKA 03
#define VECNUM_TRNG 04
#define VECNUM_EBM 05
#define VECNUM_BGI 06
#define VECNUM_IIC1 07
#define VECNUM_SPI 08
#define VECNUM_EIR0 09
#define VECNUM_MTE 10 /* MAL Tx EOB */
#define VECNUM_MRE 11 /* MAL Rx EOB */
#define VECNUM_DMA0 12
#define VECNUM_DMA1 13
#define VECNUM_DMA2 14
#define VECNUM_DMA3 15
#define VECNUM_PCIE0AL 16
#define VECNUM_PCIE0VPD 17
#define VECNUM_RPCIE0HRST 18
#define VECNUM_FPCIE0HRST 19
#define VECNUM_PCIE0TCR 20
#define VECNUM_PCIEMSI0 21
#define VECNUM_PCIEMSI1 22
#define VECNUM_SECURITY 23
#define VECNUM_ETH0 24 #define VECNUM_ETH0 24
#define VECNUM_ETH1 25 #define VECNUM_ETH1_OFFS 1
#define VECNUM_PCIEMSI2 26 #define VECNUM_UIC2NCI 28
#define VECNUM_EIR4 27 #define VECNUM_UIC2CI 29
#define VECNUM_UIC2NC 28 #define VECNUM_UIC1NCI 30
#define VECNUM_UIC2C 29 #define VECNUM_UIC1CI 31
#define VECNUM_UIC1NC 30
#define VECNUM_UIC1C 31
/* UIC 1 */ /* UIC 1 */
#define VECNUM_MS (32 + 00) /* MAL SERR */ #define VECNUM_MAL_SERR (32 + 0)
#define VECNUM_TXDE (32 + 01) /* MAL TXDE */ #define VECNUM_MAL_TXDE (32 + 1)
#define VECNUM_RXDE (32 + 02) /* MAL RXDE */ #define VECNUM_MAL_RXDE (32 + 2)
#define VECNUM_PCIE0BMVC0 (32 + 03) #endif /* CONFIG_405EX */
#define VECNUM_PCIE0DCRERR (32 + 04)
#define VECNUM_EBC (32 + 05) #if defined(CONFIG_440GP) || \
#define VECNUM_NDFC (32 + 06) defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define VECNUM_PCEI1DCRERR (32 + 07) /* UIC 0 */
#define VECNUM_CT8 (32 + 08) #define VECNUM_MAL_TXEOB 10
#define VECNUM_CT9 (32 + 09) #define VECNUM_MAL_RXEOB 11
#define VECNUM_PCIE1AL (32 + 10) #define VECNUM_UIC1NCI 30
#define VECNUM_PCIE1VPD (32 + 11) #define VECNUM_UIC1CI 31
#define VECNUM_RPCE1HRST (32 + 12)
#define VECNUM_FPCE1HRST (32 + 13) /* UIC 1 */
#define VECNUM_PCIE1TCR (32 + 14) #define VECNUM_MAL_SERR (32 + 0)
#define VECNUM_PCIE1VC0 (32 + 15) #define VECNUM_MAL_TXDE (32 + 1)
#define VECNUM_CT3 (32 + 16) #define VECNUM_MAL_RXDE (32 + 2)
#define VECNUM_CT4 (32 + 17) #define VECNUM_USBDEV (32 + 23)
#define VECNUM_EIR7 (32 + 18) #define VECNUM_ETH0 (32 + 28)
#define VECNUM_EIR8 (32 + 19) #define VECNUM_ETH1_OFFS 2
#define VECNUM_EIR9 (32 + 20) #endif /* CONFIG_440GP */
#define VECNUM_CT5 (32 + 21)
#define VECNUM_CT6 (32 + 22) #if defined(CONFIG_440GX)
#define VECNUM_CT7 (32 + 23) /* UIC 0 */
#define VECNUM_SROM (32 + 24) /* SERIAL ROM */ #define VECNUM_MAL_TXEOB 10
#define VECNUM_GPTDECPULS (32 + 25) /* GPT Decrement pulse */ #define VECNUM_MAL_RXEOB 11
#define VECNUM_EIR2 (32 + 26)
#define VECNUM_EIR5 (32 + 27) /* UIC 1 */
#define VECNUM_EIR6 (32 + 28) #define VECNUM_MAL_SERR (32 + 0)
#define VECNUM_EMAC0WAKE (32 + 29) #define VECNUM_MAL_TXDE (32 + 1)
#define VECNUM_EIR1 (32 + 30) #define VECNUM_MAL_RXDE (32 + 2)
#define VECNUM_EMAC1WAKE (32 + 31) #define VECNUM_ETH0 (32 + 28)
#define VECNUM_ETH1_OFFS 2
/* UICB 0 (440GX only) */
#define VECNUM_UIC0CI 0
#define VECNUM_UIC0NCI 1
#define VECNUM_UIC1CI 2
#define VECNUM_UIC1NCI 3
#define VECNUM_UIC2CI 4
#define VECNUM_UIC2NCI 5
#endif /* CONFIG_440GX */
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
/* UIC 0 */
#define VECNUM_MAL_TXEOB 10
#define VECNUM_MAL_RXEOB 11
#define VECNUM_USBDEV 20
#define VECNUM_ETH0 24
#define VECNUM_ETH1_OFFS 1
#define VECNUM_UIC2NCI 28
#define VECNUM_UIC2CI 29
#define VECNUM_UIC1NCI 30
#define VECNUM_UIC1CI 31
/* UIC 1 */
#define VECNUM_MAL_SERR (32 + 0)
#define VECNUM_MAL_TXDE (32 + 1)
#define VECNUM_MAL_RXDE (32 + 2)
/* UIC 2 */ /* UIC 2 */
#define VECNUM_PCIE0INTA (64 + 00) /* PCIE0 INTA */ #define VECNUM_EIRQ2 (64 + 3)
#define VECNUM_PCIE0INTB (64 + 01) /* PCIE0 INTB */ #endif /* CONFIG_440EPX */
#define VECNUM_PCIE0INTC (64 + 02) /* PCIE0 INTC */
#define VECNUM_PCIE0INTD (64 + 03) /* PCIE0 INTD */
#define VECNUM_EIR3 (64 + 04) /* External IRQ 3 */
#define VECNUM_DDRMCUE (64 + 05)
#define VECNUM_DDRMCCE (64 + 06)
#define VECNUM_MALINTCOATX0 (64 + 07) /* Interrupt coalecence TX0 */
#define VECNUM_MALINTCOATX1 (64 + 08) /* Interrupt coalecence TX1 */
#define VECNUM_MALINTCOARX0 (64 + 09) /* Interrupt coalecence RX0 */
#define VECNUM_MALINTCOARX1 (64 + 10) /* Interrupt coalecence RX1 */
#define VECNUM_PCIE1INTA (64 + 11) /* PCIE0 INTA */
#define VECNUM_PCIE1INTB (64 + 12) /* PCIE0 INTB */
#define VECNUM_PCIE1INTC (64 + 13) /* PCIE0 INTC */
#define VECNUM_PCIE1INTD (64 + 14) /* PCIE0 INTD */
#define VECNUM_RPCIEMSI2 (64 + 15) /* MSI level 2 */
#define VECNUM_PCIEMSI3 (64 + 16) /* MSI level 2 */
#define VECNUM_PCIEMSI4 (64 + 17) /* MSI level 2 */
#define VECNUM_PCIEMSI5 (64 + 18) /* MSI level 2 */
#define VECNUM_PCIEMSI6 (64 + 19) /* MSI level 2 */
#define VECNUM_PCIEMSI7 (64 + 20) /* MSI level 2 */
#define VECNUM_PCIEMSI8 (64 + 21) /* MSI level 2 */
#define VECNUM_PCIEMSI9 (64 + 22) /* MSI level 2 */
#define VECNUM_PCIEMSI10 (64 + 23) /* MSI level 2 */
#define VECNUM_PCIEMSI11 (64 + 24) /* MSI level 2 */
#define VECNUM_PCIEMSI12 (64 + 25) /* MSI level 2 */
#define VECNUM_PCIEMSI13 (64 + 26) /* MSI level 2 */
#define VECNUM_PCIEMSI14 (64 + 27) /* MSI level 2 */
#define VECNUM_PCIEMSI15 (64 + 28) /* MSI level 2 */
#define VECNUM_PLB4XAHB (64 + 29) /* PLBxAHB bridge */
#define VECNUM_USBWAKE (64 + 30) /* USB wakup */
#define VECNUM_USBOTG (64 + 31) /* USB OTG */
#else /* !CONFIG_405EZ */ #if defined(CONFIG_440SP)
/* UIC 0 */
#define VECNUM_UIC1NCI 30
#define VECNUM_UIC1CI 31
#define VECNUM_U0 0 /* UART0 */ /* UIC 1 */
#define VECNUM_U1 1 /* UART1 */ #define VECNUM_MAL_SERR (32 + 1)
#define VECNUM_D0 5 /* DMA channel 0 */ #define VECNUM_MAL_TXDE (32 + 2)
#define VECNUM_D1 6 /* DMA channel 1 */ #define VECNUM_MAL_RXDE (32 + 3)
#define VECNUM_D2 7 /* DMA channel 2 */ #define VECNUM_MAL_TXEOB (32 + 6)
#define VECNUM_D3 8 /* DMA channel 3 */ #define VECNUM_MAL_RXEOB (32 + 7)
#define VECNUM_EWU0 9 /* Ethernet wakeup */ #define VECNUM_ETH0 (32 + 28)
#define VECNUM_MS 10 /* MAL SERR */ #endif /* CONFIG_440SP */
#define VECNUM_MTE 11 /* MAL TXEOB */
#define VECNUM_MRE 12 /* MAL RXEOB */
#define VECNUM_TXDE 13 /* MAL TXDE */
#define VECNUM_RXDE 14 /* MAL RXDE */
#define VECNUM_ETH0 15 /* Ethernet interrupt status */
#define VECNUM_EIR0 25 /* External interrupt 0 */
#define VECNUM_EIR1 26 /* External interrupt 1 */
#define VECNUM_EIR2 27 /* External interrupt 2 */
#define VECNUM_EIR3 28 /* External interrupt 3 */
#define VECNUM_EIR4 29 /* External interrupt 4 */
#define VECNUM_EIR5 30 /* External interrupt 5 */
#define VECNUM_EIR6 31 /* External interrupt 6 */
#endif /* defined(CONFIG_405EZ) */
#endif /* defined(CONFIG_440) */ #if defined(CONFIG_440SPE)
/* UIC 0 */
#define VECNUM_UIC2NCI 10
#define VECNUM_UIC2CI 11
#define VECNUM_UIC3NCI 16
#define VECNUM_UIC3CI 17
#define VECNUM_UIC1NCI 30
#define VECNUM_UIC1CI 31
/* UIC 1 */
#define VECNUM_MAL_SERR (32 + 1)
#define VECNUM_MAL_TXDE (32 + 2)
#define VECNUM_MAL_RXDE (32 + 3)
#define VECNUM_MAL_TXEOB (32 + 6)
#define VECNUM_MAL_RXEOB (32 + 7)
#define VECNUM_ETH0 (32 + 28)
#endif /* CONFIG_440SPE */
#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
/* UIC 0 */
#define VECNUM_UIC2NCI 10
#define VECNUM_UIC2CI 11
#define VECNUM_UIC3NCI 16
#define VECNUM_UIC3CI 17
#define VECNUM_UIC1NCI 30
#define VECNUM_UIC1CI 31
/* UIC 2 */
#define VECNUM_MAL_SERR (64 + 3)
#define VECNUM_MAL_TXDE (64 + 4)
#define VECNUM_MAL_RXDE (64 + 5)
#define VECNUM_MAL_TXEOB (64 + 6)
#define VECNUM_MAL_RXEOB (64 + 7)
#define VECNUM_ETH0 (64 + 16)
#define VECNUM_ETH1_OFFS 1
#endif /* CONFIG_460EX */
#if !defined(VECNUM_ETH1_OFFS)
#define VECNUM_ETH1_OFFS 1
#endif
/*
* Mask definitions (used for example in 4xx_enet.c)
*/
#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f))
#define UIC_NR(vec) ((vec) >> 5)
#endif /* _PPC4xx_UIC_H_ */ #endif /* _PPC4xx_UIC_H_ */

2
include/configs/HH405.h
View file

@ -407,7 +407,7 @@
/* /*
* define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
*/ */
#define CFG_UIC0_POLARITY (0xFFFFFF80 | UIC_EXT6) #define CFG_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6))
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* FPGA stuff * FPGA stuff

247
include/ppc405.h
View file

@ -119,253 +119,6 @@
#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ #define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */
#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ #define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */
/******************************************************************************
* Universal interrupt controller
******************************************************************************/
#define UIC_SR 0x0 /* UIC status */
#define UIC_ER 0x2 /* UIC enable */
#define UIC_CR 0x3 /* UIC critical */
#define UIC_PR 0x4 /* UIC polarity */
#define UIC_TR 0x5 /* UIC triggering */
#define UIC_MSR 0x6 /* UIC masked status */
#define UIC_VR 0x7 /* UIC vector */
#define UIC_VCR 0x8 /* UIC vector configuration */
#define UIC_DCR_BASE 0xc0
#define UIC0_DCR_BASE UIC_DCR_BASE
#define uicsr (UIC_DCR_BASE+0x0) /* UIC status */
#define uicsrs (UIC_DCR_BASE+0x1) /* UIC status set */
#define uicer (UIC_DCR_BASE+0x2) /* UIC enable */
#define uiccr (UIC_DCR_BASE+0x3) /* UIC critical */
#define uicpr (UIC_DCR_BASE+0x4) /* UIC polarity */
#define uictr (UIC_DCR_BASE+0x5) /* UIC triggering */
#define uicmsr (UIC_DCR_BASE+0x6) /* UIC masked status */
#define uicvr (UIC_DCR_BASE+0x7) /* UIC vector */
#define uicvcr (UIC_DCR_BASE+0x8) /* UIC vector configuration */
#if defined(CONFIG_405EX)
#define uic0sr uicsr /* UIC status */
#define uic0srs uicsrs /* UIC status set */
#define uic0er uicer /* UIC enable */
#define uic0cr uiccr /* UIC critical */
#define uic0pr uicpr /* UIC polarity */
#define uic0tr uictr /* UIC triggering */
#define uic0msr uicmsr /* UIC masked status */
#define uic0vr uicvr /* UIC vector */
#define uic0vcr uicvcr /* UIC vector configuration*/
#define UIC_DCR_BASE1 0xd0
#define UIC1_DCR_BASE 0xd0
#define uic1sr (UIC_DCR_BASE1+0x0) /* UIC status */
#define uic1srs (UIC_DCR_BASE1+0x1) /* UIC status set */
#define uic1er (UIC_DCR_BASE1+0x2) /* UIC enable */
#define uic1cr (UIC_DCR_BASE1+0x3) /* UIC critical */
#define uic1pr (UIC_DCR_BASE1+0x4) /* UIC polarity */
#define uic1tr (UIC_DCR_BASE1+0x5) /* UIC triggering */
#define uic1msr (UIC_DCR_BASE1+0x6) /* UIC masked status */
#define uic1vr (UIC_DCR_BASE1+0x7) /* UIC vector */
#define uic1vcr (UIC_DCR_BASE1+0x8) /* UIC vector configuration*/
#define UIC_DCR_BASE2 0xe0
#define UIC2_DCR_BASE 0xe0
#define uic2sr (UIC_DCR_BASE2+0x0) /* UIC status */
#define uic2srs (UIC_DCR_BASE2+0x1) /* UIC status set */
#define uic2er (UIC_DCR_BASE2+0x2) /* UIC enable */
#define uic2cr (UIC_DCR_BASE2+0x3) /* UIC critical */
#define uic2pr (UIC_DCR_BASE2+0x4) /* UIC polarity */
#define uic2tr (UIC_DCR_BASE2+0x5) /* UIC triggering */
#define uic2msr (UIC_DCR_BASE2+0x6) /* UIC masked status */
#define uic2vr (UIC_DCR_BASE2+0x7) /* UIC vector */
#define uic2vcr (UIC_DCR_BASE2+0x8) /* UIC vector configuration*/
#endif
/*-----------------------------------------------------------------------------+
| Universal interrupt controller interrupts
+-----------------------------------------------------------------------------*/
#if defined(CONFIG_405EZ)
#define UIC_DMA0 0x80000000 /* DMA chan. 0 */
#define UIC_DMA1 0x40000000 /* DMA chan. 1 */
#define UIC_DMA2 0x20000000 /* DMA chan. 2 */
#define UIC_DMA3 0x10000000 /* DMA chan. 3 */
#define UIC_1588 0x08000000 /* IEEE 1588 network synchronization */
#define UIC_UART0 0x04000000 /* UART 0 */
#define UIC_UART1 0x02000000 /* UART 1 */
#define UIC_CAN0 0x01000000 /* CAN 0 */
#define UIC_CAN1 0x00800000 /* CAN 1 */
#define UIC_SPI 0x00400000 /* SPI */
#define UIC_IIC 0x00200000 /* IIC */
#define UIC_CHT0 0x00100000 /* Chameleon timer high pri interrupt */
#define UIC_CHT1 0x00080000 /* Chameleon timer high pri interrupt */
#define UIC_USBH1 0x00040000 /* USB Host 1 */
#define UIC_USBH2 0x00020000 /* USB Host 2 */
#define UIC_USBDEV 0x00010000 /* USB Device */
#define UIC_ENET 0x00008000 /* Ethernet interrupt status */
#define UIC_ENET1 0x00008000 /* dummy define */
#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */
#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */
#define UIC_MAL_SERR 0x00002000 /* MAL SERR */
#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */
#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */
#define UIC_MAL_TXEOB 0x00001000 /* MAL TXEOB */
#define UIC_MAL_TXEOB1 0x00000800 /* MAL TXEOB1 */
#define UIC_MAL_RXEOB 0x00000400 /* MAL RXEOB */
#define UIC_NAND 0x00000200 /* NAND Flash controller */
#define UIC_ADC 0x00000100 /* ADC */
#define UIC_DAC 0x00000080 /* DAC */
#define UIC_OPB2PLB 0x00000040 /* OPB to PLB bridge interrupt */
#define UIC_RESERVED0 0x00000020 /* Reserved */
#define UIC_EXT0 0x00000010 /* External interrupt 0 */
#define UIC_EXT1 0x00000008 /* External interrupt 1 */
#define UIC_EXT2 0x00000004 /* External interrupt 2 */
#define UIC_EXT3 0x00000002 /* External interrupt 3 */
#define UIC_EXT4 0x00000001 /* External interrupt 4 */
#elif defined(CONFIG_405EX)
/* UIC 0 */
#define UIC_U0 0x80000000 /* */
#define UIC_U1 0x40000000 /* */
#define UIC_IIC0 0x20000000 /* */
#define UIC_PKA 0x10000000 /* */
#define UIC_TRNG 0x08000000 /* */
#define UIC_EBM 0x04000000 /* */
#define UIC_BGI 0x02000000 /* */
#define UIC_IIC1 0x01000000 /* */
#define UIC_SPI 0x00800000 /* */
#define UIC_EIRQ0 0x00400000 /**/
#define UIC_MTE 0x00200000 /*MAL Tx EOB */
#define UIC_MRE 0x00100000 /*MAL Rx EOB */
#define UIC_DMA0 0x00080000 /* */
#define UIC_DMA1 0x00040000 /* */
#define UIC_DMA2 0x00020000 /* */
#define UIC_DMA3 0x00010000 /* */
#define UIC_PCIE0AL 0x00008000 /* */
#define UIC_PCIE0VPD 0x00004000 /* */
#define UIC_RPCIE0HRST 0x00002000 /* */
#define UIC_FPCIE0HRST 0x00001000 /* */
#define UIC_PCIE0TCR 0x00000800 /* */
#define UIC_PCIEMSI0 0x00000400 /* */
#define UIC_PCIEMSI1 0x00000200 /* */
#define UIC_SECURITY 0x00000100 /* */
#define UIC_ENET 0x00000080 /* */
#define UIC_ENET1 0x00000040 /* */
#define UIC_PCIEMSI2 0x00000020 /* */
#define UIC_EIRQ4 0x00000010 /**/
#define UICB0_UIC2NCI 0x00000008 /* */
#define UICB0_UIC2CI 0x00000004 /* */
#define UICB0_UIC1NCI 0x00000002 /* */
#define UICB0_UIC1CI 0x00000001 /* */
#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \
UICB0_UIC1CI | UICB0_UIC2NCI)
#define UIC_MAL_TXEOB UIC_MTE/* MAL TXEOB */
#define UIC_MAL_RXEOB UIC_MRE/* MAL RXEOB */
/* UIC 1 */
#define UIC_MS 0x80000000 /* MAL SERR */
#define UIC_MTDE 0x40000000 /* MAL TXDE */
#define UIC_MRDE 0x20000000 /* MAL RXDE */
#define UIC_PCIE0BMVC0 0x10000000 /* */
#define UIC_PCIE0DCRERR 0x08000000 /* */
#define UIC_EBC 0x04000000 /* */
#define UIC_NDFC 0x02000000 /* */
#define UIC_PCEI1DCRERR 0x01000000 /* */
#define UIC_GPTCMPT8 0x00800000 /* */
#define UIC_GPTCMPT9 0x00400000 /* */
#define UIC_PCIE1AL 0x00200000 /* */
#define UIC_PCIE1VPD 0x00100000 /* */
#define UIC_RPCE1HRST 0x00080000 /* */
#define UIC_FPCE1HRST 0x00040000 /* */
#define UIC_PCIE1TCR 0x00020000 /* */
#define UIC_PCIE1VC0 0x00010000 /* */
#define UIC_GPTCMPT3 0x00008000 /* */
#define UIC_GPTCMPT4 0x00004000 /* */
#define UIC_EIRQ7 0x00002000 /* */
#define UIC_EIRQ8 0x00001000 /* */
#define UIC_EIRQ9 0x00000800 /* */
#define UIC_GPTCMP5 0x00000400 /* */
#define UIC_GPTCMP6 0x00000200 /* */
#define UIC_GPTCMP7 0x00000100 /* */
#define UIC_SROM 0x00000080 /* SERIAL ROM*/
#define UIC_GPTDECPULS 0x00000040 /* GPT Decrement pulse*/
#define UIC_EIRQ2 0x00000020 /* */
#define UIC_EIRQ5 0x00000010 /* */
#define UIC_EIRQ6 0x00000008 /* */
#define UIC_EMAC0WAKE 0x00000004 /* */
#define UIC_EIRQ1 0x00000002 /* */
#define UIC_EMAC1WAKE 0x00000001 /* */
#define UIC_MAL_SERR UIC_MS /* MAL SERR */
#define UIC_MAL_TXDE UIC_MTDE /* MAL TXDE */
#define UIC_MAL_RXDE UIC_MRDE /* MAL RXDE */
/* UIC 2 */
#define UIC_PCIE0INTA 0x80000000 /* PCIE0 INTA*/
#define UIC_PCIE0INTB 0x40000000 /* PCIE0 INTB*/
#define UIC_PCIE0INTC 0x20000000 /* PCIE0 INTC*/
#define UIC_PCIE0INTD 0x10000000 /* PCIE0 INTD*/
#define UIC_EIRQ3 0x08000000 /* External IRQ 3*/
#define UIC_DDRMCUE 0x04000000 /* */
#define UIC_DDRMCCE 0x02000000 /* */
#define UIC_MALINTCOATX0 0x01000000 /* Interrupt coalecence TX0*/
#define UIC_MALINTCOATX1 0x00800000 /* Interrupt coalecence TX1*/
#define UIC_MALINTCOARX0 0x00400000 /* Interrupt coalecence RX0*/
#define UIC_MALINTCOARX1 0x00200000 /* Interrupt coalecence RX1*/
#define UIC_PCIE1INTA 0x00100000 /* PCIE0 INTA*/
#define UIC_PCIE1INTB 0x00080000 /* PCIE0 INTB*/
#define UIC_PCIE1INTC 0x00040000 /* PCIE0 INTC*/
#define UIC_PCIE1INTD 0x00020000 /* PCIE0 INTD*/
#define UIC_RPCIEMSI2 0x00010000 /* MSI level 2 Note this looks same as uic0-26*/
#define UIC_PCIEMSI3 0x00008000 /* MSI level 2*/
#define UIC_PCIEMSI4 0x00004000 /* MSI level 2*/
#define UIC_PCIEMSI5 0x00002000 /* MSI level 2*/
#define UIC_PCIEMSI6 0x00001000 /* MSI level 2*/
#define UIC_PCIEMSI7 0x00000800 /* MSI level 2*/
#define UIC_PCIEMSI8 0x00000400 /* MSI level 2*/
#define UIC_PCIEMSI9 0x00000200 /* MSI level 2*/
#define UIC_PCIEMSI10 0x00000100 /* MSI level 2*/
#define UIC_PCIEMSI11 0x00000080 /* MSI level 2*/
#define UIC_PCIEMSI12 0x00000040 /* MSI level 2*/
#define UIC_PCIEMSI13 0x00000020 /* MSI level 2*/
#define UIC_PCIEMSI14 0x00000010 /* MSI level 2*/
#define UIC_PCIEMSI15 0x00000008 /* MSI level 2*/
#define UIC_PLB4XAHB 0x00000004 /* PLBxAHB bridge*/
#define UIC_USBWAKE 0x00000002 /* USB wakup*/
#define UIC_USBOTG 0x00000001 /* USB OTG*/
#define UIC_ETH0 UIC_ENET
#define UIC_ETH1 UIC_ENET1
#else /* !defined(CONFIG_405EZ) */
#define UIC_UART0 0x80000000 /* UART 0 */
#define UIC_UART1 0x40000000 /* UART 1 */
#define UIC_IIC 0x20000000 /* IIC */
#define UIC_EXT_MAST 0x10000000 /* External Master */
#define UIC_PCI 0x08000000 /* PCI write to command reg */
#define UIC_DMA0 0x04000000 /* DMA chan. 0 */
#define UIC_DMA1 0x02000000 /* DMA chan. 1 */
#define UIC_DMA2 0x01000000 /* DMA chan. 2 */
#define UIC_DMA3 0x00800000 /* DMA chan. 3 */
#define UIC_EMAC_WAKE 0x00400000 /* EMAC wake up */
#define UIC_MAL_SERR 0x00200000 /* MAL SERR */
#define UIC_MAL_TXEOB 0x00100000 /* MAL TXEOB */
#define UIC_MAL_RXEOB 0x00080000 /* MAL RXEOB */
#define UIC_MAL_TXDE 0x00040000 /* MAL TXDE */
#define UIC_MAL_RXDE 0x00020000 /* MAL RXDE */
#define UIC_ENET 0x00010000 /* Ethernet0 */
#define UIC_ENET1 0x00004000 /* Ethernet1 on 405EP */
#define UIC_ECC_CE 0x00004000 /* ECC Correctable Error on 405GP */
#define UIC_EXT_PCI_SERR 0x00008000 /* External PCI SERR# */
#define UIC_PCI_PM 0x00002000 /* PCI Power Management */
#define UIC_EXT0 0x00000040 /* External interrupt 0 */
#define UIC_EXT1 0x00000020 /* External interrupt 1 */
#define UIC_EXT2 0x00000010 /* External interrupt 2 */
#define UIC_EXT3 0x00000008 /* External interrupt 3 */
#define UIC_EXT4 0x00000004 /* External interrupt 4 */
#define UIC_EXT5 0x00000002 /* External interrupt 5 */
#define UIC_EXT6 0x00000001 /* External interrupt 6 */
#endif /* defined(CONFIG_405EZ) */
#ifndef CONFIG_405EP #ifndef CONFIG_405EP
/****************************************************************************** /******************************************************************************
* Decompression Controller * Decompression Controller

708
include/ppc440.h
View file

@ -864,98 +864,6 @@
#define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ #define cntrl0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */
#define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ #define cntrl1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */
/*-----------------------------------------------------------------------------
| Universal interrupt controller
+----------------------------------------------------------------------------*/
#define UIC_SR 0x0 /* UIC status */
#define UIC_ER 0x2 /* UIC enable */
#define UIC_CR 0x3 /* UIC critical */
#define UIC_PR 0x4 /* UIC polarity */
#define UIC_TR 0x5 /* UIC triggering */
#define UIC_MSR 0x6 /* UIC masked status */
#define UIC_VR 0x7 /* UIC vector */
#define UIC_VCR 0x8 /* UIC vector configuration */
#define UIC0_DCR_BASE 0xc0
#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */
#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */
#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */
#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */
#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */
#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */
#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */
#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */
#define UIC1_DCR_BASE 0xd0
#define uic1sr (UIC1_DCR_BASE+0x0) /* UIC1 status */
#define uic1er (UIC1_DCR_BASE+0x2) /* UIC1 enable */
#define uic1cr (UIC1_DCR_BASE+0x3) /* UIC1 critical */
#define uic1pr (UIC1_DCR_BASE+0x4) /* UIC1 polarity */
#define uic1tr (UIC1_DCR_BASE+0x5) /* UIC1 triggering */
#define uic1msr (UIC1_DCR_BASE+0x6) /* UIC1 masked status */
#define uic1vr (UIC1_DCR_BASE+0x7) /* UIC1 vector */
#define uic1vcr (UIC1_DCR_BASE+0x8) /* UIC1 vector configuration */
#if defined(CONFIG_440SPE) || \
defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_460SX)
#define UIC2_DCR_BASE 0xe0
#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */
#define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */
#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
#define UIC3_DCR_BASE 0xf0
#define uic3sr (UIC3_DCR_BASE+0x0) /* UIC3 status-Read Clear */
#define uic3srs (UIC3_DCR_BASE+0x1) /* UIC3 status-Read Set */
#define uic3er (UIC3_DCR_BASE+0x2) /* UIC3 enable */
#define uic3cr (UIC3_DCR_BASE+0x3) /* UIC3 critical */
#define uic3pr (UIC3_DCR_BASE+0x4) /* UIC3 polarity */
#define uic3tr (UIC3_DCR_BASE+0x5) /* UIC3 triggering */
#define uic3msr (UIC3_DCR_BASE+0x6) /* UIC3 masked status */
#define uic3vr (UIC3_DCR_BASE+0x7) /* UIC3 vector */
#define uic3vcr (UIC3_DCR_BASE+0x8) /* UIC3 vector configuration */
#endif /* CONFIG_440SPE */
#if defined(CONFIG_440GX)
#define UIC2_DCR_BASE 0x210
#define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status */
#define uic2er (UIC2_DCR_BASE+0x2) /* UIC2 enable */
#define uic2cr (UIC2_DCR_BASE+0x3) /* UIC2 critical */
#define uic2pr (UIC2_DCR_BASE+0x4) /* UIC2 polarity */
#define uic2tr (UIC2_DCR_BASE+0x5) /* UIC2 triggering */
#define uic2msr (UIC2_DCR_BASE+0x6) /* UIC2 masked status */
#define uic2vr (UIC2_DCR_BASE+0x7) /* UIC2 vector */
#define uic2vcr (UIC2_DCR_BASE+0x8) /* UIC2 vector configuration */
#define UIC_DCR_BASE 0x200
#define uicb0sr (UIC_DCR_BASE+0x0) /* UIC Base Status Register */
#define uicb0er (UIC_DCR_BASE+0x2) /* UIC Base enable */
#define uicb0cr (UIC_DCR_BASE+0x3) /* UIC Base critical */
#define uicb0pr (UIC_DCR_BASE+0x4) /* UIC Base polarity */
#define uicb0tr (UIC_DCR_BASE+0x5) /* UIC Base triggering */
#define uicb0msr (UIC_DCR_BASE+0x6) /* UIC Base masked status */
#define uicb0vr (UIC_DCR_BASE+0x7) /* UIC Base vector */
#define uicb0vcr (UIC_DCR_BASE+0x8) /* UIC Base vector configuration */
#endif /* CONFIG_440GX */
/* The following is for compatibility with 405 code */
#define uicsr uic0sr
#define uicer uic0er
#define uiccr uic0cr
#define uicpr uic0pr
#define uictr uic0tr
#define uicmsr uic0msr
#define uicvr uic0vr
#define uicvcr uic0vcr
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX)
/*----------------------------------------------------------------------------+ /*----------------------------------------------------------------------------+
| Clock / Power-on-reset DCR's. | Clock / Power-on-reset DCR's.
@ -1139,622 +1047,6 @@
#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ #define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */
#endif /* CONFIG_440GX */ #endif /* CONFIG_440GX */
/*---------------------------------------------------------------------------+
| Universal interrupt controller 0 interrupts (UIC0)
+---------------------------------------------------------------------------*/
#if defined(CONFIG_440SP)
#define UIC_U0 0x80000000 /* UART 0 */
#define UIC_U1 0x40000000 /* UART 1 */
#define UIC_IIC0 0x20000000 /* IIC */
#define UIC_IIC1 0x10000000 /* IIC */
#define UIC_PIM 0x08000000 /* PCI0 inbound message */
#define UIC_PCRW 0x04000000 /* PCI0 command write register */
#define UIC_PPM 0x02000000 /* PCI0 power management */
#define UIC_PVPD 0x01000000 /* PCI0 VPD Access */
#define UIC_MSI0 0x00800000 /* PCI0 MSI level 0 */
#define UIC_P1IM 0x00400000 /* PCI1 Inbound Message */
#define UIC_P1CRW 0x00200000 /* PCI1 command write register */
#define UIC_P1PM 0x00100000 /* PCI1 power management */
#define UIC_P1VPD 0x00080000 /* PCI1 VPD Access */
#define UIC_P1MSI0 0x00040000 /* PCI1 MSI level 0 */
#define UIC_P2IM 0x00020000 /* PCI2 inbound message */
#define UIC_P2CRW 0x00010000 /* PCI2 command register write */
#define UIC_P2PM 0x00008000 /* PCI2 power management */
#define UIC_P2VPD 0x00004000 /* PCI2 VPD access */
#define UIC_P2MSI0 0x00002000 /* PCI2 MSI level 0 */
#define UIC_D0CPF 0x00001000 /* DMA0 command pointer */
#define UIC_D0CSF 0x00000800 /* DMA0 command status */
#define UIC_D1CPF 0x00000400 /* DMA1 command pointer */
#define UIC_D1CSF 0x00000200 /* DMA1 command status */
#define UIC_I2OID 0x00000100 /* I2O inbound doorbell */
#define UIC_I2OPLF 0x00000080 /* I2O inbound post list */
#define UIC_I2O0LL 0x00000040 /* I2O0 low latency PLB write */
#define UIC_I2O1LL 0x00000020 /* I2O1 low latency PLB write */
#define UIC_I2O0HB 0x00000010 /* I2O0 high bandwidth PLB write */
#define UIC_I2O1HB 0x00000008 /* I2O1 high bandwidth PLB write */
#define UIC_GPTCT 0x00000004 /* GPT count timer */
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
#elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
#define UIC_U0 0x80000000 /* UART 0 */
#define UIC_U1 0x40000000 /* UART 1 */
#define UIC_IIC0 0x20000000 /* IIC */
#define UIC_IIC1 0x10000000 /* IIC */
#define UIC_PIM 0x08000000 /* PCI inbound message */
#define UIC_PCRW 0x04000000 /* PCI command register write */
#define UIC_PPM 0x02000000 /* PCI power management */
#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
#define UIC_MTE 0x00200000 /* MAL TXEOB */
#define UIC_MRE 0x00100000 /* MAL RXEOB */
#define UIC_D0 0x00080000 /* DMA channel 0 */
#define UIC_D1 0x00040000 /* DMA channel 1 */
#define UIC_D2 0x00020000 /* DMA channel 2 */
#define UIC_D3 0x00010000 /* DMA channel 3 */
#define UIC_RSVD0 0x00008000 /* Reserved */
#define UIC_RSVD1 0x00004000 /* Reserved */
#define UIC_CT0 0x00002000 /* GPT compare timer 0 */
#define UIC_CT1 0x00001000 /* GPT compare timer 1 */
#define UIC_CT2 0x00000800 /* GPT compare timer 2 */
#define UIC_CT3 0x00000400 /* GPT compare timer 3 */
#define UIC_CT4 0x00000200 /* GPT compare timer 4 */
#define UIC_EIR0 0x00000100 /* External interrupt 0 */
#define UIC_EIR1 0x00000080 /* External interrupt 1 */
#define UIC_EIR2 0x00000040 /* External interrupt 2 */
#define UIC_EIR3 0x00000020 /* External interrupt 3 */
#define UIC_EIR4 0x00000010 /* External interrupt 4 */
#define UIC_EIR5 0x00000008 /* External interrupt 5 */
#define UIC_EIR6 0x00000004 /* External interrupt 6 */
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define UIC_U0 0x80000000 /* UART 0 */
#define UIC_U1 0x40000000 /* UART 1 */
#define UIC_IIC0 0x20000000 /* IIC */
#define UIC_KRD 0x10000000 /* Kasumi Ready for data */
#define UIC_KDA 0x08000000 /* Kasumi Data Available */
#define UIC_PCRW 0x04000000 /* PCI command register write */
#define UIC_PPM 0x02000000 /* PCI power management */
#define UIC_IIC1 0x01000000 /* IIC */
#define UIC_SPI 0x00800000 /* SPI */
#define UIC_EPCISER 0x00400000 /* External PCI SERR */
#define UIC_MTE 0x00200000 /* MAL TXEOB */
#define UIC_MRE 0x00100000 /* MAL RXEOB */
#define UIC_D0 0x00080000 /* DMA channel 0 */
#define UIC_D1 0x00040000 /* DMA channel 1 */
#define UIC_D2 0x00020000 /* DMA channel 2 */
#define UIC_D3 0x00010000 /* DMA channel 3 */
#define UIC_UD0 0x00008000 /* UDMA irq 0 */
#define UIC_UD1 0x00004000 /* UDMA irq 1 */
#define UIC_UD2 0x00002000 /* UDMA irq 2 */
#define UIC_UD3 0x00001000 /* UDMA irq 3 */
#define UIC_HSB2D 0x00000800 /* USB2.0 Device */
#define UIC_OHCI1 0x00000400 /* USB2.0 Host OHCI irq 1 */
#define UIC_OHCI2 0x00000200 /* USB2.0 Host OHCI irq 2 */
#define UIC_EIP94 0x00000100 /* Security EIP94 */
#define UIC_ETH0 0x00000080 /* Emac 0 */
#define UIC_ETH1 0x00000040 /* Emac 1 */
#define UIC_EHCI 0x00000020 /* USB2.0 Host EHCI */
#define UIC_EIR4 0x00000010 /* External interrupt 4 */
#define UIC_UIC2NC 0x00000008 /* UIC2 non-critical interrupt */
#define UIC_UIC2C 0x00000004 /* UIC2 critical interrupt */
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
/* For compatibility with 405 code */
#define UIC_MAL_TXEOB UIC_MTE
#define UIC_MAL_RXEOB UIC_MRE
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define UIC_RSVD0 0x80000000 /* N/A - unused */
#define UIC_U1 0x40000000 /* UART 1 */
#define UIC_IIC0 0x20000000 /* IIC */
#define UIC_IIC1 0x10000000 /* IIC */
#define UIC_PIM 0x08000000 /* PCI inbound message */
#define UIC_PCRW 0x04000000 /* PCI command register write */
#define UIC_PPM 0x02000000 /* PCI power management */
#define UIC_PCIVPD 0x01000000 /* PCI VPD */
#define UIC_MSI0 0x00800000 /* PCI MSI level 0 */
#define UIC_EIR0 0x00400000 /* External interrupt 0 */
#define UIC_UIC2NC 0x00200000 /* UIC2 non-critical interrupt */
#define UIC_UIC2C 0x00100000 /* UIC2 critical interrupt */
#define UIC_D0 0x00080000 /* DMA channel 0 */
#define UIC_D1 0x00040000 /* DMA channel 1 */
#define UIC_D2 0x00020000 /* DMA channel 2 */
#define UIC_D3 0x00010000 /* DMA channel 3 */
#define UIC_UIC3NC 0x00008000 /* UIC3 non-critical interrupt */
#define UIC_UIC3C 0x00004000 /* UIC3 critical interrupt */
#define UIC_EIR1 0x00002000 /* External interrupt 1 */
#define UIC_TRNGDA 0x00001000 /* TRNG data available */
#define UIC_PKAR1 0x00000800 /* PKA ready (PKA[1]) */
#define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */
#define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */
#define UIC_I2OID 0x00000100 /* I2O inbound door bell */
#define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */
#define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */
#define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */
#define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */
#define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */
#define UIC_EIP94 0x00000004 /* Security EIP94 */
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
#elif !defined(CONFIG_440SPE)
#define UIC_U0 0x80000000 /* UART 0 */
#define UIC_U1 0x40000000 /* UART 1 */
#define UIC_IIC0 0x20000000 /* IIC */
#define UIC_IIC1 0x10000000 /* IIC */
#define UIC_PIM 0x08000000 /* PCI inbound message */
#define UIC_PCRW 0x04000000 /* PCI command register write */
#define UIC_PPM 0x02000000 /* PCI power management */
#define UIC_MSI0 0x01000000 /* PCI MSI level 0 */
#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
#define UIC_MTE 0x00200000 /* MAL TXEOB */
#define UIC_MRE 0x00100000 /* MAL RXEOB */
#define UIC_D0 0x00080000 /* DMA channel 0 */
#define UIC_D1 0x00040000 /* DMA channel 1 */
#define UIC_D2 0x00020000 /* DMA channel 2 */
#define UIC_D3 0x00010000 /* DMA channel 3 */
#define UIC_RSVD0 0x00008000 /* Reserved */
#define UIC_RSVD1 0x00004000 /* Reserved */
#define UIC_CT0 0x00002000 /* GPT compare timer 0 */
#define UIC_CT1 0x00001000 /* GPT compare timer 1 */
#define UIC_CT2 0x00000800 /* GPT compare timer 2 */
#define UIC_CT3 0x00000400 /* GPT compare timer 3 */
#define UIC_CT4 0x00000200 /* GPT compare timer 4 */
#define UIC_EIR0 0x00000100 /* External interrupt 0 */
#define UIC_EIR1 0x00000080 /* External interrupt 1 */
#define UIC_EIR2 0x00000040 /* External interrupt 2 */
#define UIC_EIR3 0x00000020 /* External interrupt 3 */
#define UIC_EIR4 0x00000010 /* External interrupt 4 */
#define UIC_EIR5 0x00000008 /* External interrupt 5 */
#define UIC_EIR6 0x00000004 /* External interrupt 6 */
#define UIC_UIC1NC 0x00000002 /* UIC1 non-critical interrupt */
#define UIC_UIC1C 0x00000001 /* UIC1 critical interrupt */
#endif /* CONFIG_440GX */
/* For compatibility with 405 code */
#define UIC_MAL_TXEOB UIC_MTE
#define UIC_MAL_RXEOB UIC_MRE
/*---------------------------------------------------------------------------+
| Universal interrupt controller 1 interrupts (UIC1)
+---------------------------------------------------------------------------*/
#if defined(CONFIG_440SP)
#define UIC_EIR0 0x80000000 /* External interrupt 0 */
#define UIC_MS 0x40000000 /* MAL SERR */
#define UIC_MTDE 0x20000000 /* MAL TXDE */
#define UIC_MRDE 0x10000000 /* MAL RXDE */
#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
#define UIC_MTE 0x02000000 /* MAL TXEOB */
#define UIC_MRE 0x01000000 /* MAL RXEOB */
#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */
#define UIC_P1MSI1 0x00400000 /* PCI1 MSI level 1 */
#define UIC_P2MSI1 0x00200000 /* PCI2 MSI level 1 */
#define UIC_L2C 0x00100000 /* L2 cache */
#define UIC_CT0 0x00080000 /* GPT compare timer 0 */
#define UIC_CT1 0x00040000 /* GPT compare timer 1 */
#define UIC_CT2 0x00020000 /* GPT compare timer 2 */
#define UIC_CT3 0x00010000 /* GPT compare timer 3 */
#define UIC_CT4 0x00008000 /* GPT compare timer 4 */
#define UIC_EIR1 0x00004000 /* External interrupt 1 */
#define UIC_EIR2 0x00002000 /* External interrupt 2 */
#define UIC_EIR3 0x00001000 /* External interrupt 3 */
#define UIC_EIR4 0x00000800 /* External interrupt 4 */
#define UIC_EIR5 0x00000400 /* External interrupt 5 */
#define UIC_DMAE 0x00000200 /* DMA error */
#define UIC_I2OE 0x00000100 /* I2O error */
#define UIC_SRE 0x00000080 /* Serial ROM error */
#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */
#define UIC_P1AE 0x00000020 /* PCI1 asynchronous error */
#define UIC_P2AE 0x00000010 /* PCI2 asynchronous error */
#define UIC_ETH0 0x00000008 /* Ethernet 0 */
#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
#define UIC_ETH1 0x00000002 /* Reserved */
#define UIC_XOR 0x00000001 /* XOR */
#elif defined(CONFIG_440GX) || defined(CONFIG_440EP)
#define UIC_MS 0x80000000 /* MAL SERR */
#define UIC_MTDE 0x40000000 /* MAL TXDE */
#define UIC_MRDE 0x20000000 /* MAL RXDE */
#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
#define UIC_EBMI 0x02000000 /* EBMI interrupt status */
#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
#define UIC_PPMI 0x00004000 /* PPM interrupt status */
#define UIC_EIR7 0x00002000 /* External interrupt 7 */
#define UIC_EIR8 0x00001000 /* External interrupt 8 */
#define UIC_EIR9 0x00000800 /* External interrupt 9 */
#define UIC_EIR10 0x00000400 /* External interrupt 10 */
#define UIC_EIR11 0x00000200 /* External interrupt 11 */
#define UIC_EIR12 0x00000100 /* External interrupt 12 */
#define UIC_SRE 0x00000080 /* Serial ROM error */
#define UIC_RSVD2 0x00000040 /* Reserved */
#define UIC_RSVD3 0x00000020 /* Reserved */
#define UIC_PAE 0x00000010 /* PCI asynchronous error */
#define UIC_ETH0 0x00000008 /* Ethernet 0 */
#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
#define UIC_ETH1 0x00000002 /* Ethernet 1 */
#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define UIC_EIR2 0x80000000 /* External interrupt 2 */
#define UIC_U0 0x40000000 /* UART 0 */
#define UIC_SPI 0x20000000 /* SPI */
#define UIC_TRNGAL 0x10000000 /* TRNG alarm */
#define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */
#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
#define UIC_NDFC 0x02000000 /* NDFC */
#define UIC_EIPPKPSE 0x01000000 /* EIPPKP slave error */
#define UIC_P0MSI1 0x00800000 /* PCI0 MSI level 1 */
#define UIC_P0MSI2 0x00400000 /* PCI0 MSI level 2 */
#define UIC_P0MSI3 0x00200000 /* PCI0 MSI level 3 */
#define UIC_L2C 0x00100000 /* L2 cache */
#define UIC_CT0 0x00080000 /* GPT compare timer 0 */
#define UIC_CT1 0x00040000 /* GPT compare timer 1 */
#define UIC_CT2 0x00020000 /* GPT compare timer 2 */
#define UIC_CT3 0x00010000 /* GPT compare timer 3 */
#define UIC_CT4 0x00008000 /* GPT compare timer 4 */
#define UIC_CT5 0x00004000 /* GPT compare timer 5 */
#define UIC_CT6 0x00002000 /* GPT compare timer 6 */
#define UIC_GPTDC 0x00001000 /* GPT decrementer pulse */
#define UIC_EIR3 0x00000800 /* External interrupt 3 */
#define UIC_EIR4 0x00000400 /* External interrupt 4 */
#define UIC_DMAE 0x00000200 /* DMA error */
#define UIC_I2OE 0x00000100 /* I2O error */
#define UIC_SRE 0x00000080 /* Serial ROM error */
#define UIC_P0AE 0x00000040 /* PCI0 asynchronous error */
#define UIC_EIR5 0x00000020 /* External interrupt 5 */
#define UIC_EIR6 0x00000010 /* External interrupt 6 */
#define UIC_U2 0x00000008 /* UART 2 */
#define UIC_U3 0x00000004 /* UART 3 */
#define UIC_EIR7 0x00000002 /* External interrupt 7 */
#define UIC_EIR8 0x00000001 /* External interrupt 8 */
#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define UIC_MS 0x80000000 /* MAL SERR */
#define UIC_MTDE 0x40000000 /* MAL TXDE */
#define UIC_MRDE 0x20000000 /* MAL RXDE */
#define UIC_U2 0x10000000 /* UART 2 */
#define UIC_U3 0x08000000 /* UART 3 */
#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
#define UIC_NDFC 0x02000000 /* NDFC */
#define UIC_KSLE 0x01000000 /* KASUMI slave error */
#define UIC_CT5 0x00800000 /* GPT compare timer 5 */
#define UIC_CT6 0x00400000 /* GPT compare timer 6 */
#define UIC_PLB34I0 0x00200000 /* PLB3X4X MIRQ0 */
#define UIC_PLB34I1 0x00100000 /* PLB3X4X MIRQ1 */
#define UIC_PLB34I2 0x00080000 /* PLB3X4X MIRQ2 */
#define UIC_PLB34I3 0x00040000 /* PLB3X4X MIRQ3 */
#define UIC_PLB34I4 0x00020000 /* PLB3X4X MIRQ4 */
#define UIC_PLB34I5 0x00010000 /* PLB3X4X MIRQ5 */
#define UIC_CT0 0x00008000 /* GPT compare timer 0 */
#define UIC_CT1 0x00004000 /* GPT compare timer 1 */
#define UIC_EIR7 0x00002000 /* External interrupt 7 */
#define UIC_EIR8 0x00001000 /* External interrupt 8 */
#define UIC_EIR9 0x00000800 /* External interrupt 9 */
#define UIC_CT2 0x00000400 /* GPT compare timer 2 */
#define UIC_CT3 0x00000200 /* GPT compare timer 3 */
#define UIC_CT4 0x00000100 /* GPT compare timer 4 */
#define UIC_SRE 0x00000080 /* Serial ROM error */
#define UIC_GPTDC 0x00000040 /* GPT decrementer pulse */
#define UIC_RSVD0 0x00000020 /* Reserved */
#define UIC_EPCIPER 0x00000010 /* External PCI PERR */
#define UIC_EIR0 0x00000008 /* External interrupt 0 */
#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
#define UIC_EIR1 0x00000002 /* External interrupt 1 */
#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
/* For compatibility with 405 code */
#define UIC_MAL_SERR UIC_MS
#define UIC_MAL_TXDE UIC_MTDE
#define UIC_MAL_RXDE UIC_MRDE
#define UIC_ENET UIC_ETH0
#elif !defined(CONFIG_440SPE)
#define UIC_MS 0x80000000 /* MAL SERR */
#define UIC_MTDE 0x40000000 /* MAL TXDE */
#define UIC_MRDE 0x20000000 /* MAL RXDE */
#define UIC_DEUE 0x10000000 /* DDR SDRAM ECC uncorrectible error*/
#define UIC_DECE 0x08000000 /* DDR SDRAM correctible error */
#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
#define UIC_EBMI 0x02000000 /* EBMI interrupt status */
#define UIC_OPB 0x01000000 /* OPB to PLB bridge interrupt stat */
#define UIC_MSI3 0x00800000 /* PCI MSI level 3 */
#define UIC_MSI4 0x00400000 /* PCI MSI level 4 */
#define UIC_MSI5 0x00200000 /* PCI MSI level 5 */
#define UIC_MSI6 0x00100000 /* PCI MSI level 6 */
#define UIC_MSI7 0x00080000 /* PCI MSI level 7 */
#define UIC_MSI8 0x00040000 /* PCI MSI level 8 */
#define UIC_MSI9 0x00020000 /* PCI MSI level 9 */
#define UIC_MSI10 0x00010000 /* PCI MSI level 10 */
#define UIC_MSI11 0x00008000 /* PCI MSI level 11 */
#define UIC_PPMI 0x00004000 /* PPM interrupt status */
#define UIC_EIR7 0x00002000 /* External interrupt 7 */
#define UIC_EIR8 0x00001000 /* External interrupt 8 */
#define UIC_EIR9 0x00000800 /* External interrupt 9 */
#define UIC_EIR10 0x00000400 /* External interrupt 10 */
#define UIC_EIR11 0x00000200 /* External interrupt 11 */
#define UIC_EIR12 0x00000100 /* External interrupt 12 */
#define UIC_SRE 0x00000080 /* Serial ROM error */
#define UIC_RSVD2 0x00000040 /* Reserved */
#define UIC_RSVD3 0x00000020 /* Reserved */
#define UIC_PAE 0x00000010 /* PCI asynchronous error */
#define UIC_ETH0 0x00000008 /* Ethernet 0 */
#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
#define UIC_ETH1 0x00000002 /* Ethernet 1 */
#define UIC_EWU1 0x00000001 /* Ethernet 1 wakeup */
#endif /* CONFIG_440SP */
/* For compatibility with 405 code */
#define UIC_MAL_SERR UIC_MS
#define UIC_MAL_TXDE UIC_MTDE
#define UIC_MAL_RXDE UIC_MRDE
#define UIC_ENET UIC_ETH0
/*---------------------------------------------------------------------------+
| Universal interrupt controller 2 interrupts (UIC2)
+---------------------------------------------------------------------------*/
#if defined(CONFIG_440GX)
#define UIC_ETH2 0x80000000 /* Ethernet 2 */
#define UIC_EWU2 0x40000000 /* Ethernet 2 wakeup */
#define UIC_ETH3 0x20000000 /* Ethernet 3 */
#define UIC_EWU3 0x10000000 /* Ethernet 3 wakeup */
#define UIC_TAH0 0x08000000 /* TAH 0 */
#define UIC_TAH1 0x04000000 /* TAH 1 */
#define UIC_IMUOBFQ 0x02000000 /* IMU outbound free queue */
#define UIC_IMUIBPQ 0x01000000 /* IMU inbound post queue */
#define UIC_IMUIRQDB 0x00800000 /* IMU irq doorbell */
#define UIC_IMUIBDB 0x00400000 /* IMU inbound doorbell */
#define UIC_IMUMSG0 0x00200000 /* IMU inbound message 0 */
#define UIC_IMUMSG1 0x00100000 /* IMU inbound message 1 */
#define UIC_IMUTO 0x00080000 /* IMU timeout */
#define UIC_MSI12 0x00040000 /* PCI MSI level 12 */
#define UIC_MSI13 0x00020000 /* PCI MSI level 13 */
#define UIC_MSI14 0x00010000 /* PCI MSI level 14 */
#define UIC_MSI15 0x00008000 /* PCI MSI level 15 */
#define UIC_EIR13 0x00004000 /* External interrupt 13 */
#define UIC_EIR14 0x00002000 /* External interrupt 14 */
#define UIC_EIR15 0x00001000 /* External interrupt 15 */
#define UIC_EIR16 0x00000800 /* External interrupt 16 */
#define UIC_EIR17 0x00000400 /* External interrupt 17 */
#define UIC_PCIVPD 0x00000200 /* PCI VPD */
#define UIC_L2C 0x00000100 /* L2 Cache */
#define UIC_ETH2PCS 0x00000080 /* Ethernet 2 PCS */
#define UIC_ETH3PCS 0x00000040 /* Ethernet 3 PCS */
#define UIC_RSVD26 0x00000020 /* Reserved */
#define UIC_RSVD27 0x00000010 /* Reserved */
#define UIC_RSVD28 0x00000008 /* Reserved */
#define UIC_RSVD29 0x00000004 /* Reserved */
#define UIC_RSVD30 0x00000002 /* Reserved */
#define UIC_RSVD31 0x00000001 /* Reserved */
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
#define UIC_TAH0 0x80000000 /* TAHOE 0 */
#define UIC_TAH1 0x40000000 /* TAHOE 1 */
#define UIC_EIR9 0x20000000 /* External interrupt 9 */
#define UIC_MS 0x10000000 /* MAL SERR */
#define UIC_MTDE 0x08000000 /* MAL TXDE */
#define UIC_MRDE 0x04000000 /* MAL RXDE */
#define UIC_MTE 0x02000000 /* MAL TXEOB */
#define UIC_MRE 0x01000000 /* MAL RXEOB */
#define UIC_MCTX0 0x00800000 /* MAL interrupt coalescence TX0 */
#define UIC_MCTX1 0x00400000 /* MAL interrupt coalescence TX1 */
#define UIC_MCTX2 0x00200000 /* MAL interrupt coalescence TX2 */
#define UIC_MCTX3 0x00100000 /* MAL interrupt coalescence TX3 */
#define UIC_MCTR0 0x00080000 /* MAL interrupt coalescence TR0 */
#define UIC_MCTR1 0x00040000 /* MAL interrupt coalescence TR1 */
#define UIC_MCTR2 0x00020000 /* MAL interrupt coalescence TR2 */
#define UIC_MCTR3 0x00010000 /* MAL interrupt coalescence TR3 */
#define UIC_ETH0 0x00008000 /* Ethernet 0 */
#define UIC_ETH1 0x00004000 /* Ethernet 1 */
#define UIC_ETH2 0x00002000 /* Ethernet 2 */
#define UIC_ETH3 0x00001000 /* Ethernet 3 */
#define UIC_EWU0 0x00000800 /* Ethernet 0 wakeup */
#define UIC_EWU1 0x00000400 /* Ethernet 1 wakeup */
#define UIC_EWU2 0x00000200 /* Ethernet 2 wakeup */
#define UIC_EWU3 0x00000100 /* Ethernet 3 wakeup */
#define UIC_EIR10 0x00000080 /* External interrupt 10 */
#define UIC_EIR11 0x00000040 /* External interrupt 11 */
#define UIC_RSVD2 0x00000020 /* Reserved */
#define UIC_PLB4XAHB 0x00000010 /* PLB4XAHB / AHBARB error */
#define UIC_OTG 0x00000008 /* USB2.0 OTG */
#define UIC_EHCI 0x00000004 /* USB2.0 Host EHCI */
#define UIC_OHCI 0x00000002 /* USB2.0 Host OHCI */
#define UIC_OHCISMI 0x00000001 /* USB2.0 Host OHCI SMI */
#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* UIC2 */
#define UIC_EIR5 0x80000000 /* External interrupt 5 */
#define UIC_EIR6 0x40000000 /* External interrupt 6 */
#define UIC_OPB 0x20000000 /* OPB to PLB bridge interrupt stat */
#define UIC_EIR2 0x10000000 /* External interrupt 2 */
#define UIC_EIR3 0x08000000 /* External interrupt 3 */
#define UIC_DDR2 0x04000000 /* DDR2 sdram */
#define UIC_MCTX0 0x02000000 /* MAl intp coalescence TX0 */
#define UIC_MCTX1 0x01000000 /* MAl intp coalescence TX1 */
#define UIC_MCTR0 0x00800000 /* MAl intp coalescence TR0 */
#define UIC_MCTR1 0x00400000 /* MAl intp coalescence TR1 */
#endif /* CONFIG_440GX */
/*---------------------------------------------------------------------------+
| Universal interrupt controller Base 0 interrupts (UICB0)
+---------------------------------------------------------------------------*/
#if defined(CONFIG_440GX)
#define UICB0_UIC0CI 0x80000000 /* UIC0 Critical Interrupt */
#define UICB0_UIC0NCI 0x40000000 /* UIC0 Noncritical Interrupt */
#define UICB0_UIC1CI 0x20000000 /* UIC1 Critical Interrupt */
#define UICB0_UIC1NCI 0x10000000 /* UIC1 Noncritical Interrupt */
#define UICB0_UIC2CI 0x08000000 /* UIC2 Critical Interrupt */
#define UICB0_UIC2NCI 0x04000000 /* UIC2 Noncritical Interrupt */
#define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \
UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI)
#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
defined(CONFIG_460SX)
#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */
#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */
#define UICB0_UIC2NCI 0x00200000 /* UIC2 Noncritical Interrupt */
#define UICB0_UIC2CI 0x00100000 /* UIC2 Critical Interrupt */
#define UICB0_UIC3NCI 0x00008000 /* UIC3 Noncritical Interrupt */
#define UICB0_UIC3CI 0x00004000 /* UIC3 Critical Interrupt */
#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
#elif defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */
#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */
#define UICB0_UIC2CI 0x00000004 /* UIC2 Critical Interrupt */
#define UICB0_UIC2NCI 0x00000008 /* UIC2 Noncritical Interrupt */
#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | \
UICB0_UIC1CI | UICB0_UIC2NCI)
#elif defined(CONFIG_440GP) || defined(CONFIG_440SP) || \
defined(CONFIG_440EP) || defined(CONFIG_440GR)
#define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */
#define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */
#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI)
#endif /* CONFIG_440GX */
/*---------------------------------------------------------------------------+
| Universal interrupt controller interrupts
+---------------------------------------------------------------------------*/
#if defined(CONFIG_440SPE)
/*#define UICB0_UIC0CI 0x80000000*/ /* UIC0 Critical Interrupt */
/*#define UICB0_UIC0NCI 0x40000000*/ /* UIC0 Noncritical Interrupt */
#define UICB0_UIC1CI 0x00000002 /* UIC1 Critical Interrupt */
#define UICB0_UIC1NCI 0x00000001 /* UIC1 Noncritical Interrupt */
#define UICB0_UIC2CI 0x00200000 /* UIC2 Critical Interrupt */
#define UICB0_UIC2NCI 0x00100000 /* UIC2 Noncritical Interrupt */
#define UICB0_UIC3CI 0x00008000 /* UIC3 Critical Interrupt */
#define UICB0_UIC3NCI 0x00004000 /* UIC3 Noncritical Interrupt */
#define UICB0_ALL (UICB0_UIC1CI | UICB0_UIC1NCI | UICB0_UIC2CI | \
UICB0_UIC2NCI | UICB0_UIC3CI | UICB0_UIC3NCI)
/*---------------------------------------------------------------------------+
| Universal interrupt controller 0 interrupts (UIC0)
+---------------------------------------------------------------------------*/
#define UIC_U0 0x80000000 /* UART 0 */
#define UIC_U1 0x40000000 /* UART 1 */
#define UIC_IIC0 0x20000000 /* IIC */
#define UIC_IIC1 0x10000000 /* IIC */
#define UIC_PIM 0x08000000 /* PCI inbound message */
#define UIC_PCRW 0x04000000 /* PCI command register write */
#define UIC_PPM 0x02000000 /* PCI power management */
#define UIC_PVPDA 0x01000000 /* PCIx 0 vpd access */
#define UIC_MSI0 0x00800000 /* PCIx MSI level 0 */
#define UIC_EIR15 0x00400000 /* External intp 15 */
#define UIC_PEMSI0 0x00080000 /* PCIe MSI level 0 */
#define UIC_PEMSI1 0x00040000 /* PCIe MSI level 1 */
#define UIC_PEMSI2 0x00020000 /* PCIe MSI level 2 */
#define UIC_PEMSI3 0x00010000 /* PCIe MSI level 3 */
#define UIC_EIR14 0x00002000 /* External interrupt 14 */
#define UIC_D0CPFF 0x00001000 /* DMA0 cp fifo full */
#define UIC_D0CSNS 0x00000800 /* DMA0 cs fifo needs service */
#define UIC_D1CPFF 0x00000400 /* DMA1 cp fifo full */
#define UIC_D1CSNS 0x00000200 /* DMA1 cs fifo needs service */
#define UIC_I2OID 0x00000100 /* I2O inbound door bell */
#define UIC_I2OLNE 0x00000080 /* I2O Inbound Post List FIFO Not Empty */
#define UIC_I20R0LL 0x00000040 /* I2O Region 0 Low Latency PLB Write */
#define UIC_I2OR1LL 0x00000020 /* I2O Region 1 Low Latency PLB Write */
#define UIC_I20R0HB 0x00000010 /* I2O Region 0 High Bandwidth PLB Write */
#define UIC_I2OR1HB 0x00000008 /* I2O Region 1 High Bandwidth PLB Write */
#define UIC_CPTCNT 0x00000004 /* GPT Count Timer */
/*---------------------------------------------------------------------------+
| Universal interrupt controller 1 interrupts (UIC1)
+---------------------------------------------------------------------------*/
#define UIC_EIR13 0x80000000 /* externei intp 13 */
#define UIC_MS 0x40000000 /* MAL SERR */
#define UIC_MTDE 0x20000000 /* MAL TXDE */
#define UIC_MRDE 0x10000000 /* MAL RXDE */
#define UIC_DEUE 0x08000000 /* DDR SDRAM ECC correct/uncorrectable error */
#define UIC_EBCO 0x04000000 /* EBCO interrupt status */
#define UIC_MTE 0x02000000 /* MAL TXEOB */
#define UIC_MRE 0x01000000 /* MAL RXEOB */
#define UIC_MSI1 0x00800000 /* PCI MSI level 1 */
#define UIC_MSI2 0x00400000 /* PCI MSI level 2 */
#define UIC_MSI3 0x00200000 /* PCI MSI level 3 */
#define UIC_L2C 0x00100000 /* L2 cache */
#define UIC_CT0 0x00080000 /* GPT compare timer 0 */
#define UIC_CT1 0x00040000 /* GPT compare timer 1 */
#define UIC_CT2 0x00020000 /* GPT compare timer 2 */
#define UIC_CT3 0x00010000 /* GPT compare timer 3 */
#define UIC_CT4 0x00008000 /* GPT compare timer 4 */
#define UIC_EIR12 0x00004000 /* External interrupt 12 */
#define UIC_EIR11 0x00002000 /* External interrupt 11 */
#define UIC_EIR10 0x00001000 /* External interrupt 10 */
#define UIC_EIR9 0x00000800 /* External interrupt 9 */
#define UIC_EIR8 0x00000400 /* External interrupt 8 */
#define UIC_DMAE 0x00000200 /* dma error */
#define UIC_I2OE 0x00000100 /* i2o error */
#define UIC_SRE 0x00000080 /* Serial ROM error */
#define UIC_PCIXAE 0x00000040 /* Pcix0 async error */
#define UIC_EIR7 0x00000020 /* External interrupt 7 */
#define UIC_EIR6 0x00000010 /* External interrupt 6 */
#define UIC_ETH0 0x00000008 /* Ethernet 0 */
#define UIC_EWU0 0x00000004 /* Ethernet 0 wakeup */
#define UIC_ETH1 0x00000002 /* reserved */
#define UIC_XOR 0x00000001 /* xor */
/*---------------------------------------------------------------------------+
| Universal interrupt controller 2 interrupts (UIC2)
+---------------------------------------------------------------------------*/
#define UIC_PEOAL 0x80000000 /* PE0 AL */
#define UIC_PEOVA 0x40000000 /* PE0 VPD access */
#define UIC_PEOHRR 0x20000000 /* PE0 Host reset request rising */
#define UIC_PE0HRF 0x10000000 /* PE0 Host reset request falling */
#define UIC_PE0TCR 0x08000000 /* PE0 TCR */
#define UIC_PE0BVCO 0x04000000 /* PE0 Busmaster VCO */
#define UIC_PE0DCRE 0x02000000 /* PE0 DCR error */
#define UIC_PE1AL 0x00800000 /* PE1 AL */
#define UIC_PE1VA 0x00400000 /* PE1 VPD access */
#define UIC_PE1HRR 0x00200000 /* PE1 Host reset request rising */
#define UIC_PE1HRF 0x00100000 /* PE1 Host reset request falling */
#define UIC_PE1TCR 0x00080000 /* PE1 TCR */
#define UIC_PE1BVCO 0x00040000 /* PE1 Busmaster VCO */
#define UIC_PE1DCRE 0x00020000 /* PE1 DCR error */
#define UIC_PE2AL 0x00008000 /* PE2 AL */
#define UIC_PE2VA 0x00004000 /* PE2 VPD access */
#define UIC_PE2HRR 0x00002000 /* PE2 Host reset request rising */
#define UIC_PE2HRF 0x00001000 /* PE2 Host reset request falling */
#define UIC_PE2TCR 0x00000800 /* PE2 TCR */
#define UIC_PE2BVCO 0x00000400 /* PE2 Busmaster VCO */
#define UIC_PE2DCRE 0x00000200 /* PE2 DCR error */
#define UIC_EIR5 0x00000080 /* External interrupt 5 */
#define UIC_EIR4 0x00000040 /* External interrupt 4 */
#define UIC_EIR3 0x00000020 /* External interrupt 3 */
#define UIC_EIR2 0x00000010 /* External interrupt 2 */
#define UIC_EIR1 0x00000008 /* External interrupt 1 */
#define UIC_EIR0 0x00000004 /* External interrupt 0 */
#endif /* CONFIG_440SPE */
/*-----------------------------------------------------------------------------+ /*-----------------------------------------------------------------------------+
| SDR0 Bit Settings | SDR0 Bit Settings
+-----------------------------------------------------------------------------*/ +-----------------------------------------------------------------------------*/