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sunxi: dram: Optionally use standard JEDEC timings for sun[457]i
In addition to the current Android magic settings, allow to optionally use DDR3 timing parameters, which are tailored for different clock frequencies and JEDEC speed bins. This should improve reliability and performance. Adding '+S:CONFIG_DRAM_TIMINGS_DDR3_1066F_1333H=y' to the board defconfig allows to use timings, which are calculated for the DDR3-1066F speed bin. A lot of DDR3 chips, which are used in real Allwinner based devices, support DDR3-1066F speed bin timings. And adding '+S:CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y' should work with any DDR3 chips, because this targets the slowest JEDEC speed bins. The vendor magic values are still used by default for DRAM, but board maintainers now have more flexibility in DRAM timings selection. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Siarhei Siamashka
Hans de Goede
parent
fb75d972ea
commit
d133647af4
4 changed files with 249 additions and 4 deletions
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@ -55,6 +55,38 @@ config DRAM_EMR1
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default 4 if MACH_SUN5I || MACH_SUN7I
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---help---
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Set the dram controller emr1 value.
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choice
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prompt "sunxi dram timings"
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default DRAM_TIMINGS_VENDOR_MAGIC
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---help---
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Select the timings of the DDR3 chips.
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config DRAM_TIMINGS_VENDOR_MAGIC
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bool "Magic vendor timings from Android"
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---help---
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The same DRAM timings as in the Allwinner boot0 bootloader.
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config DRAM_TIMINGS_DDR3_1066F_1333H
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bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
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---help---
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Use the timings of the standard JEDEC DDR3-1066F speed bin for
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DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
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for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
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used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
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or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
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that down binning to DDR3-1066F is supported (because DDR3-1066F
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uses a bit faster timings than DDR3-1333H).
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config DRAM_TIMINGS_DDR3_800E_1066G_1333J
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bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
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---help---
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Use the timings of the slowest possible JEDEC speed bin for the
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selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
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DDR3-800E, DDR3-1066G or DDR3-1333J.
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endchoice
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endif
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config SYS_CONFIG_NAME
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@ -8,18 +8,22 @@ static struct dram_para dram_para = {
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.density = 0,
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.io_width = 0,
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.bus_width = 0,
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.cas = 6,
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.zq = CONFIG_DRAM_ZQ,
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.odt_en = 0,
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.size = 0,
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#ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC
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.cas = 6,
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.tpr0 = 0x30926692,
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.tpr1 = 0x1090,
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.tpr2 = 0x1a0c8,
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.emr2 = 0,
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#else
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# include "dram_timings_sun4i.h"
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#endif
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.tpr3 = 0,
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.tpr4 = 0,
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.tpr5 = 0,
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.emr1 = CONFIG_DRAM_EMR1,
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.emr2 = 0,
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.emr3 = 0,
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};
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@ -10,18 +10,22 @@ static struct dram_para dram_para = {
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.density = 0,
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.io_width = 0,
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.bus_width = 0,
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.cas = 9,
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.zq = CONFIG_DRAM_ZQ,
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.odt_en = 0,
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.size = 0,
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#ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC
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.cas = 9,
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.tpr0 = 0x42d899b7,
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.tpr1 = 0xa090,
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.tpr2 = 0x22a00,
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.emr2 = 0x10,
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#else
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# include "dram_timings_sun4i.h"
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#endif
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.tpr3 = 0,
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.tpr4 = 0,
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.tpr5 = 0,
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.emr1 = CONFIG_DRAM_EMR1,
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.emr2 = 0x10,
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.emr3 = 0,
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};
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205
board/sunxi/dram_timings_sun4i.h
Normal file
205
board/sunxi/dram_timings_sun4i.h
Normal file
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@ -0,0 +1,205 @@
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/* This file is automatically generated, do not edit */
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#if defined(CONFIG_DRAM_TIMINGS_DDR3_1066F_1333H)
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# if CONFIG_DRAM_CLK <= 360 /* DDR3-1066F @360MHz, timings: 6-5-5-14 */
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.cas = 6,
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.tpr0 = 0x268e5590,
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.tpr1 = 0xa090,
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.tpr2 = 0x22a00,
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.emr2 = 0x0,
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# elif CONFIG_DRAM_CLK <= 384 /* DDR3-1066F @384MHz, timings: 6-6-6-15 */
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.cas = 6,
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.tpr0 = 0x288f6690,
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.tpr1 = 0xa0a0,
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.tpr2 = 0x22a00,
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.emr2 = 0x0,
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# elif CONFIG_DRAM_CLK <= 396 /* DDR3-1066F @396MHz, timings: 6-6-6-15 */
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.cas = 6,
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.tpr0 = 0x2a8f6690,
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.tpr1 = 0xa0a0,
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.tpr2 = 0x22a00,
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.emr2 = 0x0,
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# elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066F @408MHz, timings: 7-6-6-16 */
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.cas = 7,
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.tpr0 = 0x2ab06690,
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.tpr1 = 0xa0a8,
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.tpr2 = 0x22a00,
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.emr2 = 0x8,
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# elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066F @432MHz, timings: 7-6-6-17 */
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.cas = 7,
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.tpr0 = 0x2cb16690,
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.tpr1 = 0xa0b0,
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.tpr2 = 0x22e00,
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.emr2 = 0x8,
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# elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066F @456MHz, timings: 7-6-6-18 */
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.cas = 7,
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.tpr0 = 0x30b26690,
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.tpr1 = 0xa0b8,
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.tpr2 = 0x22e00,
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.emr2 = 0x8,
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# elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066F @468MHz, timings: 7-7-7-18 */
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.cas = 7,
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.tpr0 = 0x30b27790,
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.tpr1 = 0xa0c0,
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.tpr2 = 0x23200,
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.emr2 = 0x8,
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# elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066F @480MHz, timings: 7-7-7-18 */
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.cas = 7,
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.tpr0 = 0x32b27790,
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.tpr1 = 0xa0c0,
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.tpr2 = 0x23200,
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.emr2 = 0x8,
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# elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066F @504MHz, timings: 7-7-7-19 */
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.cas = 7,
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.tpr0 = 0x34d37790,
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.tpr1 = 0xa0d0,
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.tpr2 = 0x23600,
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.emr2 = 0x8,
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# elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066F @528MHz, timings: 7-7-7-20 */
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.cas = 7,
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.tpr0 = 0x36d47790,
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.tpr1 = 0xa0d8,
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.tpr2 = 0x23600,
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.emr2 = 0x8,
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# elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333H @540MHz, timings: 9-8-8-20 */
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.cas = 9,
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.tpr0 = 0x36b488b4,
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.tpr1 = 0xa0c8,
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.tpr2 = 0x2b600,
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.emr2 = 0x10,
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# elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333H @552MHz, timings: 9-8-8-20 */
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.cas = 9,
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.tpr0 = 0x38b488b4,
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.tpr1 = 0xa0c8,
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.tpr2 = 0x2ba00,
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.emr2 = 0x10,
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# elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333H @576MHz, timings: 9-8-8-21 */
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.cas = 9,
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.tpr0 = 0x3ab588b4,
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.tpr1 = 0xa0d0,
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.tpr2 = 0x2ba00,
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.emr2 = 0x10,
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# elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333H @600MHz, timings: 9-9-9-22 */
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.cas = 9,
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.tpr0 = 0x3cb699b4,
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.tpr1 = 0xa0d8,
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.tpr2 = 0x2be00,
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.emr2 = 0x10,
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# elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333H @624MHz, timings: 9-9-9-23 */
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.cas = 9,
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.tpr0 = 0x3eb799b4,
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.tpr1 = 0xa0e8,
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.tpr2 = 0x2be00,
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.emr2 = 0x10,
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# elif CONFIG_DRAM_CLK <= 648 /* DDR3-1333H @648MHz, timings: 9-9-9-24 */
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.cas = 9,
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.tpr0 = 0x42b899b4,
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.tpr1 = 0xa0f0,
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.tpr2 = 0x2c200,
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.emr2 = 0x10,
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# else
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# error CONFIG_DRAM_CLK is set too high
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# endif
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#elif defined(CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J)
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# if CONFIG_DRAM_CLK <= 360 /* DDR3-800E @360MHz, timings: 6-6-6-14 */
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.cas = 6,
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.tpr0 = 0x268e6690,
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.tpr1 = 0xa090,
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.tpr2 = 0x22a00,
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.emr2 = 0x0,
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# elif CONFIG_DRAM_CLK <= 384 /* DDR3-800E @384MHz, timings: 6-6-6-15 */
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.cas = 6,
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.tpr0 = 0x2a8f6690,
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.tpr1 = 0xa0a0,
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.tpr2 = 0x22a00,
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.emr2 = 0x0,
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# elif CONFIG_DRAM_CLK <= 396 /* DDR3-800E @396MHz, timings: 6-6-6-15 */
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.cas = 6,
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.tpr0 = 0x2a8f6690,
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.tpr1 = 0xa0a0,
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.tpr2 = 0x22a00,
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.emr2 = 0x0,
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# elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066G @408MHz, timings: 8-7-7-16 */
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.cas = 8,
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.tpr0 = 0x2cb07790,
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.tpr1 = 0xa0a8,
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.tpr2 = 0x22a00,
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.emr2 = 0x8,
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# elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066G @432MHz, timings: 8-7-7-17 */
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.cas = 8,
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.tpr0 = 0x2eb17790,
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.tpr1 = 0xa0b0,
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.tpr2 = 0x22e00,
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.emr2 = 0x8,
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# elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066G @456MHz, timings: 8-7-7-18 */
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.cas = 8,
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.tpr0 = 0x30b27790,
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.tpr1 = 0xa0b8,
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.tpr2 = 0x22e00,
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.emr2 = 0x8,
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# elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066G @468MHz, timings: 8-8-8-18 */
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.cas = 8,
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.tpr0 = 0x32b28890,
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.tpr1 = 0xa0c0,
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.tpr2 = 0x23200,
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.emr2 = 0x8,
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# elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066G @480MHz, timings: 8-8-8-18 */
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.cas = 8,
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.tpr0 = 0x34b28890,
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.tpr1 = 0xa0c0,
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.tpr2 = 0x23200,
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.emr2 = 0x8,
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# elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066G @504MHz, timings: 8-8-8-19 */
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.cas = 8,
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.tpr0 = 0x36d38890,
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.tpr1 = 0xa0d0,
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.tpr2 = 0x23600,
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.emr2 = 0x8,
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# elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066G @528MHz, timings: 8-8-8-20 */
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.cas = 8,
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.tpr0 = 0x38d48890,
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.tpr1 = 0xa0d8,
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.tpr2 = 0x23600,
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.emr2 = 0x8,
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# elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333J @540MHz, timings: 10-9-9-20 */
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.cas = 10,
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.tpr0 = 0x38b499b4,
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.tpr1 = 0xa0c8,
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.tpr2 = 0x2b600,
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.emr2 = 0x10,
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# elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333J @552MHz, timings: 10-9-9-20 */
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.cas = 10,
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.tpr0 = 0x3ab499b4,
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.tpr1 = 0xa0c8,
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.tpr2 = 0x2ba00,
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.emr2 = 0x10,
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# elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333J @576MHz, timings: 10-9-9-21 */
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.cas = 10,
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.tpr0 = 0x3cb599b4,
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.tpr1 = 0xa0d0,
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.tpr2 = 0x2ba00,
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.emr2 = 0x10,
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# elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333J @600MHz, timings: 10-9-9-22 */
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.cas = 10,
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.tpr0 = 0x3eb699b4,
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.tpr1 = 0xa0d8,
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.tpr2 = 0x2be00,
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.emr2 = 0x10,
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# elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333J @624MHz, timings: 10-10-10-23 */
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.cas = 10,
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.tpr0 = 0x40b7aab4,
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.tpr1 = 0xa0e8,
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.tpr2 = 0x2be00,
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.emr2 = 0x10,
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# elif CONFIG_DRAM_CLK <= 648 /* DDR3-1333J @648MHz, timings: 10-10-10-24 */
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.cas = 10,
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.tpr0 = 0x44b8aab4,
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.tpr1 = 0xa0f0,
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.tpr2 = 0x2c200,
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.emr2 = 0x10,
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# else
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# error CONFIG_DRAM_CLK is set too high
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# endif
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#else
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# error CONFIG_DRAM_TIMINGS_* is not defined
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#endif
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