mirror of
https://github.com/AsahiLinux/u-boot
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imx: add i.MX8QXP MEK board support
Add i.MX8QXP MEK board support Enabled pinctrl/clk/power-domain/mmc/i2c/fec driver. Added README file. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
This commit is contained in:
Peng Fan
Stefano Babic
parent
f180f4a482
commit
d0dd73974c
11 changed files with 819 additions and 0 deletions
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@ -452,6 +452,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
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dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
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dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
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dtb-$(CONFIG_RCAR_GEN3) += \
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r8a7795-h3ulcb.dtb \
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r8a7795-salvator-x.dtb \
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246
arch/arm/dts/fsl-imx8qxp-mek.dts
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246
arch/arm/dts/fsl-imx8qxp-mek.dts
Normal file
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@ -0,0 +1,246 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017-2018 NXP
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*/
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/dts-v1/;
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#include "fsl-imx8qxp.dtsi"
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/ {
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model = "Freescale i.MX8QXP MEK";
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compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
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chosen {
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bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
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stdout-path = &lpuart0;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_usdhc2_vmmc: usdhc2-vmmc {
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compatible = "regulator-fixed";
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regulator-name = "SD1_SPWR";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
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off-on-delay = <3480>;
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enable-active-high;
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};
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx8qxp-mek {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c
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SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
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>;
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};
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pinctrl_ioexp_rst: ioexp-rst-grp {
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fsl,pins = <
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SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048
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SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048
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SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000048
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SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000048
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SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000048
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SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000048
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SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000048
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SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000048
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SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000048
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SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000048
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SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000048
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SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000048
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SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000048
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SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000048
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>;
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};
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pinctrl_fec2: fec2grp {
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fsl,pins = <
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SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x06000048
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SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x06000048
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SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x06000048
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SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x06000048
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SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x06000048
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SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x06000048
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SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x06000048
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SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x06000048
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SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x06000048
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SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x06000048
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SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x06000048
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SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x06000048
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>;
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};
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pinctrl_lpi2c1: lpi2c1grp {
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fsl,pins = <
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SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021
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SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021
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>;
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};
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pinctrl_lpuart0: lpuart0grp {
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fsl,pins = <
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SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
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SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
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>;
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};
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pinctrl_usdhc2_gpio: usdhc2gpiogrp {
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fsl,pins = <
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SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021
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SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021
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SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
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SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
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SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
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SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
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SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
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SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
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SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
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>;
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};
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};
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};
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&A35_0 {
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u-boot,dm-pre-reloc;
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};
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&lpuart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart0>;
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>;
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status = "okay";
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i2cswitch@71 {
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compatible = "nxp,pca9646";
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reg = <0x71>;
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#address-cells = <1>;
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#size-cells = <0>;
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reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
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bb_i2c1: i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0>;
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};
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mfi_i2c1: i2c@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1>;
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};
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i2cexp1_i2c1: i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2>;
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};
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i2cexp2_i2c1: i2c@3 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3>;
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pca9557_a: gpio@1a {
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compatible = "nxp,pca9557";
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reg = <0x1a>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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pca9557_b: gpio@1d {
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compatible = "nxp,pca9557";
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reg = <0x1d>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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};
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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bus-width = <4>;
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cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii";
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phy-handle = <ðphy0>;
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fsl,ar8031-phy-fixup;
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fsl,magic-packet;
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status = "okay";
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phy-reset-gpios = <&pca9557_a 4 GPIO_ACTIVE_LOW>;
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phy-reset-duration = <10>;
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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};
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@ -10,4 +10,17 @@ config IMX8QXP
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config SYS_SOC
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default "imx8"
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choice
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prompt "i.MX8 board select"
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optional
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config TARGET_IMX8QXP_MEK
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bool "Support i.MX8QXP MEK board"
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select BOARD_LATE_INIT
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select IMX8QXP
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endchoice
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source "board/freescale/imx8qxp_mek/Kconfig"
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endif
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14
board/freescale/imx8qxp_mek/Kconfig
Normal file
14
board/freescale/imx8qxp_mek/Kconfig
Normal file
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@ -0,0 +1,14 @@
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if TARGET_IMX8QXP_MEK
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config SYS_BOARD
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default "imx8qxp_mek"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "imx8qxp_mek"
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source "board/freescale/common/Kconfig"
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endif
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6
board/freescale/imx8qxp_mek/MAINTAINERS
Normal file
6
board/freescale/imx8qxp_mek/MAINTAINERS
Normal file
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@ -0,0 +1,6 @@
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i.MX8QXP MEK BOARD
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M: Peng Fan <peng.fan@nxp.com>
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S: Maintained
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F: board/freescale/imx8qxp_mek/
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F: include/configs/imx8qxp_mek.h
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F: configs/imx8qxp_mek_defconfig
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7
board/freescale/imx8qxp_mek/Makefile
Normal file
7
board/freescale/imx8qxp_mek/Makefile
Normal file
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@ -0,0 +1,7 @@
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#
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# Copyright 2017 NXP
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += imx8qxp_mek.o
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72
board/freescale/imx8qxp_mek/README
Normal file
72
board/freescale/imx8qxp_mek/README
Normal file
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@ -0,0 +1,72 @@
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U-Boot for the NXP i.MX8QXP EVK board
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Quick Start
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===========
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- Build U-Boot
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- Build the ARM Trusted firmware binary
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- Get scfw_tcm.bin and ahab-container.img
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- Get mkimage tool
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- Generate flash.bin using imx-mkimage
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- Flash the binary into the SD card
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- Boot
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Build U-Boot
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============
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$ make imx8qxp_mek_defconfig
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$ make
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Get and Build the ARM Trusted firmware
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======================================
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$ git clone https://source.codeaurora.org/external/imx/imx-atf
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$ cd imx-atf/
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$ git checkout origin/imx_4.9.88_imx8qxp_beta2 -b imx_4.9.88_imx8qxp_beta2
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$ make PLAT=imx8qxp bl31
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Get scfw_tcm.bin and ahab-container.img
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==============================
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$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-sc-firmware-0.7.bin
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$ chmod +x imx-sc-firmware-0.7.bin
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$ ./imx-sc-firmware-0.7.bin
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$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.6.bin
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$ chmod +x firmware-imx-7.6.bin
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$ ./firmware-imx-7.6.bin
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Get imx-mkimage tool
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==============================
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Download the imx-mkimage tool:
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$ git clone https://source.codeaurora.org/external/imx/imx-mkimage/
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$ cd imx-mkimage/
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$ git checkout origin/imx_4.9.88_imx8qxp_beta2 -b imx_4.9.88_imx8qxp_beta2
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Generate flash.bin using imx-mkimage
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====================================
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Copy the following binaries to imx-mkimage/iMX8M folder:
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$ cp imx-atf/build/imx8qxp/release/bl31.bin imx-mkimage/iMX8QX/
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$ cp u-boot/u-boot.bin imx-mkimage/iMX8QX/
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Copy the following firmwares to imx-mkimage/iMX8 folder :
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$ cp firmware-imx-7.6/firmware/seco/ahab-container.img imx-mkimage/iMX8QX/
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$ cp imx-sc-firmware-0.7/mx8qx-mek-scfw-tcm.bin imx-mkimage/iMX8QX/scfw_tcm.bin
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$ cd imx-mkimage/
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$ make SOC=iMX8QX flash
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Flash the binary into the SD card
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=================================
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Burn the flash.bin binary to SD card offset 32KB:
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$ sudo dd if=iMX8QX/flash.bin of=/dev/sd[x] bs=1024 seek=32
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Boot
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====
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Set Boot switch SW2: 1100.
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170
board/freescale/imx8qxp_mek/imx8qxp_mek.c
Normal file
170
board/freescale/imx8qxp_mek/imx8qxp_mek.c
Normal file
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@ -0,0 +1,170 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <common.h>
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#include <errno.h>
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#include <linux/libfdt.h>
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#include <environment.h>
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#include <fsl_esdhc.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sci/sci.h>
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#include <asm/arch/imx8-pins.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/sys_proto.h>
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|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
|
||||
(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
|
||||
(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
|
||||
|
||||
static iomux_cfg_t uart0_pads[] = {
|
||||
SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
||||
};
|
||||
|
||||
static void setup_iomux_uart(void)
|
||||
{
|
||||
imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
int ret;
|
||||
/* Set UART0 clock root to 80 MHz */
|
||||
sc_pm_clock_rate_t rate = 80000000;
|
||||
|
||||
/* Power up UART0 */
|
||||
ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Enable UART0 clock root */
|
||||
ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
setup_iomux_uart();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if IS_ENABLED(CONFIG_DM_GPIO)
|
||||
static void board_gpio_init(void)
|
||||
{
|
||||
struct gpio_desc desc;
|
||||
int ret;
|
||||
|
||||
ret = dm_gpio_lookup_name("gpio@1a_3", &desc);
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
ret = dm_gpio_request(&desc, "bb_per_rst_b");
|
||||
if (ret)
|
||||
return;
|
||||
|
||||
dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
|
||||
dm_gpio_set_value(&desc, 0);
|
||||
udelay(50);
|
||||
dm_gpio_set_value(&desc, 1);
|
||||
}
|
||||
#else
|
||||
static inline void board_gpio_init(void) {}
|
||||
#endif
|
||||
|
||||
#if IS_ENABLED(CONFIG_FEC_MXC)
|
||||
#include <miiphy.h>
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
|
||||
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
|
||||
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
|
||||
|
||||
if (phydev->drv->config)
|
||||
phydev->drv->config(phydev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
void build_info(void)
|
||||
{
|
||||
u32 sc_build = 0, sc_commit = 0;
|
||||
|
||||
/* Get SCFW build and commit id */
|
||||
sc_misc_build_info(-1, &sc_build, &sc_commit);
|
||||
if (!sc_build) {
|
||||
printf("SCFW does not support build info\n");
|
||||
sc_commit = 0; /* Display 0 when the build info is not supported*/
|
||||
}
|
||||
printf("Build: SCFW %x\n", sc_commit);
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
puts("Board: iMX8QXP MEK\n");
|
||||
|
||||
build_info();
|
||||
print_bootinfo();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_init(void)
|
||||
{
|
||||
board_gpio_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void detail_board_ddr_info(void)
|
||||
{
|
||||
puts("\nDDR ");
|
||||
}
|
||||
|
||||
/*
|
||||
* Board specific reset that is system reset.
|
||||
*/
|
||||
void reset_cpu(ulong addr)
|
||||
{
|
||||
/* TODO */
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_mmc_get_env_dev(int devno)
|
||||
{
|
||||
return devno;
|
||||
}
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
env_set("board_name", "MEK");
|
||||
env_set("board_rev", "iMX8QXP");
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
81
board/freescale/mx8mq_evk/README
Normal file
81
board/freescale/mx8mq_evk/README
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
U-Boot for the NXP i.MX8MQ EVK board
|
||||
|
||||
Quick Start
|
||||
===========
|
||||
|
||||
- Build U-Boot
|
||||
- Build the ARM Trusted firmware binary
|
||||
- Get DDR firmware and mkimage tool
|
||||
- Generate flash.bin using imx-mkimage
|
||||
- Flash the binary into the SD card
|
||||
- Boot
|
||||
|
||||
Build U-Boot
|
||||
============
|
||||
|
||||
$ make mx8mq_evk_defconfig
|
||||
$ make
|
||||
|
||||
Get and Build the ARM Trusted firmware
|
||||
======================================
|
||||
|
||||
$ git clone https://source.codeaurora.org/external/imx/imx-atf
|
||||
$ cd imx-atf/
|
||||
$ git checkout origin/imx_4.9.51_imx8m_beta
|
||||
$ make PLAT=imx8mq bl31
|
||||
|
||||
Get the DDR firmware and mkimage tool
|
||||
==============================
|
||||
|
||||
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.2.bin
|
||||
$ chmod +x firmware-imx-7.2.bin
|
||||
$ ./firmware-imx-7.2.bin
|
||||
|
||||
Download the imx-mkimage tool:
|
||||
|
||||
$ git clone https://source.codeaurora.org/external/imx/imx-mkimage/
|
||||
$ cd imx-mkimage/
|
||||
$ git checkout origin/imx_4.9.51_imx8m_beta
|
||||
|
||||
|
||||
Generate flash.bin using imx-mkimage
|
||||
====================================
|
||||
|
||||
Copy the following binaries to imx-mkimage/iMX8M folder:
|
||||
|
||||
$ cp imx-atf/build/imx8mq/release/bl31.bin imx-mkimage/iMX8M/
|
||||
$ cp u-boot/u-boot-nodtb.bin imx-mkimage/iMX8M/
|
||||
$ cp u-boot/spl/u-boot-spl.bin imx-mkimage/iMX8M/
|
||||
$ cp u-boot/arch/arm/dts/fsl-imx8mq-evk.dtb imx-mkimage/iMX8M/
|
||||
|
||||
Copy the following firmwares to imx-mkimage/iMX8 folder :
|
||||
|
||||
$ cp firmware-imx-7.2/firmware/ddr/synopsys/lpddr4_pmu_train_1d_dmem.bin imx-mkimage/iMX8M/
|
||||
$ cp firmware-imx-7.2/firmware/ddr/synopsys/lpddr4_pmu_train_1d_imem.bin imx-mkimage/iMX8M/
|
||||
$ cp firmware-imx-7.2/firmware/ddr/synopsys/lpddr4_pmu_train_2d_dmem.bin imx-mkimage/iMX8M/
|
||||
$ cp firmware-imx-7.2/firmware/ddr/synopsys/lpddr4_pmu_train_2d_imem.bin imx-mkimage/iMX8M/
|
||||
|
||||
If you want to run with HDMI, copy signed_hdmi_imx8m.bin to imx-mkimage/iMX8M.
|
||||
|
||||
Before generating the flash.bin, transfer the mkimage generated by U-Boot to iMX8M folder:
|
||||
|
||||
$ cp u-boot/tools/mkimage imx-mkimage/iMX8M/
|
||||
$ mv imx-mkimage/iMX8M/mkimage imx-mkimage/iMX8M/mkimage_uboot
|
||||
|
||||
$ cd imx-mkimage/
|
||||
$ make SOC=iMX8M flash_spl_uboot
|
||||
|
||||
Or for using HDMI:
|
||||
|
||||
$ make SOC=iMX8M flash_hdmi_spl_uboot
|
||||
|
||||
Flash the binary into the SD card
|
||||
=================================
|
||||
|
||||
Burn the flash.bin binary to SD card offset 33KB:
|
||||
|
||||
$ sudo dd if=iMX8M/flash.bin of=/dev/sd[x] bs=1024 seek=33
|
||||
|
||||
Boot
|
||||
====
|
||||
Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
|
||||
51
configs/imx8qxp_mek_defconfig
Normal file
51
configs/imx8qxp_mek_defconfig
Normal file
|
|
@ -0,0 +1,51 @@
|
|||
CONFIG_ARM=y
|
||||
CONFIG_ARCH_IMX8=y
|
||||
CONFIG_SYS_TEXT_BASE=0x80020000
|
||||
CONFIG_SYS_MALLOC_F_LEN=0x2000
|
||||
CONFIG_TARGET_IMX8QXP_MEK=y
|
||||
CONFIG_NR_DRAM_BANKS=3
|
||||
CONFIG_BOOTDELAY=3
|
||||
CONFIG_CMD_CPU=y
|
||||
# CONFIG_CMD_IMPORTENV is not set
|
||||
CONFIG_CMD_CLK=y
|
||||
CONFIG_CMD_DM=y
|
||||
CONFIG_CMD_GPIO=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_CLK_IMX8=y
|
||||
CONFIG_CPU=y
|
||||
CONFIG_DM_GPIO=y
|
||||
CONFIG_MXC_GPIO=y
|
||||
CONFIG_DM_PCA953X=y
|
||||
CONFIG_DM_I2C=y
|
||||
CONFIG_SYS_I2C_IMX_LPI2C=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_I2C_MUX_PCA954x=y
|
||||
CONFIG_MISC=y
|
||||
CONFIG_DM_MMC=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHY_ADDR_ENABLE=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_DM_ETH=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_FEC_MXC_SHARE_MDIO=y
|
||||
CONFIG_FEC_MXC_MDIO_BASE=0x5B040000
|
||||
CONFIG_FEC_MXC=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PINCTRL=y
|
||||
CONFIG_PINCTRL_IMX8=y
|
||||
CONFIG_POWER_DOMAIN=y
|
||||
CONFIG_IMX8_POWER_DOMAIN=y
|
||||
CONFIG_DM_REGULATOR=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_SERIAL=y
|
||||
CONFIG_FSL_LPUART=y
|
||||
# CONFIG_EFI_LOADER is not set
|
||||
157
include/configs/imx8qxp_mek.h
Normal file
157
include/configs/imx8qxp_mek.h
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2018 NXP
|
||||
*/
|
||||
|
||||
#ifndef __IMX8QXP_MEK_H
|
||||
#define __IMX8QXP_MEK_H
|
||||
|
||||
#include <linux/sizes.h>
|
||||
#include <asm/arch/imx-regs.h>
|
||||
|
||||
#define CONFIG_REMAKE_ELF
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F
|
||||
|
||||
/* Flat Device Tree Definitions */
|
||||
#define CONFIG_OF_BOARD_SETUP
|
||||
|
||||
#undef CONFIG_CMD_EXPORTENV
|
||||
#undef CONFIG_CMD_IMPORTENV
|
||||
#undef CONFIG_CMD_IMLS
|
||||
|
||||
#undef CONFIG_CMD_CRC32
|
||||
#undef CONFIG_BOOTM_NETBSD
|
||||
|
||||
#define CONFIG_FSL_ESDHC
|
||||
#define CONFIG_FSL_USDHC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
#define USDHC1_BASE_ADDR 0x5B010000
|
||||
#define USDHC2_BASE_ADDR 0x5B020000
|
||||
#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
||||
|
||||
/* Initial environment variables */
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"script=boot.scr\0" \
|
||||
"image=Image\0" \
|
||||
"panel=NULL\0" \
|
||||
"console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \
|
||||
"fdt_addr=0x83000000\0" \
|
||||
"fdt_high=0xffffffffffffffff\0" \
|
||||
"boot_fdt=try\0" \
|
||||
"fdt_file=fsl-imx8qxp-mek.dtb\0" \
|
||||
"initrd_addr=0x83800000\0" \
|
||||
"initrd_high=0xffffffffffffffff\0" \
|
||||
"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
|
||||
"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
|
||||
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
|
||||
"mmcautodetect=yes\0" \
|
||||
"mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
|
||||
"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
|
||||
"bootscript=echo Running bootscript from mmc ...; " \
|
||||
"source\0" \
|
||||
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
|
||||
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
|
||||
"mmcboot=echo Booting from mmc ...; " \
|
||||
"run mmcargs; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if run loadfdt; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"echo wait for boot; " \
|
||||
"fi;\0" \
|
||||
"netargs=setenv bootargs console=${console} " \
|
||||
"root=/dev/nfs " \
|
||||
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
|
||||
"netboot=echo Booting from net ...; " \
|
||||
"run netargs; " \
|
||||
"if test ${ip_dyn} = yes; then " \
|
||||
"setenv get_cmd dhcp; " \
|
||||
"else " \
|
||||
"setenv get_cmd tftp; " \
|
||||
"fi; " \
|
||||
"${get_cmd} ${loadaddr} ${image}; " \
|
||||
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
|
||||
"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
|
||||
"booti ${loadaddr} - ${fdt_addr}; " \
|
||||
"else " \
|
||||
"echo WARN: Cannot load the DT; " \
|
||||
"fi; " \
|
||||
"else " \
|
||||
"booti; " \
|
||||
"fi;\0"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND \
|
||||
"mmc dev ${mmcdev}; if mmc rescan; then " \
|
||||
"if run loadbootscript; then " \
|
||||
"run bootscript; " \
|
||||
"else " \
|
||||
"if run loadimage; then " \
|
||||
"run mmcboot; " \
|
||||
"else run netboot; " \
|
||||
"fi; " \
|
||||
"fi; " \
|
||||
"else booti ${loadaddr} - ${fdt_addr}; fi"
|
||||
|
||||
/* Link Definitions */
|
||||
#define CONFIG_LOADADDR 0x80280000
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
|
||||
|
||||
#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
|
||||
|
||||
/* Default environment is in SD */
|
||||
#define CONFIG_ENV_SIZE 0x1000
|
||||
#define CONFIG_ENV_OFFSET (64 * SZ_64K)
|
||||
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
|
||||
|
||||
#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
|
||||
|
||||
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
|
||||
#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
|
||||
#define CONFIG_SYS_FSL_USDHC_NUM 2
|
||||
|
||||
/* Size of malloc() pool */
|
||||
#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
|
||||
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x80000000
|
||||
#define PHYS_SDRAM_1 0x80000000
|
||||
#define PHYS_SDRAM_2 0x880000000
|
||||
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
|
||||
/* LPDDR4 board total DDR is 3GB */
|
||||
#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */
|
||||
|
||||
/* Serial */
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
|
||||
/* Monitor Command Prompt */
|
||||
#define CONFIG_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_CBSIZE 2048
|
||||
#define CONFIG_SYS_MAXARGS 64
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
|
||||
sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
/* Generic Timer Definitions */
|
||||
#define COUNTER_FREQUENCY 8000000 /* 8MHz */
|
||||
|
||||
#ifndef CONFIG_DM_PCA953X
|
||||
#define CONFIG_PCA953X
|
||||
#define CONFIG_CMD_PCA953X
|
||||
#define CONFIG_CMD_PCA953X_INFO
|
||||
#endif
|
||||
|
||||
/* Networking */
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
#define FEC_QUIRK_ENET_MAC
|
||||
|
||||
#endif /* __IMX8QXP_MEK_H */
|
||||
Loading…
Reference in a new issue