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SMDK2410: various cleanup/code style fixes

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Signed-off-by: David Müller <d.mueller@elsoft.ch>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
David Müller (ELSOFT AG) 2011-03-24 22:28:06 +00:00 committed by Minkyu Kang
parent a5ec7f6494
commit d0b375f647
2 changed files with 133 additions and 69 deletions
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61
board/samsung/smdk2410/smdk2410.c
View file

@ -3,7 +3,7 @@
* Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de> * Marius Groeger <mgroeger@sysgo.de>
* *
* (C) Copyright 2002 * (C) Copyright 2002, 2010
* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch> * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
* *
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
@ -27,6 +27,7 @@
#include <common.h> #include <common.h>
#include <netdev.h> #include <netdev.h>
#include <asm/io.h>
#include <asm/arch/s3c24x0_cpu.h> #include <asm/arch/s3c24x0_cpu.h>
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
@ -55,7 +56,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define U_M_SDIV 0x2 #define U_M_SDIV 0x2
#endif #endif
static inline void delay (unsigned long loops) static inline void pll_delay(unsigned long loops)
{ {
__asm__ volatile ("1:\n" __asm__ volatile ("1:\n"
"subs %0, %1, #1\n" "subs %0, %1, #1\n"
@ -66,44 +67,51 @@ static inline void delay (unsigned long loops)
* Miscellaneous platform dependent initialisations * Miscellaneous platform dependent initialisations
*/ */
int board_init (void) int board_early_init_f(void)
{ {
struct s3c24x0_clock_power * const clk_power = struct s3c24x0_clock_power * const clk_power =
s3c24x0_get_base_clock_power(); s3c24x0_get_base_clock_power();
struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */ /* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->locktime = 0xFFFFFF; writel(0xFFFFFF, &clk_power->locktime);
/* configure MPLL */ /* configure MPLL */
clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,
&clk_power->mpllcon);
/* some delay between MPLL and UPLL */ /* some delay between MPLL and UPLL */
delay (4000); pll_delay(4000);
/* configure UPLL */ /* configure UPLL */
clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
&clk_power->upllcon);
/* some delay between MPLL and UPLL */ /* some delay between MPLL and UPLL */
delay (8000); pll_delay(8000);
/* set up the I/O ports */ /* set up the I/O ports */
gpio->gpacon = 0x007FFFFF; writel(0x007FFFFF, &gpio->gpacon);
gpio->gpbcon = 0x00044555; writel(0x00044555, &gpio->gpbcon);
gpio->gpbup = 0x000007FF; writel(0x000007FF, &gpio->gpbup);
gpio->gpccon = 0xAAAAAAAA; writel(0xAAAAAAAA, &gpio->gpccon);
gpio->gpcup = 0x0000FFFF; writel(0x0000FFFF, &gpio->gpcup);
gpio->gpdcon = 0xAAAAAAAA; writel(0xAAAAAAAA, &gpio->gpdcon);
gpio->gpdup = 0x0000FFFF; writel(0x0000FFFF, &gpio->gpdup);
gpio->gpecon = 0xAAAAAAAA; writel(0xAAAAAAAA, &gpio->gpecon);
gpio->gpeup = 0x0000FFFF; writel(0x0000FFFF, &gpio->gpeup);
gpio->gpfcon = 0x000055AA; writel(0x000055AA, &gpio->gpfcon);
gpio->gpfup = 0x000000FF; writel(0x000000FF, &gpio->gpfup);
gpio->gpgcon = 0xFF95FFBA; writel(0xFF95FFBA, &gpio->gpgcon);
gpio->gpgup = 0x0000FFFF; writel(0x0000FFFF, &gpio->gpgup);
gpio->gphcon = 0x002AFAAA; writel(0x002AFAAA, &gpio->gphcon);
gpio->gphup = 0x000007FF; writel(0x000007FF, &gpio->gphup);
return 0;
}
int board_init(void)
{
/* arch number of SMDK2410-Board */ /* arch number of SMDK2410-Board */
gd->bd->bi_arch_number = MACH_TYPE_SMDK2410; gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
@ -116,11 +124,10 @@ int board_init (void)
return 0; return 0;
} }
int dram_init (void) int dram_init(void)
{ {
gd->bd->bi_dram[0].start = PHYS_SDRAM_1; /* dram_init must store complete ramsize in gd->ram_size */
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; gd->ram_size = PHYS_SDRAM_1_SIZE;
return 0; return 0;
} }

141
include/configs/smdk2410.h
View file

@ -33,24 +33,23 @@
* High Level Configuration Options * High Level Configuration Options
* (easy to change) * (easy to change)
*/ */
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ #define CONFIG_ARM920T /* This is an ARM920T Core */
#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ #define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */
#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ #define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */
#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */ #define CONFIG_SMDK2410 /* on a SAMSUNG SMDK2410 Board */
#define CONFIG_SYS_TEXT_BASE 0x0 #define CONFIG_SYS_TEXT_BASE 0x0
/* input clock of PLL */ #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */
/* input clock of PLL (the SMDK2410 has 12MHz input clock) */
#define CONFIG_SYS_CLK_FREQ 12000000
#define USE_920T_MMU 1 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
/* #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
* Size of malloc() pool #define CONFIG_SETUP_MEMORY_TAGS
*/ #define CONFIG_INITRD_TAG
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
/* /*
* Hardware drivers * Hardware drivers
@ -64,19 +63,24 @@
* select serial console configuration * select serial console configuration
*/ */
#define CONFIG_S3C24X0_SERIAL #define CONFIG_S3C24X0_SERIAL
#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */ #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */
/************************************************************
* USB support (currently only works with D-cache off)
************************************************************/
#define CONFIG_USB_OHCI
#define CONFIG_USB_KEYBOARD
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
/************************************************************ /************************************************************
* RTC * RTC
************************************************************/ ************************************************************/
#define CONFIG_RTC_S3C24X0 1 #define CONFIG_RTC_S3C24X0
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200 #define CONFIG_BAUDRATE 115200
/* /*
* BOOTP options * BOOTP options
*/ */
@ -85,52 +89,71 @@
#define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME #define CONFIG_BOOTP_HOSTNAME
/* /*
* Command line configuration. * Command line configuration.
*/ */
#include <config_cmd_default.h> #include <config_cmd_default.h>
#define CONFIG_CMD_BSP
#define CONFIG_CMD_CACHE #define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE #define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF #define CONFIG_CMD_ELF
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_USB
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#define CONFIG_CMDLINE_EDITING
#define CONFIG_BOOTDELAY 3 /* autoboot */
/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ #define CONFIG_BOOTDELAY 5
/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */ #define CONFIG_BOOT_RETRY_TIME -1
#define CONFIG_NETMASK 255.255.255.0 #define CONFIG_RESET_TO_RETRY
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 10.0.0.110 #define CONFIG_IPADDR 10.0.0.110
#define CONFIG_SERVERIP 10.0.0.1 #define CONFIG_SERVERIP 10.0.0.1
/*#define CONFIG_BOOTFILE "elinos-lart" */
/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
#if defined(CONFIG_CMD_KGDB) #if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
/* what's this ? it's not used anywhere */ /* what's this ? it's not used anywhere */
#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif #endif
/* /*
* Miscellaneous configurable options * Miscellaneous configurable options
*/ */
#define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LONGHELP /* undef to save memory */
#define CONFIG_SYS_PROMPT "SMDK2410 # " /* Monitor Command Prompt */ #define CONFIG_SYS_PROMPT "SMDK2410 # "
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 256
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ /* may be activated as soon as s3c24x0 has print_cpuinfo support */
#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ /*#define CONFIG_DISPLAY_CPUINFO*/ /* Display cpu info */
#define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */ #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_LOAD_ADDR 0x30800000
#define CONFIG_SYS_HZ 1000
/* valid baudrates */ /* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/* support additional compression methods */
#define CONFIG_BZIP2
#define CONFIG_LZO
#define CONFIG_LZMA
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Stack sizes * Stack sizes
* *
@ -145,11 +168,11 @@
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Physical Memory Map * Physical Memory Map
*/ */
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #0 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
@ -164,19 +187,53 @@
#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_MAX_FLASH_SECT (19) #define CONFIG_SYS_MAX_FLASH_SECT (19)
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000)
#define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000)
#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ #define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE 0x10000
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
/*
* Size of malloc() pool
* BZIP2 / LZO / LZMA need a lot of RAM
*/
#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_LEN (448 * 1024) #define CONFIG_SYS_MONITOR_LEN (448 * 1024)
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
/*
* NAND configuration
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_S3C2410
#define CONFIG_SYS_S3C2410_NAND_HWECC
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0x4E000000
#endif
/*
* File system
*/
#define CONFIG_CMD_FAT
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS
#define CONFIG_YAFFS2
#define CONFIG_RBTREE
/* additions for new relocation code, must be added to all boards */ /* additions for new relocation code, must be added to all boards */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
GENERATED_GBL_DATA_SIZE) GENERATED_GBL_DATA_SIZE)
#define CONFIG_BOARD_EARLY_INIT_F
#endif /* __CONFIG_H */ #endif /* __CONFIG_H */