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https://github.com/AsahiLinux/u-boot
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SMDK2410: various cleanup/code style fixes
Signed-off-by: David Müller <d.mueller@elsoft.ch> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
David Müller (ELSOFT AG)
Minkyu Kang
parent
a5ec7f6494
commit
d0b375f647
2 changed files with 133 additions and 69 deletions
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@ -3,7 +3,7 @@
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* (C) Copyright 2002, 2010
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* David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
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*
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* See file CREDITS for list of people who contributed to this
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@ -27,6 +27,7 @@
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/arch/s3c24x0_cpu.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -55,7 +56,7 @@ DECLARE_GLOBAL_DATA_PTR;
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#define U_M_SDIV 0x2
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#endif
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static inline void delay (unsigned long loops)
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static inline void pll_delay(unsigned long loops)
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{
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__asm__ volatile ("1:\n"
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"subs %0, %1, #1\n"
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@ -66,44 +67,51 @@ static inline void delay (unsigned long loops)
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* Miscellaneous platform dependent initialisations
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*/
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int board_init (void)
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int board_early_init_f(void)
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{
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struct s3c24x0_clock_power * const clk_power =
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s3c24x0_get_base_clock_power();
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struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
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/* to reduce PLL lock time, adjust the LOCKTIME register */
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clk_power->locktime = 0xFFFFFF;
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writel(0xFFFFFF, &clk_power->locktime);
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/* configure MPLL */
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clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
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writel((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV,
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&clk_power->mpllcon);
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/* some delay between MPLL and UPLL */
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delay (4000);
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pll_delay(4000);
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/* configure UPLL */
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clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
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writel((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV,
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&clk_power->upllcon);
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/* some delay between MPLL and UPLL */
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delay (8000);
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pll_delay(8000);
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/* set up the I/O ports */
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gpio->gpacon = 0x007FFFFF;
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gpio->gpbcon = 0x00044555;
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gpio->gpbup = 0x000007FF;
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gpio->gpccon = 0xAAAAAAAA;
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gpio->gpcup = 0x0000FFFF;
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gpio->gpdcon = 0xAAAAAAAA;
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gpio->gpdup = 0x0000FFFF;
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gpio->gpecon = 0xAAAAAAAA;
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gpio->gpeup = 0x0000FFFF;
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gpio->gpfcon = 0x000055AA;
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gpio->gpfup = 0x000000FF;
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gpio->gpgcon = 0xFF95FFBA;
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gpio->gpgup = 0x0000FFFF;
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gpio->gphcon = 0x002AFAAA;
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gpio->gphup = 0x000007FF;
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writel(0x007FFFFF, &gpio->gpacon);
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writel(0x00044555, &gpio->gpbcon);
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writel(0x000007FF, &gpio->gpbup);
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writel(0xAAAAAAAA, &gpio->gpccon);
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writel(0x0000FFFF, &gpio->gpcup);
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writel(0xAAAAAAAA, &gpio->gpdcon);
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writel(0x0000FFFF, &gpio->gpdup);
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writel(0xAAAAAAAA, &gpio->gpecon);
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writel(0x0000FFFF, &gpio->gpeup);
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writel(0x000055AA, &gpio->gpfcon);
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writel(0x000000FF, &gpio->gpfup);
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writel(0xFF95FFBA, &gpio->gpgcon);
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writel(0x0000FFFF, &gpio->gpgup);
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writel(0x002AFAAA, &gpio->gphcon);
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writel(0x000007FF, &gpio->gphup);
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return 0;
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}
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int board_init(void)
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{
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/* arch number of SMDK2410-Board */
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gd->bd->bi_arch_number = MACH_TYPE_SMDK2410;
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@ -116,11 +124,10 @@ int board_init (void)
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return 0;
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}
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int dram_init (void)
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int dram_init(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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@ -33,24 +33,23 @@
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
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#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
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#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
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#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
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#define CONFIG_ARM920T /* This is an ARM920T Core */
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#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */
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#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */
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#define CONFIG_SMDK2410 /* on a SAMSUNG SMDK2410 Board */
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#define CONFIG_SYS_TEXT_BASE 0x0
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/* input clock of PLL */
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#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */
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#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
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/* input clock of PLL (the SMDK2410 has 12MHz input clock) */
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#define CONFIG_SYS_CLK_FREQ 12000000
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#define USE_920T_MMU 1
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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/*
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* Hardware drivers
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@ -64,19 +63,24 @@
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* select serial console configuration
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*/
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#define CONFIG_S3C24X0_SERIAL
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#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */
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#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */
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/************************************************************
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* USB support (currently only works with D-cache off)
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************************************************************/
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#define CONFIG_USB_OHCI
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#define CONFIG_USB_KEYBOARD
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#define CONFIG_USB_STORAGE
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#define CONFIG_DOS_PARTITION
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/************************************************************
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* RTC
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************************************************************/
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#define CONFIG_RTC_S3C24X0 1
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#define CONFIG_RTC_S3C24X0
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_BAUDRATE 115200
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/*
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* BOOTP options
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*/
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@ -85,52 +89,71 @@
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BSP
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_USB
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_BOOTDELAY 3
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/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
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/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */
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#define CONFIG_NETMASK 255.255.255.0
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/* autoboot */
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_BOOT_RETRY_TIME -1
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#define CONFIG_RESET_TO_RETRY
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#define CONFIG_ZERO_BOOTDELAY_CHECK
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_IPADDR 10.0.0.110
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#define CONFIG_SERVERIP 10.0.0.1
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/*#define CONFIG_BOOTFILE "elinos-lart" */
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/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
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#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
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/* what's this ? it's not used anywhere */
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#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
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#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "SMDK2410 # " /* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_SYS_LONGHELP /* undef to save memory */
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#define CONFIG_SYS_PROMPT "SMDK2410 # "
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#define CONFIG_SYS_CBSIZE 256
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/* Print Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
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/* may be activated as soon as s3c24x0 has print_cpuinfo support */
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/*#define CONFIG_DISPLAY_CPUINFO*/ /* Display cpu info */
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#define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */
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#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
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#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_SYS_LOAD_ADDR 0x30800000
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#define CONFIG_SYS_HZ 1000
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/* valid baudrates */
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* support additional compression methods */
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#define CONFIG_BZIP2
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#define CONFIG_LZO
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#define CONFIG_LZMA
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/*-----------------------------------------------------------------------
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* Stack sizes
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*
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@ -145,11 +168,11 @@
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
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#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
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#define PHYS_FLASH_1 0x00000000 /* Flash Bank #0 */
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#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
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@ -164,19 +187,53 @@
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#define CONFIG_FLASH_SHOW_PROGRESS 45
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_MAX_FLASH_SECT (19)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000)
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000)
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_SIZE 0x10000
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/*
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* Size of malloc() pool
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* BZIP2 / LZO / LZMA need a lot of RAM
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*/
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#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
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#define CONFIG_SYS_MONITOR_LEN (448 * 1024)
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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/*
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* NAND configuration
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*/
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_NAND_S3C2410
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#define CONFIG_SYS_S3C2410_NAND_HWECC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define NAND_MAX_CHIPS 1
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#define CONFIG_SYS_NAND_BASE 0x4E000000
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#endif
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/*
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* File system
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*/
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_UBI
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#define CONFIG_CMD_UBIFS
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_DEVICE
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_YAFFS2
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#define CONFIG_RBTREE
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/* additions for new relocation code, must be added to all boards */
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
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GENERATED_GBL_DATA_SIZE)
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#define CONFIG_BOARD_EARLY_INIT_F
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#endif /* __CONFIG_H */
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#endif /* __CONFIG_H */
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