Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-29 08:01:08 +00:00
Code Issues Projects Releases Packages Wiki Activity

clk: stm32f7: retrieve PWR base address from DT

Browse source 
PWR IP is used to enable over-drive feature in
order to reach a higher frequency.
Get its base address from DT instead of hard-coded value

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
This commit is contained in:
Patrice Chotard 2017-11-15 13:14:44 +01:00 committed by Tom Rini
parent d3651aac46
commit d0a768b1c8
4 changed files with 69 additions and 18 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

23
arch/arm/include/asm/arch-stm32f4/stm32_pwr.h Normal file
View file

@ -0,0 +1,23 @@
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __STM32_PWR_H_
/*
* Offsets of some PWR registers
*/
#define PWR_CR1_ODEN BIT(16)
#define PWR_CR1_ODSWEN BIT(17)
#define PWR_CSR1_ODRDY BIT(16)
#define PWR_CSR1_ODSWRDY BIT(17)
struct stm32_pwr_regs {
u32 cr1; /* power control register 1 */
u32 csr1; /* power control/status register 2 */
};
#endif /* __STM32_PWR_H_ */

7
arch/arm/include/asm/arch-stm32f7/stm32.h
View file

@ -95,13 +95,6 @@ struct stm32_rcc_regs {
};
#define STM32_RCC ((struct stm32_rcc_regs *)RCC_BASE)
struct stm32_pwr_regs {
u32 cr1; /* power control register 1 */
u32 csr1; /* power control/status register 2 */
u32 cr2; /* power control register 2 */
u32 csr2; /* power control/status register 2 */
};
#define STM32_PWR ((struct stm32_pwr_regs *)PWR_BASE)
void stm32_flash_latency_cfg(int latency);

25
arch/arm/include/asm/arch-stm32f7/stm32_pwr.h Normal file
View file

@ -0,0 +1,25 @@
/*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __STM32_PWR_H_
/*
* Offsets of some PWR registers
*/
#define PWR_CR1_ODEN BIT(16)
#define PWR_CR1_ODSWEN BIT(17)
#define PWR_CSR1_ODRDY BIT(16)
#define PWR_CSR1_ODSWRDY BIT(17)
struct stm32_pwr_regs {
u32 cr1; /* power control register 1 */
u32 csr1; /* power control/status register 2 */
u32 cr2; /* power control register 2 */
u32 csr2; /* power control/status register 2 */
};
#endif /* __STM32_PWR_H_ */

32
drivers/clk/clk_stm32f7.c
View file

@ -8,10 +8,12 @@
#include <common.h>
#include <clk-uclass.h>
#include <dm.h>
#include <asm/io.h>
#include <asm/arch/rcc.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>
#include <asm/arch/stm32_pwr.h>
#include <dt-bindings/mfd/stm32f7-rcc.h>
@ -52,13 +54,6 @@
#define RCC_CFGR_PPRE1_SHIFT 10
#define RCC_CFGR_PPRE2_SHIFT 13
/*
* Offsets of some PWR registers
*/
#define PWR_CR1_ODEN BIT(16)
#define PWR_CR1_ODSWEN BIT(17)
#define PWR_CSR1_ODRDY BIT(16)
#define PWR_CSR1_ODSWRDY BIT(17)
struct pll_psc {
u8 pll_m;
@ -88,6 +83,7 @@ struct pll_psc {
struct stm32_clk {
struct stm32_rcc_regs *base;
struct stm32_pwr_regs *pwr_regs;
};
#if !defined(CONFIG_STM32_HSE_HZ)
@ -115,6 +111,7 @@ static int configure_clocks(struct udevice *dev)
{
struct stm32_clk *priv = dev_get_priv(dev);
struct stm32_rcc_regs *regs = priv->base;
struct stm32_pwr_regs *pwr = priv->pwr_regs;
/* Reset RCC configuration */
setbits_le32(&regs->cr, RCC_CR_HSION);
@ -153,14 +150,14 @@ static int configure_clocks(struct udevice *dev)
/* Enable high performance mode, System frequency up to 200 MHz */
setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);
setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
/* Infinite wait! */
while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
;
/* Enable the Over-drive switch */
setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
/* Infinite wait! */
while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
;
stm32_flash_latency_cfg(5);
@ -268,6 +265,9 @@ void clock_setup(int peripheral)
static int stm32_clk_probe(struct udevice *dev)
{
struct ofnode_phandle_args args;
int err;
debug("%s: stm32_clk_probe\n", __func__);
struct stm32_clk *priv = dev_get_priv(dev);
@ -279,6 +279,16 @@ static int stm32_clk_probe(struct udevice *dev)
priv->base = (struct stm32_rcc_regs *)addr;
err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
&args);
if (err) {
debug("%s: can't find syscon device (%d)\n", __func__,
err);
return err;
}
priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
configure_clocks(dev);
return 0;