Convert CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS et al to Kconfig

This converts the following to Kconfig:
   CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
   CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS

And we remove the entries from the README for a number of already
converted items.

Signed-off-by: Tom Rini <trini@konsulko.com>

README

@@ -363,68 +363,17 @@ The following options need to be configured:
 		CONFIG_SYS_FSL_DDR_ADDR
 		Freescale DDR memory-mapped register base.
 
-		CONFIG_SYS_FSL_DDRC_GEN1
-		Freescale DDR1 controller.
-
-		CONFIG_SYS_FSL_DDRC_GEN2
-		Freescale DDR2 controller.
-
-		CONFIG_SYS_FSL_DDRC_GEN3
-		Freescale DDR3 controller.
-
-		CONFIG_SYS_FSL_DDRC_GEN4
-		Freescale DDR4 controller.
-
-		CONFIG_SYS_FSL_DDRC_ARM_GEN3
-		Freescale DDR3 controller for ARM-based SoCs.
-
-		CONFIG_SYS_FSL_DDR1
-		Board config to use DDR1. It can be enabled for SoCs with
-		Freescale DDR1 or DDR2 controllers, depending on the board
-		implemetation.
-
-		CONFIG_SYS_FSL_DDR2
-		Board config to use DDR2. It can be enabled for SoCs with
-		Freescale DDR2 or DDR3 controllers, depending on the board
-		implementation.
-
-		CONFIG_SYS_FSL_DDR3
-		Board config to use DDR3. It can be enabled for SoCs with
-		Freescale DDR3 or DDR3L controllers.
-
-		CONFIG_SYS_FSL_DDR3L
-		Board config to use DDR3L. It can be enabled for SoCs with
-		DDR3L controllers.
-
 		CONFIG_SYS_FSL_IFC_CLK_DIV
 		Defines divider of platform clock(clock input to IFC controller).
 
 		CONFIG_SYS_FSL_LBC_CLK_DIV
 		Defines divider of platform clock(clock input to eLBC controller).
 
-		CONFIG_SYS_FSL_DDR_BE
-		Defines the DDR controller register space as Big Endian
-
-		CONFIG_SYS_FSL_DDR_LE
-		Defines the DDR controller register space as Little Endian
-
 		CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
 		Physical address from the view of DDR controllers. It is the
 		same as CONFIG_SYS_DDR_SDRAM_BASE for  all Power SoCs. But
 		it could be different for ARM SoCs.
 
-		CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
-		Number of controllers used as main memory.
-
-		CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
-		Number of controllers used for other than main memory.
-
-		CONFIG_SYS_FSL_SEC_BE
-		Defines the SEC controller register space as Big Endian
-
-		CONFIG_SYS_FSL_SEC_LE
-		Defines the SEC controller register space as Little Endian
-
 - MIPS CPU options:
 		CONFIG_XWAY_SWAP_BYTES
 

arch/arm/cpu/armv8/fsl-layerscape/Kconfig

@@ -193,6 +193,7 @@ config ARCH_LS2080A
 	select FSL_IFC
 	select FSL_LAYERSCAPE
 	select FSL_LSCH3
+	select SYS_FSL_OTHER_DDR_NUM_CTRLS
 	select GICV3
 	select SKIP_LOWLEVEL_INIT
 	select SYS_FSL_SRDS_1

configs/ls2080aqds_SECURE_BOOT_defconfig

@@ -54,6 +54,7 @@ CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

configs/ls2080aqds_defconfig

@@ -57,6 +57,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

configs/ls2080aqds_nand_defconfig

@@ -77,6 +77,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

configs/ls2080aqds_qspi_defconfig

@@ -58,6 +58,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

configs/ls2080aqds_sdcard_defconfig

@@ -72,6 +72,7 @@ CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

configs/ls2080ardb_SECURE_BOOT_defconfig

@@ -58,6 +58,7 @@ CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

configs/ls2080ardb_defconfig

@@ -61,6 +61,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

configs/ls2080ardb_nand_defconfig

@@ -81,6 +81,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

configs/ls2081ardb_defconfig

@@ -59,6 +59,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

configs/ls2088aqds_tfa_defconfig

@@ -64,6 +64,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DYNAMIC_DDR_CLK_FREQ=y
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

configs/ls2088ardb_qspi_SECURE_BOOT_defconfig

@@ -54,6 +54,7 @@ CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

configs/ls2088ardb_qspi_defconfig

@@ -61,6 +61,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

configs/ls2088ardb_tfa_SECURE_BOOT_defconfig

@@ -59,6 +59,7 @@ CONFIG_SATA=y
 CONFIG_SATA_CEVA=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

configs/ls2088ardb_tfa_defconfig

@@ -66,6 +66,7 @@ CONFIG_SATA_CEVA=y
 CONFIG_FSL_CAAM=y
 CONFIG_DDR_CLK_FREQ=133333333
 CONFIG_DIMM_SLOTS_PER_CTLR=2
+CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS=2
 CONFIG_DDR_ECC=y
 CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
 CONFIG_SYS_FSL_DDR_INTLV_256B=y

drivers/ddr/fsl/Kconfig

@@ -40,6 +40,9 @@ config FSL_DDR_SYNC_REFRESH
 config FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 	bool
 
+config SYS_FSL_OTHER_DDR_NUM_CTRLS
+	bool
+
 menu "Freescale DDR controllers"
 	depends on SYS_FSL_DDR
 
@@ -63,6 +66,10 @@ config DIMM_SLOTS_PER_CTLR
 	int "Number of DIMM slots per controller"
 	default 1
 
+config SYS_FSL_DDR_MAIN_NUM_CTRLS
+	int "Number of controllers used as main memory"
+	default SYS_NUM_DDR_CTLRS
+
 config SYS_FSL_DDR_VER
 	int
 	default 50 if SYS_FSL_DDR_VER_50

include/configs/kontron_sl28.h

@@ -23,7 +23,6 @@
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_DDR_BLOCK2_BASE	0x2080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	1
 
 /* early stack pointer */
 

include/configs/ls1028a_common.h

@@ -17,7 +17,6 @@
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_DDR_BLOCK2_BASE	0x2080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	1
 
 /*
  * SMP Definitinos

include/configs/ls1088a_common.h

@@ -34,7 +34,6 @@
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	1
 /*
  * SMP Definitinos
  */

include/configs/ls2080a_common.h

@@ -21,15 +21,12 @@
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_DDR_BLOCK2_BASE	0x8080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2
 
 /*
  * SMP Definitinos
  */
 #define CPU_RELEASE_ADDR		secondary_boot_addr
 
-#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
-
 /*
  * This is not an accurate number. It is used in start.S. The frequency
  * will be udpated later when get_bus_freq(0) is available.

include/configs/lx2160a_common.h

@@ -17,7 +17,6 @@
 #define CONFIG_SYS_DDR_SDRAM_BASE		0x80000000UL
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
 #define CONFIG_SYS_DDR_BLOCK2_BASE		0x2080000000ULL
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	2
 #define CONFIG_SYS_SDRAM_SIZE			0x200000000UL
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef

include/fsl_ddr.h

@@ -14,11 +14,6 @@
 
 struct cmd_tbl;
 
-#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
-/* All controllers are for main memory */
-#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS	CONFIG_SYS_NUM_DDR_CTLRS
-#endif
-
 #ifdef CONFIG_SYS_FSL_DDR_LE
 #define ddr_in32(a)	in_le32(a)
 #define ddr_out32(a, v)	out_le32(a, v)