mirror of
https://github.com/AsahiLinux/u-boot
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8xx, mgsuvd: rename board to a more generic name
renaming the "mgsuvd" board port into "km8xx", because there come more similar boards from keymile. Compiling the mgsuvd board with "make mgsuvd_config" remains. Signed-off-by: Heiko Schocher <hs@denx.de>
This commit is contained in:
Heiko Schocher
Wolfgang Denk
parent
18b2f35bde
commit
d044954fe2
11 changed files with 327 additions and 291 deletions
2
Makefile
2
Makefile
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@ -938,7 +938,7 @@ MBX860T_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc8xx mbx8xx
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mgsuvd_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc8xx mgsuvd keymile
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@$(MKCONFIG) $(@:_config=) ppc mpc8xx km8xx keymile
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MHPC_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc8xx mhpc eltec
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@ -390,7 +390,7 @@ static void setports (int gpio)
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#endif
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#endif
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#if defined(CONFIG_MGSUVD)
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#if defined(CONFIG_KM8XX)
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static void set_sda (int state)
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{
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I2C_SDA(state);
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@ -25,7 +25,7 @@
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#define _KEYMILE_HDLC_ENET_H_
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/* Unfortuantely, we have do this to get the flag defines in the cbd_t */
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#ifdef CONFIG_MGSUVD
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#ifdef CONFIG_KM8XX
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#include <commproc.h>
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#endif
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#ifdef CONFIG_MGCOGE
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@ -29,7 +29,7 @@ endif
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LIB = $(obj)lib$(BOARD).a
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COBJS = $(BOARD).o ../common/common.o ../common/keymile_hdlc_enet.o \
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mgsuvd_hdlc_enet.o
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km8xx_hdlc_enet.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -1122,11 +1122,11 @@ typedef struct scc_enet {
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#define SICR_ENET_CLKRT ((uint)0x0000003d)
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#endif /* CONFIG_MBX */
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/*** MGSUVD *********************************************************/
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/*** KM8XX *********************************************************/
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/* The MGSUVD Service Module uses SCC3 for Ethernet */
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/* The KM8XX Service Module uses SCC3 for Ethernet */
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#ifdef CONFIG_MGSUVD
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#ifdef CONFIG_KM8XX
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#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */
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#define CPM_CR_ENET CPM_CR_CH_SCC3
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#define SCC_ENET 2
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@ -1145,7 +1145,7 @@ typedef struct scc_enet {
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*/
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#define SICR_ENET_MASK ((uint)0x00FF0000)
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#define SICR_ENET_CLKRT ((uint)0x00250000)
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#endif /* CONFIG_MGSUVD */
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#endif /* CONFIG_KM8XX */
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/*** MHPC ********************************************************/
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317
include/configs/km8xx.h
Normal file
317
include/configs/km8xx.h
Normal file
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@ -0,0 +1,317 @@
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/*
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* (C) Copyright 2009
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* configuration options, keymile 8xx board specific
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*/
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#ifndef __CONFIG_KM8XX_H
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#define __CONFIG_KM8XX_H
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_KM8XX 1 /* on a km8xx board */
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/* include common defines/options for all Keymile boards */
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#include "keymile-common.h"
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#define CONFIG_8xx_GCLK_FREQ 66000000
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#define CONFIG_SYS_SMC_UCODE_PATCH 1 /* Relocate SMC1 */
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#define CONFIG_SYS_SMC_DPMEM_OFFSET 0x1fc0
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#define CONFIG_SYS_SMC_RXBUFLEN 128
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#define CONFIG_SYS_MAXIDLE 10
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#define CONFIG_SYS_CPM_BOOTCOUNT_ADDR 0x1eb0 /* In case of SMC relocation,
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* the default value is not
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* working
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*/
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#define BOOTFLASH_START F0000000
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#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#define BOOTFLASH_START F0000000
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#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
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#define CONFIG_ENV_IVM "EEprom_ivm=pca9544a:70:4 \0"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_KM_DEF_ENV \
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"rootpath=/opt/eldk/ppc_8xx\0" \
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"addcon=setenv bootargs ${bootargs} " \
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"console=ttyCPM0,${baudrate}\0" \
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"mtdids=nor0=app \0" \
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"mtdparts=mtdparts=app:384k(u-boot),128k(env),128k(envred)," \
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"128k(free),1536k(esw0),8704k(rootfs0),1536k(esw1)," \
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"2432k(rootfs1),640k(var),768k(cfg)\0" \
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"partition=nor0,9 \0" \
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"new_env=prot off F0060000 F009FFFF; era F0060000 F009FFFF \0" \
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CONFIG_ENV_IVM \
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""
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#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
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#define CONFIG_TIMESTAMP /* but print image timestmps */
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/*
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* Low Level Configuration Settings
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* (address mappings, register initial values, etc.)
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* You should know what you are doing if you make changes here.
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*/
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/*-----------------------------------------------------------------------
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* Internal Memory Mapped Register
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*/
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#define CONFIG_SYS_IMMR 0xFFF00000
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in DPRAM)
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*/
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
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#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
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#define CONFIG_SYS_GBL_DATA_SIZE 64
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#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
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*/
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_FLASH_BASE 0xf0000000
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#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
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#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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/* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_FLASH_SIZE 32
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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/* max num of sects on one chip */
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* (in ms) */
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#define CONFIG_ENV_IS_IN_FLASH 1
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#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
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#define CONFIG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#define CONFIG_ENV_BUFFER_PRINT 1
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
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#endif
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/*-----------------------------------------------------------------------
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* SYPCR - System Protection Control 11-9
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* SYPCR can only be written once after reset!
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*-----------------------------------------------------------------------
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* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
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*/
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#define CONFIG_SYS_SYPCR 0xffffff89
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/*-----------------------------------------------------------------------
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* SIUMCR - SIU Module Configuration 11-6
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*-----------------------------------------------------------------------
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*/
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#define CONFIG_SYS_SIUMCR 0x00610480
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/*-----------------------------------------------------------------------
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* TBSCR - Time Base Status and Control 11-26
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*-----------------------------------------------------------------------
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* Clear Reference Interrupt Status, Timebase freezing enabled
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*/
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#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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/*-----------------------------------------------------------------------
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* PISCR - Periodic Interrupt Status and Control 11-31
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*-----------------------------------------------------------------------
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* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
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*/
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#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
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/*-----------------------------------------------------------------------
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* SCCR - System Clock and reset Control Register 15-27
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*-----------------------------------------------------------------------
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* Set clock output, timebase and RTC source and divider,
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* power management and some other internal clocks
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*/
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#define SCCR_MASK 0x01800000
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#define CONFIG_SYS_SCCR 0x01800000
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#define CONFIG_SYS_DER 0
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM 0xf0000000 /* FLASH bank #0 */
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/* used to re-map FLASH both when starting from SRAM or FLASH:
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* restrict access enough to keep SRAM working (if any)
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* but not too much to meddle with FLASH accesses
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*/
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#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
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#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
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/*
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* FLASH timing: Default value of OR0 after reset
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*/
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#define CONFIG_SYS_OR0_PRELIM 0xfe000954
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#define CONFIG_SYS_BR0_PRELIM 0xf0000401
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/*
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* BR1 and OR1 (SDRAM)
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*
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*/
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#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
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#define SDRAM_MAX_SIZE (64 << 20) /* max 64 MB per bank */
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/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
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#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
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#define CONFIG_SYS_OR1_PRELIM 0xfc000800
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#define CONFIG_SYS_BR1_PRELIM (0x000000C0 | 0x01)
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#define CONFIG_SYS_MPTPR 0x0200
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/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
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1 Write loop Cycle (not used), 1 Timer Loop Cycle */
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#define CONFIG_SYS_MBMR 0x10964111
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#define CONFIG_SYS_MAR 0x00000088
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/*
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* 4096 Rows from SDRAM example configuration
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* 1000 factor s -> ms
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* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
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* 4 Number of refresh cycles per period
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* 64 Refresh cycle in ms per number of rows
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*/
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#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
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/* GPIO/PIGGY on CS3 initialization values
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*/
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#define CONFIG_SYS_PIGGY_BASE (0x30000000)
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#define CONFIG_SYS_OR3_PRELIM (0xfe000d24)
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#define CONFIG_SYS_BR3_PRELIM (0x30000401)
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#define CONFIG_SCC3_ENET
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#define CONFIG_ETHPRIME "SCC ETHERNET"
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#define CONFIG_HAS_ETH0
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/* pass open firmware flat tree */
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#define CONFIG_OF_LIBFDT 1
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#define CONFIG_OF_BOARD_SETUP 1
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#define OF_STDOUT_PATH "/soc/cpm/serial@a80"
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/* enable I2C and select the hardware/software driver */
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#undef CONFIG_HARD_I2C /* I2C with hardware support */
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#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
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/* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SPEED 50000
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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#define I2C_SOFT_DECLARATIONS
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define I2C_BASE_DIR ((u16 *)(CONFIG_SYS_PIGGY_BASE + 0x04))
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#define I2C_BASE_PORT ((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x09))
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#define SDA_BIT 0x40
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#define SCL_BIT 0x80
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#define SDA_CONF 0x1000
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#define SCL_CONF 0x2000
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#define I2C_ACTIVE do {} while (0)
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#define I2C_TRISTATE do {} while (0)
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#define I2C_READ ((in_8(I2C_BASE_PORT) & SDA_BIT) == SDA_BIT)
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#define I2C_SDA(bit) if(bit) { \
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clrbits(be16, I2C_BASE_DIR, SDA_CONF); \
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} else { \
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clrbits(8, I2C_BASE_PORT, SDA_BIT); \
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setbits(be16, I2C_BASE_DIR, SDA_CONF); \
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}
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#define I2C_SCL(bit) if(bit) { \
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clrbits(be16, I2C_BASE_DIR, SCL_CONF); \
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} else { \
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clrbits(8, I2C_BASE_PORT, SCL_BIT); \
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setbits(be16, I2C_BASE_DIR, SCL_CONF); \
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}
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#define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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/* I2C SYSMON (LM75, AD7414 is almost compatible) */
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#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
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#define CONFIG_DTT_SENSORS {0, 2, 4, 6} /* Sensor addresses */
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#define CONFIG_SYS_DTT_MAX_TEMP 70
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#define CONFIG_SYS_DTT_LOW_TEMP -30
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#define CONFIG_SYS_DTT_HYSTERESIS 3
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#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
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#define MTDIDS_DEFAULT "nor0=app"
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#define MTDPARTS_DEFAULT ( \
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"mtdparts=app:384k(u-boot),128k(env),128k(envred),128k(free)," \
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"1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var)," \
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"768k(cfg)")
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#endif /* __CONFIG_KM8XX_H */
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@ -28,292 +28,11 @@
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
|
||||
* (easy to change)
|
||||
*/
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||||
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#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
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#define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */
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#define CONFIG_HOSTNAME mgsuvd
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/* include common defines/options for all Keymile boards */
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#include "keymile-common.h"
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#define CONFIG_8xx_GCLK_FREQ 66000000
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#define CONFIG_SYS_SMC_UCODE_PATCH 1 /* Relocate SMC1 */
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#define CONFIG_SYS_SMC_DPMEM_OFFSET 0x1fc0
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#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
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#define CONFIG_SYS_SMC_RXBUFLEN 128
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#define CONFIG_SYS_MAXIDLE 10
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#define CONFIG_SYS_CPM_BOOTCOUNT_ADDR 0x1eb0 /* In case of SMC relocation,
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* the default value is not
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* working
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*/
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#define BOOTFLASH_START F0000000
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#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#define BOOTFLASH_START F0000000
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#define CONFIG_PRAM 512 /* protected RAM [KBytes] */
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#define CONFIG_ENV_IVM "EEprom_ivm=pca9544a:70:4 \0"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_KM_DEF_ENV \
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"rootpath=/opt/eldk/ppc_8xx\0" \
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"addcon=setenv bootargs ${bootargs} " \
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"console=ttyCPM0,${baudrate}\0" \
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"mtdids=nor0=app \0" \
|
||||
"mtdparts=mtdparts=app:384k(u-boot),128k(env),128k(envred)," \
|
||||
"128k(free),1536k(esw0),8704k(rootfs0),1536k(esw1)," \
|
||||
"2432k(rootfs1),640k(var),768k(cfg)\0" \
|
||||
"partition=nor0,9 \0" \
|
||||
"new_env=prot off F0060000 F009FFFF; era F0060000 F009FFFF \0" \
|
||||
CONFIG_ENV_IVM \
|
||||
""
|
||||
|
||||
#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
|
||||
|
||||
#define CONFIG_TIMESTAMP /* but print image timestmps */
|
||||
|
||||
/*
|
||||
* Low Level Configuration Settings
|
||||
* (address mappings, register initial values, etc.)
|
||||
* You should know what you are doing if you make changes here.
|
||||
*/
|
||||
/*-----------------------------------------------------------------------
|
||||
* Internal Memory Mapped Register
|
||||
*/
|
||||
#define CONFIG_SYS_IMMR 0xFFF00000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 64
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Start addresses for the final memory configuration
|
||||
* (Set up by the startup code)
|
||||
* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
|
||||
*/
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_FLASH_BASE 0xf0000000
|
||||
#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 8 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH organization
|
||||
*/
|
||||
/* max number of memory banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_FLASH_SIZE 32
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
/* max num of sects on one chip */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* (in ms) */
|
||||
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
|
||||
#define CONFIG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
#define CONFIG_ENV_BUFFER_PRINT 1
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Cache Configuration
|
||||
*/
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SYPCR - System Protection Control 11-9
|
||||
* SYPCR can only be written once after reset!
|
||||
*-----------------------------------------------------------------------
|
||||
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||
*/
|
||||
#define CONFIG_SYS_SYPCR 0xffffff89
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SIUMCR - SIU Module Configuration 11-6
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
#define CONFIG_SYS_SIUMCR 0x00610480
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* TBSCR - Time Base Status and Control 11-26
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||
*-----------------------------------------------------------------------
|
||||
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||
*/
|
||||
#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* SCCR - System Clock and reset Control Register 15-27
|
||||
*-----------------------------------------------------------------------
|
||||
* Set clock output, timebase and RTC source and divider,
|
||||
* power management and some other internal clocks
|
||||
*/
|
||||
#define SCCR_MASK 0x01800000
|
||||
#define CONFIG_SYS_SCCR 0x01800000
|
||||
|
||||
#define CONFIG_SYS_DER 0
|
||||
|
||||
/*
|
||||
* Init Memory Controller:
|
||||
*
|
||||
* BR0/1 and OR0/1 (FLASH)
|
||||
*/
|
||||
|
||||
#define FLASH_BASE0_PRELIM 0xf0000000 /* FLASH bank #0 */
|
||||
|
||||
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||
* restrict access enough to keep SRAM working (if any)
|
||||
* but not too much to meddle with FLASH accesses
|
||||
*/
|
||||
#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||
#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
|
||||
|
||||
/*
|
||||
* FLASH timing: Default value of OR0 after reset
|
||||
*/
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xfe000954
|
||||
#define CONFIG_SYS_BR0_PRELIM 0xf0000401
|
||||
|
||||
/*
|
||||
* BR1 and OR1 (SDRAM)
|
||||
*
|
||||
*/
|
||||
#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
|
||||
#define SDRAM_MAX_SIZE (64 << 20) /* max 64 MB per bank */
|
||||
|
||||
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
||||
#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
|
||||
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xfc000800
|
||||
#define CONFIG_SYS_BR1_PRELIM (0x000000C0 | 0x01)
|
||||
|
||||
#define CONFIG_SYS_MPTPR 0x0200
|
||||
/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
|
||||
1 Write loop Cycle (not used), 1 Timer Loop Cycle */
|
||||
#define CONFIG_SYS_MBMR 0x10964111
|
||||
#define CONFIG_SYS_MAR 0x00000088
|
||||
|
||||
/*
|
||||
* 4096 Rows from SDRAM example configuration
|
||||
* 1000 factor s -> ms
|
||||
* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
|
||||
* 4 Number of refresh cycles per period
|
||||
* 64 Refresh cycle in ms per number of rows
|
||||
*/
|
||||
#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
|
||||
|
||||
/* GPIO/PIGGY on CS3 initialization values
|
||||
*/
|
||||
#define CONFIG_SYS_PIGGY_BASE (0x30000000)
|
||||
#define CONFIG_SYS_OR3_PRELIM (0xfe000d24)
|
||||
#define CONFIG_SYS_BR3_PRELIM (0x30000401)
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
*
|
||||
* Boot Flags
|
||||
*/
|
||||
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||
|
||||
#define CONFIG_SCC3_ENET
|
||||
#define CONFIG_ETHPRIME "SCC ETHERNET"
|
||||
#define CONFIG_HAS_ETH0
|
||||
|
||||
/* pass open firmware flat tree */
|
||||
#define CONFIG_OF_LIBFDT 1
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
|
||||
#define OF_STDOUT_PATH "/soc/cpm/serial@a80"
|
||||
|
||||
/* enable I2C and select the hardware/software driver */
|
||||
#undef CONFIG_HARD_I2C /* I2C with hardware support */
|
||||
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
|
||||
/* I2C speed and slave address */
|
||||
#define CONFIG_SYS_I2C_SPEED 50000
|
||||
#define CONFIG_SYS_I2C_SLAVE 0x7F
|
||||
#define I2C_SOFT_DECLARATIONS
|
||||
|
||||
/*
|
||||
* Software (bit-bang) I2C driver configuration
|
||||
*/
|
||||
#define I2C_BASE_DIR ((u16 *)(CONFIG_SYS_PIGGY_BASE + 0x04))
|
||||
#define I2C_BASE_PORT ((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x09))
|
||||
|
||||
#define SDA_BIT 0x40
|
||||
#define SCL_BIT 0x80
|
||||
#define SDA_CONF 0x1000
|
||||
#define SCL_CONF 0x2000
|
||||
|
||||
#define I2C_ACTIVE do {} while (0)
|
||||
#define I2C_TRISTATE do {} while (0)
|
||||
#define I2C_READ ((in_8(I2C_BASE_PORT) & SDA_BIT) == SDA_BIT)
|
||||
#define I2C_SDA(bit) if(bit) { \
|
||||
clrbits(be16, I2C_BASE_DIR, SDA_CONF); \
|
||||
} else { \
|
||||
clrbits(8, I2C_BASE_PORT, SDA_BIT); \
|
||||
setbits(be16, I2C_BASE_DIR, SDA_CONF); \
|
||||
}
|
||||
#define I2C_SCL(bit) if(bit) { \
|
||||
clrbits(be16, I2C_BASE_DIR, SCL_CONF); \
|
||||
} else { \
|
||||
clrbits(8, I2C_BASE_PORT, SCL_BIT); \
|
||||
setbits(be16, I2C_BASE_DIR, SCL_CONF); \
|
||||
}
|
||||
#define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */
|
||||
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
|
||||
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
|
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
|
||||
#define CONFIG_DTT_SENSORS {0, 2, 4, 6} /* Sensor addresses */
|
||||
#define CONFIG_SYS_DTT_MAX_TEMP 70
|
||||
#define CONFIG_SYS_DTT_LOW_TEMP -30
|
||||
#define CONFIG_SYS_DTT_HYSTERESIS 3
|
||||
#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
|
||||
|
||||
#define MTDIDS_DEFAULT "nor0=app"
|
||||
#define MTDPARTS_DEFAULT ( \
|
||||
"mtdparts=app:384k(u-boot),128k(env),128k(envred),128k(free)," \
|
||||
"1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var)," \
|
||||
"768k(cfg)")
|
||||
/* include common defines/options for all Keymile 8xx boards */
|
||||
#include "km8xx.h"
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
|
|
|||
Loading…
Reference in a new issue