mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-26 06:30:39 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-ppc4xx
This commit is contained in:
Wolfgang Denk
commit
d03161b455
8 changed files with 140 additions and 104 deletions
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@ -59,15 +59,15 @@ void __ft_board_setup(void *blob, bd_t *bd)
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*p++ = 0;
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*p++ = bxcr & EBC_BXCR_BAS_MASK;
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*p++ = EBC_BXCR_BANK_SIZE(bxcr);
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#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
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/* Try to update reg property in nor flash node too */
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fdt_fixup_nor_flash_size(blob, i,
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EBC_BXCR_BANK_SIZE(bxcr));
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#endif
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}
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}
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#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
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/* Update reg property in all nor flash nodes too */
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fdt_fixup_nor_flash_size(blob);
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#endif
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/* Some 405 PPC's have EBC as direct PLB child in the dts */
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if (fdt_path_offset(blob, ebc_path) < 0)
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strcpy(ebc_path, "/plb/ebc");
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@ -34,6 +34,7 @@
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#include <common.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#undef DEBUG
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#ifdef DEBUG
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@ -71,6 +72,36 @@ static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
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*/
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static ulong flash_get_size(vu_long * addr, flash_info_t * info);
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/*
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* Override the weak default mapping function with a board specific one
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*/
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u32 flash_get_bank_size(int cs, int idx)
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{
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u8 reg = in_8((void *)CONFIG_SYS_FPGA_BASE);
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if ((reg & BOOT_SMALL_FLASH) && !(reg & FLASH_ONBD_N)) {
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/*
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* cs0: small flash (512KiB)
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* cs2: 2 * big flash (2 * 2MiB)
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*/
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if (cs == 0)
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return flash_info[2].size;
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if (cs == 2)
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return flash_info[0].size + flash_info[1].size;
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} else {
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/*
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* cs0: 2 * big flash (2 * 2MiB)
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* cs2: small flash (512KiB)
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*/
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if (cs == 0)
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return flash_info[0].size + flash_info[1].size;
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if (cs == 2)
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return flash_info[2].size;
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}
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return 0;
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}
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unsigned long flash_init(void)
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{
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unsigned long total_b = 0;
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@ -590,12 +590,31 @@ int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose) {
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#endif
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#ifdef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
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/*
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* Provide a weak default function to return the flash bank size.
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* There might be multiple non-identical flash chips connected to one
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* chip-select, so we need to pass an index as well.
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*/
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u32 __flash_get_bank_size(int cs, int idx)
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{
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extern flash_info_t flash_info[];
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/*
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* As default, a simple 1:1 mapping is provided. Boards with
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* a different mapping need to supply a board specific mapping
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* routine.
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*/
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return flash_info[cs].size;
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}
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u32 flash_get_bank_size(int cs, int idx)
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__attribute__((weak, alias("__flash_get_bank_size")));
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/*
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* This function can be used to update the size in the "reg" property
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* of the NOR FLASH device nodes. This is necessary for boards with
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* of all NOR FLASH device nodes. This is necessary for boards with
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* non-fixed NOR FLASH sizes.
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*/
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int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size)
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int fdt_fixup_nor_flash_size(void *blob)
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{
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char compat[][16] = { "cfi-flash", "jedec-flash" };
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int off;
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@ -607,19 +626,31 @@ int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size)
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for (i = 0; i < 2; i++) {
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off = fdt_node_offset_by_compatible(blob, -1, compat[i]);
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while (off != -FDT_ERR_NOTFOUND) {
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int idx;
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/*
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* Found one compatible node, now check if this one
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* has the correct CS
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* Found one compatible node, so fixup the size
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* int its reg properties
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*/
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prop = fdt_get_property_w(blob, off, "reg", &len);
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if (prop) {
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reg = (u32 *)&prop->data[0];
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if (reg[0] == cs) {
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reg[2] = size;
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fdt_setprop(blob, off, "reg", reg,
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3 * sizeof(u32));
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int tuple_size = 3 * sizeof(reg);
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return 0;
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/*
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* There might be multiple reg-tuples,
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* so loop through them all
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*/
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len /= tuple_size;
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reg = (u32 *)&prop->data[0];
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for (idx = 0; idx < len; idx++) {
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/*
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* Update size in reg property
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*/
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reg[2] = flash_get_bank_size(reg[0],
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idx);
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fdt_setprop(blob, off, "reg", reg,
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tuple_size);
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reg += tuple_size;
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}
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}
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@ -629,7 +660,7 @@ int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size)
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}
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}
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return -1;
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return 0;
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}
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#endif
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@ -105,6 +105,7 @@
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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#define CONFIG_PPC4xx_EMAC
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#undef CONFIG_EXT_PHY
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#define CONFIG_NET_MULTI 1
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@ -398,6 +399,7 @@
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* I2C EEPROM (CAT24WC16) for environment
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*/
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#define CONFIG_HARD_I2C /* I2c with hardware support */
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#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
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#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CONFIG_SYS_I2C_SLAVE 0x7F
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@ -410,16 +412,6 @@
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/* last 4 bits of the address */
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
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/*-----------------------------------------------------------------------
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* Cache Configuration
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*/
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#define CONFIG_SYS_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
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/* have only 8kB, 16kB is save here */
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#define CONFIG_SYS_CACHELINE_SIZE 32 /* ... */
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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#endif
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/*
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* Init Memory Controller:
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*
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@ -570,17 +562,6 @@
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#define DIMM_READ_ADDR 0xAB
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#define DIMM_WRITE_ADDR 0xAA
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#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
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#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
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#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
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#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */
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#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
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#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
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#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
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#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
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#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
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#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
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/* Defines for CPC0_PLLMR1 Register fields */
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#define PLL_ACTIVE 0x80000000
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#define CPC0_PLLMR1_SSCS 0x80000000
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@ -120,7 +120,13 @@
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#else
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#define CONFIG_SYS_NO_FLASH 1 /* No NOR on Acadia when NAND-booting */
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/*
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* No NOR-flash on Acadia when NAND-booting. We need to undef the
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* NOR device-tree fixup code as well, since flash_info is not defined
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* in this case.
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*/
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#define CONFIG_SYS_NO_FLASH 1
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#undef CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
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#endif
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#ifdef CONFIG_ENV_IS_IN_FLASH
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@ -79,7 +79,7 @@ void ft_pci_setup(void *blob, bd_t *bd);
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void set_working_fdt_addr(void *addr);
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int fdt_resize(void *blob);
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int fdt_fixup_nor_flash_size(void *blob, int cs, u32 size);
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int fdt_fixup_nor_flash_size(void *blob);
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void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
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void fdt_del_node_and_alias(void *blob, const char *alias);
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@ -99,6 +99,16 @@
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#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/
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/*
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* Define ns16550 register offset for all PPC4xx SoC's. Some
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* mostly FPGA based PPC4xx implementations use a different
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* offset. So let's give them a chance to define their offset
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* in the board config header.
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*/
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#if !defined(CONFIG_SYS_NS16550_REG_SIZE)
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#endif
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#if defined(CONFIG_440)
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#include <ppc440.h>
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#else
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@ -4,6 +4,8 @@
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*
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* Author: Igor Lisitsin <igor@emcraft.com>
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*
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* Copyright 2010, Stefan Roese, DENX Software Engineering, sr@denx.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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@ -24,6 +26,9 @@
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <ns16550.h>
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#include <asm/io.h>
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/*
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* UART test
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@ -119,33 +124,24 @@
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#define UDIV_MAX 32
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#endif
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#define UART_RBR 0x00
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#define UART_THR 0x00
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#define UART_IER 0x01
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#define UART_IIR 0x02
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#define UART_FCR 0x02
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#define UART_LCR 0x03
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#define UART_MCR 0x04
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#define UART_LSR 0x05
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#define UART_MSR 0x06
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#define UART_SCR 0x07
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#define UART_DLL 0x00
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#define UART_DLM 0x01
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/*
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* Line Status Register.
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*/
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#define asyncLSRDataReady1 0x01
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#define asyncLSROverrunError1 0x02
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#define asyncLSRParityError1 0x04
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#define asyncLSRFramingError1 0x08
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#define asyncLSRBreakInterrupt1 0x10
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#define asyncLSRTxHoldEmpty1 0x20
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#define asyncLSRTxShiftEmpty1 0x40
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#define asyncLSRRxFifoError1 0x80
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DECLARE_GLOBAL_DATA_PTR;
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static void uart_post_init_common(struct NS16550 *com_port, unsigned short bdiv)
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{
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volatile char val;
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out_8(&com_port->lcr, 0x80); /* set DLAB bit */
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out_8(&com_port->dll, bdiv); /* set baudrate divisor */
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out_8(&com_port->dlm, bdiv >> 8); /* set baudrate divisor */
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out_8(&com_port->lcr, 0x03); /* clear DLAB; set 8 bits, no parity */
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out_8(&com_port->fcr, 0x00); /* disable FIFO */
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out_8(&com_port->mcr, 0x10); /* enable loopback mode */
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val = in_8(&com_port->lsr); /* clear line status */
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val = in_8(&com_port->rbr); /* read receive buffer */
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out_8(&com_port->scr, 0x00); /* set scratchpad */
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out_8(&com_port->ier, 0x00); /* set interrupt enable reg */
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}
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#if defined(CONFIG_440) || defined(CONFIG_405EX)
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#if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
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static void serial_divs (int baudrate, unsigned long *pudiv,
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@ -190,19 +186,18 @@ static void serial_divs (int baudrate, unsigned long *pudiv,
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}
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#endif
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static int uart_post_init (unsigned long dev_base)
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static int uart_post_init (struct NS16550 *com_port)
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{
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unsigned long reg = 0;
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unsigned long udiv;
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unsigned short bdiv;
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volatile char val;
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#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
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unsigned long tmp;
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#endif
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int i;
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|
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for (i = 0; i < 3500; i++) {
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if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
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if (in_8(&com_port->lsr) & UART_LSR_THRE)
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break;
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udelay (100);
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}
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@ -239,34 +234,24 @@ static int uart_post_init (unsigned long dev_base)
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MTREG(UART3_SDR, reg);
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#endif
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out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
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out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
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out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
|
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out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
|
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out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
|
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out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
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val = in8(dev_base + UART_LSR); /* clear line status */
|
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val = in8(dev_base + UART_RBR); /* read receive buffer */
|
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out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
|
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out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
|
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uart_post_init_common(com_port, bdiv);
|
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|
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return 0;
|
||||
}
|
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|
||||
#else /* CONFIG_440 */
|
||||
|
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static int uart_post_init (unsigned long dev_base)
|
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static int uart_post_init (struct NS16550 *com_port)
|
||||
{
|
||||
unsigned long reg;
|
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unsigned long tmp;
|
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unsigned long clk;
|
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unsigned long udiv;
|
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unsigned short bdiv;
|
||||
volatile char val;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 3500; i++) {
|
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if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
|
||||
if (in_8(&com_port->lsr) & UART_LSR_THRE)
|
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break;
|
||||
udelay (100);
|
||||
}
|
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|
|
@ -309,59 +294,51 @@ static int uart_post_init (unsigned long dev_base)
|
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bdiv = (clk + tmp / 2) / tmp;
|
||||
#endif /* CONFIG_405EZ */
|
||||
|
||||
out8(dev_base + UART_LCR, 0x80); /* set DLAB bit */
|
||||
out8(dev_base + UART_DLL, bdiv); /* set baudrate divisor */
|
||||
out8(dev_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */
|
||||
out8(dev_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
|
||||
out8(dev_base + UART_FCR, 0x00); /* disable FIFO */
|
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out8(dev_base + UART_MCR, 0x10); /* enable loopback mode */
|
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val = in8(dev_base + UART_LSR); /* clear line status */
|
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val = in8(dev_base + UART_RBR); /* read receive buffer */
|
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out8(dev_base + UART_SCR, 0x00); /* set scratchpad */
|
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out8(dev_base + UART_IER, 0x00); /* set interrupt enable reg */
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uart_post_init_common(com_port, bdiv);
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return (0);
|
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return 0;
|
||||
}
|
||||
#endif /* CONFIG_440 */
|
||||
|
||||
static void uart_post_putc (unsigned long dev_base, char c)
|
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static void uart_post_putc (struct NS16550 *com_port, char c)
|
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{
|
||||
int i;
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||||
|
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out8 (dev_base + UART_THR, c); /* put character out */
|
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out_8(&com_port->thr, c); /* put character out */
|
||||
|
||||
/* Wait for transfer completion */
|
||||
for (i = 0; i < 3500; i++) {
|
||||
if (in8 (dev_base + UART_LSR) & asyncLSRTxHoldEmpty1)
|
||||
if (in_8(&com_port->lsr) & UART_LSR_THRE)
|
||||
break;
|
||||
udelay (100);
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||||
}
|
||||
}
|
||||
|
||||
static int uart_post_getc (unsigned long dev_base)
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static int uart_post_getc (struct NS16550 *com_port)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Wait for character available */
|
||||
for (i = 0; i < 3500; i++) {
|
||||
if (in8 (dev_base + UART_LSR) & asyncLSRDataReady1)
|
||||
if (in_8(&com_port->lsr) & UART_LSR_DR)
|
||||
break;
|
||||
udelay (100);
|
||||
}
|
||||
return 0xff & in8 (dev_base + UART_RBR);
|
||||
|
||||
return 0xff & in_8(&com_port->rbr);
|
||||
}
|
||||
|
||||
static int test_ctlr (unsigned long dev_base, int index)
|
||||
static int test_ctlr (struct NS16550 *com_port, int index)
|
||||
{
|
||||
int res = -1;
|
||||
char test_str[] = "*** UART Test String ***\r\n";
|
||||
int i;
|
||||
|
||||
uart_post_init (dev_base);
|
||||
uart_post_init (com_port);
|
||||
|
||||
for (i = 0; i < sizeof (test_str) - 1; i++) {
|
||||
uart_post_putc (dev_base, test_str[i]);
|
||||
if (uart_post_getc (dev_base) != test_str[i])
|
||||
uart_post_putc (com_port, test_str[i]);
|
||||
if (uart_post_getc (com_port) != test_str[i])
|
||||
goto done;
|
||||
}
|
||||
res = 0;
|
||||
|
|
@ -377,8 +354,8 @@ int uart_post_test (int flags)
|
|||
int i, res = 0;
|
||||
static unsigned long base[] = CONFIG_SYS_POST_UART_TABLE;
|
||||
|
||||
for (i = 0; i < sizeof (base) / sizeof (base[0]); i++) {
|
||||
if (test_ctlr (base[i], i))
|
||||
for (i = 0; i < ARRAY_SIZE(base); i++) {
|
||||
if (test_ctlr((struct NS16550 *)base[i], i))
|
||||
res = -1;
|
||||
}
|
||||
serial_reinit_all ();
|
||||
|
|
|
|||
Loading…
Reference in a new issue