mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 16:10:58 +00:00
Merge with /home/mk/11-cmb1920/u-boot
This commit is contained in:
Wolfgang Denk
commit
cf8f60f0ea
18 changed files with 1387 additions and 29 deletions
23
MAKEALL
23
MAKEALL
|
|
@ -34,7 +34,6 @@ LIST_5xxx=" \
|
||||||
#########################################################################
|
#########################################################################
|
||||||
## MPC8xx Systems
|
## MPC8xx Systems
|
||||||
#########################################################################
|
#########################################################################
|
||||||
|
|
||||||
LIST_8xx=" \
|
LIST_8xx=" \
|
||||||
Adder87x GENIETV MBX860T R360MPI \
|
Adder87x GENIETV MBX860T R360MPI \
|
||||||
AdderII GTH MHPC RBC823 \
|
AdderII GTH MHPC RBC823 \
|
||||||
|
|
@ -44,16 +43,18 @@ LIST_8xx=" \
|
||||||
CCM IP860 NETPHONE RPXlite_DW \
|
CCM IP860 NETPHONE RPXlite_DW \
|
||||||
cogent_mpc8xx IVML24 NETTA RRvision \
|
cogent_mpc8xx IVML24 NETTA RRvision \
|
||||||
ELPT860 IVML24_128 NETTA2 SM850 \
|
ELPT860 IVML24_128 NETTA2 SM850 \
|
||||||
EP88x IVML24_256 NETTA_ISDN SPD823TS \
|
EP88x IVML24_256 NETTA_ISDN spc1920 \
|
||||||
ESTEEM192E IVMS8 NETVIA svm_sc8xx \
|
ESTEEM192E IVMS8 NETVIA SPD823TS \
|
||||||
ETX094 IVMS8_128 NETVIA_V2 SXNI855T \
|
ETX094 IVMS8_128 NETVIA_V2 svm_sc8xx \
|
||||||
FADS823 IVMS8_256 NX823 TOP860 \
|
FADS823 IVMS8_256 NX823 SXNI855T \
|
||||||
FADS850SAR KUP4K pcu_e TQM823L \
|
FADS850SAR KUP4K pcu_e TOP860 \
|
||||||
FADS860T KUP4X QS823 TQM823L_LCD \
|
FADS860T KUP4X QS823 TQM823L \
|
||||||
FLAGADM LANTEC QS850 TQM850L \
|
FLAGADM LANTEC QS850 TQM823L_LCD \
|
||||||
FPS850L lwmon QS860T TQM855L \
|
FPS850L lwmon QS860T TQM850L \
|
||||||
GEN860T MBX quantum TQM860L \
|
GEN860T MBX quantum TQM855L \
|
||||||
GEN860T_SC uc100 \
|
GEN860T_SC TQM860L \
|
||||||
|
TQM885D \
|
||||||
|
uc100 \
|
||||||
v37 \
|
v37 \
|
||||||
"
|
"
|
||||||
|
|
||||||
|
|
|
||||||
4
Makefile
4
Makefile
|
|
@ -705,6 +705,9 @@ RRvision_LCD_config: unconfig
|
||||||
SM850_config : unconfig
|
SM850_config : unconfig
|
||||||
@./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
|
@./mkconfig $(@:_config=) ppc mpc8xx tqm8xx
|
||||||
|
|
||||||
|
spc1920_config:
|
||||||
|
@./mkconfig $(@:_config=) ppc mpc8xx spc1920
|
||||||
|
|
||||||
SPD823TS_config: unconfig
|
SPD823TS_config: unconfig
|
||||||
@./mkconfig $(@:_config=) ppc mpc8xx spd8xx
|
@./mkconfig $(@:_config=) ppc mpc8xx spd8xx
|
||||||
|
|
||||||
|
|
@ -742,6 +745,7 @@ TQM855M_config \
|
||||||
TQM860M_config \
|
TQM860M_config \
|
||||||
TQM862M_config \
|
TQM862M_config \
|
||||||
TQM866M_config \
|
TQM866M_config \
|
||||||
|
TQM885D_config \
|
||||||
virtlab2_config: unconfig
|
virtlab2_config: unconfig
|
||||||
@ >include/config.h
|
@ >include/config.h
|
||||||
@[ -z "$(findstring _LCD,$@)" ] || \
|
@[ -z "$(findstring _LCD,$@)" ] || \
|
||||||
|
|
|
||||||
40
board/spc1920/Makefile
Normal file
40
board/spc1920/Makefile
Normal file
|
|
@ -0,0 +1,40 @@
|
||||||
|
#
|
||||||
|
# (C) Copyright 2000
|
||||||
|
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
#
|
||||||
|
# See file CREDITS for list of people who contributed to this
|
||||||
|
# project.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
# MA 02111-1307 USA
|
||||||
|
#
|
||||||
|
|
||||||
|
include $(TOPDIR)/config.mk
|
||||||
|
|
||||||
|
LIB = lib$(BOARD).a
|
||||||
|
|
||||||
|
OBJS = $(BOARD).o
|
||||||
|
|
||||||
|
$(LIB): .depend $(OBJS)
|
||||||
|
$(AR) crv $@ $(OBJS)
|
||||||
|
|
||||||
|
#########################################################################
|
||||||
|
|
||||||
|
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
|
||||||
|
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
|
||||||
|
|
||||||
|
sinclude .depend
|
||||||
|
|
||||||
|
#########################################################################
|
||||||
35
board/spc1920/config.mk
Normal file
35
board/spc1920/config.mk
Normal file
|
|
@ -0,0 +1,35 @@
|
||||||
|
#
|
||||||
|
# (C) Copyright 2000-2004
|
||||||
|
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
#
|
||||||
|
# Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
|
||||||
|
#
|
||||||
|
# See file CREDITS for list of people who contributed to this
|
||||||
|
# project.
|
||||||
|
#
|
||||||
|
# This program is free software; you can redistribute it and/or
|
||||||
|
# modify it under the terms of the GNU General Public License as
|
||||||
|
# published by the Free Software Foundation; either version 2 of
|
||||||
|
# the License, or (at your option) any later version.
|
||||||
|
#
|
||||||
|
# This program is distributed in the hope that it will be useful,
|
||||||
|
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
# GNU General Public License for more details.
|
||||||
|
#
|
||||||
|
# You should have received a copy of the GNU General Public License
|
||||||
|
# along with this program; if not, write to the Free Software
|
||||||
|
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
# MA 02111-1307 USA
|
||||||
|
#
|
||||||
|
|
||||||
|
#
|
||||||
|
# Motorola old MPC821/860ADS, MPC8xxFADS, new MPC866ADS, and
|
||||||
|
# MPC885ADS boards
|
||||||
|
#
|
||||||
|
|
||||||
|
#TEXT_BASE = 0xFE000000
|
||||||
|
TEXT_BASE = 0xFFF00000
|
||||||
|
PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/spc1920
|
||||||
|
HOST_CFLAGS += -I$(TOPDIR)/board/spc1920
|
||||||
|
HOST_ENVIRO_CFLAGS += -I$(TOPDIR)/board/spc1920
|
||||||
14
board/spc1920/pld.h
Normal file
14
board/spc1920/pld.h
Normal file
|
|
@ -0,0 +1,14 @@
|
||||||
|
#ifndef __PLD_H__
|
||||||
|
#define __PLD_H__
|
||||||
|
|
||||||
|
typedef struct spc1920_pld {
|
||||||
|
uchar com1_en;
|
||||||
|
uchar dsp_reset;
|
||||||
|
uchar dsp_hpi_on;
|
||||||
|
uchar codec_dsp_power_en;
|
||||||
|
uchar clk2_en;
|
||||||
|
uchar clk3_select;
|
||||||
|
uchar clk4_select;
|
||||||
|
} spc1920_pld_t;
|
||||||
|
|
||||||
|
#endif /* __PLD_H__ */
|
||||||
237
board/spc1920/spc1920.c
Normal file
237
board/spc1920/spc1920.c
Normal file
|
|
@ -0,0 +1,237 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2000-2004
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* Modified by, Yuli Barcohen, Arabella Software Ltd., yuli@arabellasw.com
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <config.h>
|
||||||
|
#include <common.h>
|
||||||
|
#include <mpc8xx.h>
|
||||||
|
#include "pld.h"
|
||||||
|
|
||||||
|
#define _NOT_USED_ 0xFFFFFFFF
|
||||||
|
/* #define debug(fmt,args...) printf (fmt ,##args) */
|
||||||
|
|
||||||
|
static long int dram_size (long int, long int *, long int);
|
||||||
|
|
||||||
|
const uint sdram_table[] = {
|
||||||
|
/*
|
||||||
|
* Single Read. (Offset 0 in UPMB RAM)
|
||||||
|
*/
|
||||||
|
0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
|
||||||
|
0x1FF77C47, /* last */
|
||||||
|
/*
|
||||||
|
* SDRAM Initialization (offset 5 in UPMB RAM)
|
||||||
|
*
|
||||||
|
* This is no UPM entry point. The following definition uses
|
||||||
|
* the remaining space to establish an initialization
|
||||||
|
* sequence, which is executed by a RUN command.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
|
||||||
|
/*
|
||||||
|
* Burst Read. (Offset 8 in UPMB RAM)
|
||||||
|
*/
|
||||||
|
0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
|
||||||
|
0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
|
||||||
|
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
|
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
|
/*
|
||||||
|
* Single Write. (Offset 18 in UPMB RAM)
|
||||||
|
*/
|
||||||
|
0x1F07FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
|
||||||
|
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
|
/*
|
||||||
|
* Burst Write. (Offset 20 in UPMB RAM)
|
||||||
|
*/
|
||||||
|
0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
|
||||||
|
0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
|
||||||
|
_NOT_USED_,
|
||||||
|
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
|
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
|
/*
|
||||||
|
* Refresh (Offset 30 in UPMB RAM)
|
||||||
|
*/
|
||||||
|
0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
|
||||||
|
0xFFFFFC84, 0xFFFFFC07, /* last */
|
||||||
|
_NOT_USED_, _NOT_USED_,
|
||||||
|
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
|
/*
|
||||||
|
* Exception. (Offset 3c in UPMB RAM)
|
||||||
|
*/
|
||||||
|
0x7FFFFC07, /* last */
|
||||||
|
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
|
};
|
||||||
|
|
||||||
|
long int initdram (int board_type)
|
||||||
|
{
|
||||||
|
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
||||||
|
volatile memctl8xx_t *memctl = &immr->im_memctl;
|
||||||
|
/* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE; */
|
||||||
|
|
||||||
|
long int size_b0;
|
||||||
|
long int size8, size9;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Configure UPMB for SDRAM
|
||||||
|
*/
|
||||||
|
upmconfig (UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
|
||||||
|
|
||||||
|
udelay(100);
|
||||||
|
|
||||||
|
memctl->memc_mptpr = CFG_MPTPR;
|
||||||
|
|
||||||
|
/* burst length=4, burst type=sequential, CAS latency=2 */
|
||||||
|
memctl->memc_mar = CFG_MAR;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Map controller bank 1 to the SDRAM bank at preliminary address.
|
||||||
|
*/
|
||||||
|
memctl->memc_or1 = CFG_OR1_PRELIM;
|
||||||
|
memctl->memc_br1 = CFG_BR1_PRELIM;
|
||||||
|
|
||||||
|
/* initialize memory address register */
|
||||||
|
memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
|
||||||
|
|
||||||
|
/* mode initialization (offset 5) */
|
||||||
|
udelay (200); /* 0x80006105 */
|
||||||
|
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x05);
|
||||||
|
|
||||||
|
/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
|
||||||
|
udelay (1); /* 0x80006130 */
|
||||||
|
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);
|
||||||
|
udelay (1); /* 0x80006130 */
|
||||||
|
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x30);
|
||||||
|
udelay (1); /* 0x80006106 */
|
||||||
|
memctl->memc_mcr = MCR_OP_RUN | MCR_UPM_B | MCR_MB_CS1 | MCR_MLCF (1) | MCR_MAD (0x06);
|
||||||
|
|
||||||
|
memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
|
||||||
|
|
||||||
|
udelay (200);
|
||||||
|
|
||||||
|
/* Need at least 10 DRAM accesses to stabilize */
|
||||||
|
for (i = 0; i < 10; ++i) {
|
||||||
|
volatile unsigned long *addr =
|
||||||
|
(volatile unsigned long *) CFG_SDRAM_BASE;
|
||||||
|
unsigned long val;
|
||||||
|
|
||||||
|
val = *(addr + i);
|
||||||
|
*(addr + i) = val;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Check Bank 0 Memory Size for re-configuration
|
||||||
|
*
|
||||||
|
* try 8 column mode
|
||||||
|
*/
|
||||||
|
size8 = dram_size (CFG_MBMR_8COL, (long *)CFG_SDRAM_BASE, SDRAM_MAX_SIZE);
|
||||||
|
|
||||||
|
udelay (1000);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* try 9 column mode
|
||||||
|
*/
|
||||||
|
size9 = dram_size (CFG_MBMR_9COL, (long *)CFG_SDRAM_BASE, SDRAM_MAX_SIZE);
|
||||||
|
|
||||||
|
if (size8 < size9) { /* leave configuration at 9 columns */
|
||||||
|
size_b0 = size9;
|
||||||
|
memctl->memc_mbmr = CFG_MBMR_9COL | MBMR_PTBE;
|
||||||
|
udelay (500);
|
||||||
|
} else { /* back to 8 columns */
|
||||||
|
size_b0 = size8;
|
||||||
|
memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
|
||||||
|
udelay (500);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Final mapping:
|
||||||
|
*/
|
||||||
|
|
||||||
|
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) |
|
||||||
|
OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
|
||||||
|
memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
|
||||||
|
udelay (1000);
|
||||||
|
|
||||||
|
|
||||||
|
/* PLD Setup */
|
||||||
|
memctl->memc_or5 = CFG_OR5_PRELIM;
|
||||||
|
memctl->memc_br5 = CFG_BR5_PRELIM;
|
||||||
|
udelay(1000);
|
||||||
|
|
||||||
|
return (size_b0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Check memory range for valid RAM. A simple memory test determines
|
||||||
|
* the actually available RAM size between addresses `base' and
|
||||||
|
* `base + maxsize'. Some (not all) hardware errors are detected:
|
||||||
|
* - short between address lines
|
||||||
|
* - short between data lines
|
||||||
|
*/
|
||||||
|
static long int dram_size (long int mbmr_value, long int *base,
|
||||||
|
long int maxsize)
|
||||||
|
{
|
||||||
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
|
|
||||||
|
memctl->memc_mbmr = mbmr_value;
|
||||||
|
|
||||||
|
return (get_ram_size (base, maxsize));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/************* other stuff ******************/
|
||||||
|
|
||||||
|
|
||||||
|
int board_early_init_f(void)
|
||||||
|
{
|
||||||
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
|
|
||||||
|
|
||||||
|
/* Turn on LED PD9 */
|
||||||
|
immap->im_ioport.iop_pdpar &= ~(0x0040);
|
||||||
|
immap->im_ioport.iop_pddir |= 0x0040;
|
||||||
|
immap->im_ioport.iop_pddat |= 0x0040;
|
||||||
|
|
||||||
|
/* Enable PD10 (COM2_EN) */
|
||||||
|
immap->im_ioport.iop_pdpar &= ~0x0020;
|
||||||
|
immap->im_ioport.iop_pddir &= ~0x4000;
|
||||||
|
immap->im_ioport.iop_pddir |= 0x0020;
|
||||||
|
immap->im_ioport.iop_pddat |= 0x0020;
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef CFG_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */
|
||||||
|
immap->im_cpm.cp_simode |= 0x7000;
|
||||||
|
immap->im_cpm.cp_simode &= ~(0x8000);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
int checkboard (void)
|
||||||
|
{
|
||||||
|
puts("Board: SPC1920\n");
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
144
board/spc1920/u-boot.lds
Normal file
144
board/spc1920/u-boot.lds
Normal file
|
|
@ -0,0 +1,144 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2000
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
OUTPUT_ARCH(powerpc)
|
||||||
|
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
|
||||||
|
/* Do we need any of these for elf?
|
||||||
|
__DYNAMIC = 0; */
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* Read-only sections, merged into text segment: */
|
||||||
|
. = + SIZEOF_HEADERS;
|
||||||
|
.interp : { *(.interp) }
|
||||||
|
.hash : { *(.hash) }
|
||||||
|
.dynsym : { *(.dynsym) }
|
||||||
|
.dynstr : { *(.dynstr) }
|
||||||
|
.rel.text : { *(.rel.text) }
|
||||||
|
.rela.text : { *(.rela.text) }
|
||||||
|
.rel.data : { *(.rel.data) }
|
||||||
|
.rela.data : { *(.rela.data) }
|
||||||
|
.rel.rodata : { *(.rel.rodata) }
|
||||||
|
.rela.rodata : { *(.rela.rodata) }
|
||||||
|
.rel.got : { *(.rel.got) }
|
||||||
|
.rela.got : { *(.rela.got) }
|
||||||
|
.rel.ctors : { *(.rel.ctors) }
|
||||||
|
.rela.ctors : { *(.rela.ctors) }
|
||||||
|
.rel.dtors : { *(.rel.dtors) }
|
||||||
|
.rela.dtors : { *(.rela.dtors) }
|
||||||
|
.rel.bss : { *(.rel.bss) }
|
||||||
|
.rela.bss : { *(.rela.bss) }
|
||||||
|
.rel.plt : { *(.rel.plt) }
|
||||||
|
.rela.plt : { *(.rela.plt) }
|
||||||
|
.init : { *(.init) }
|
||||||
|
.plt : { *(.plt) }
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
/* WARNING - the following is hand-optimized to fit within */
|
||||||
|
/* the sector layout of our flash chips! XXX FIXME XXX */
|
||||||
|
|
||||||
|
cpu/mpc8xx/start.o (.text)
|
||||||
|
cpu/mpc8xx/traps.o (.text)
|
||||||
|
common/dlmalloc.o (.text)
|
||||||
|
lib_ppc/ppcstring.o (.text)
|
||||||
|
lib_generic/vsprintf.o (.text)
|
||||||
|
lib_generic/crc32.o (.text)
|
||||||
|
lib_generic/zlib.o (.text)
|
||||||
|
lib_ppc/cache.o (.text)
|
||||||
|
lib_ppc/time.o (.text)
|
||||||
|
|
||||||
|
. = DEFINED(env_offset) ? env_offset : .;
|
||||||
|
common/environment.o (.ppcenv)
|
||||||
|
|
||||||
|
*(.text)
|
||||||
|
*(.fixup)
|
||||||
|
*(.got1)
|
||||||
|
}
|
||||||
|
_etext = .;
|
||||||
|
PROVIDE (etext = .);
|
||||||
|
.rodata :
|
||||||
|
{
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata1)
|
||||||
|
*(.rodata.str1.4)
|
||||||
|
*(.eh_frame)
|
||||||
|
}
|
||||||
|
.fini : { *(.fini) } =0
|
||||||
|
.ctors : { *(.ctors) }
|
||||||
|
.dtors : { *(.dtors) }
|
||||||
|
|
||||||
|
/* Read-write section, merged into data segment: */
|
||||||
|
. = (. + 0x00FF) & 0xFFFFFF00;
|
||||||
|
_erotext = .;
|
||||||
|
PROVIDE (erotext = .);
|
||||||
|
.reloc :
|
||||||
|
{
|
||||||
|
*(.got)
|
||||||
|
_GOT2_TABLE_ = .;
|
||||||
|
*(.got2)
|
||||||
|
_FIXUP_TABLE_ = .;
|
||||||
|
*(.fixup)
|
||||||
|
}
|
||||||
|
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
|
||||||
|
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
|
||||||
|
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
*(.data)
|
||||||
|
*(.data1)
|
||||||
|
*(.sdata)
|
||||||
|
*(.sdata2)
|
||||||
|
*(.dynamic)
|
||||||
|
CONSTRUCTORS
|
||||||
|
}
|
||||||
|
_edata = .;
|
||||||
|
PROVIDE (edata = .);
|
||||||
|
|
||||||
|
. = .;
|
||||||
|
__u_boot_cmd_start = .;
|
||||||
|
.u_boot_cmd : { *(.u_boot_cmd) }
|
||||||
|
__u_boot_cmd_end = .;
|
||||||
|
|
||||||
|
|
||||||
|
. = .;
|
||||||
|
__start___ex_table = .;
|
||||||
|
__ex_table : { *(__ex_table) }
|
||||||
|
__stop___ex_table = .;
|
||||||
|
|
||||||
|
. = ALIGN(256);
|
||||||
|
__init_begin = .;
|
||||||
|
.text.init : { *(.text.init) }
|
||||||
|
.data.init : { *(.data.init) }
|
||||||
|
. = ALIGN(256);
|
||||||
|
__init_end = .;
|
||||||
|
|
||||||
|
__bss_start = .;
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
*(.sbss) *(.scommon)
|
||||||
|
*(.dynbss)
|
||||||
|
*(.bss)
|
||||||
|
*(COMMON)
|
||||||
|
}
|
||||||
|
_end = . ;
|
||||||
|
PROVIDE (end = .);
|
||||||
|
}
|
||||||
|
|
@ -33,12 +33,13 @@
|
||||||
|
|
||||||
DECLARE_GLOBAL_DATA_PTR;
|
DECLARE_GLOBAL_DATA_PTR;
|
||||||
|
|
||||||
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
|
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
|
||||||
|
&& !defined(CONFIG_TQM885D)
|
||||||
# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
|
# ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
|
||||||
# define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
# define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||||
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
OR_SCY_2_CLK | OR_EHTR | OR_BI)
|
||||||
# endif
|
# endif
|
||||||
#endif /* CONFIG_TQM8xxL/M, !TQM866M */
|
#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
|
||||||
|
|
||||||
#ifndef CFG_ENV_ADDR
|
#ifndef CFG_ENV_ADDR
|
||||||
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
|
#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
|
||||||
|
|
|
||||||
|
|
@ -119,6 +119,10 @@ int checkboard (void)
|
||||||
gd->board_type = 'M';
|
gd->board_type = 'M';
|
||||||
}
|
}
|
||||||
|
|
||||||
|
if ((*(s + 6) == 'D')) { /* a TQM885D type */
|
||||||
|
gd->board_type = 'D';
|
||||||
|
}
|
||||||
|
|
||||||
for (; *s; ++s) {
|
for (; *s; ++s) {
|
||||||
if (*s == ' ')
|
if (*s == ' ')
|
||||||
break;
|
break;
|
||||||
|
|
@ -178,7 +182,8 @@ long int initdram (int board_type)
|
||||||
|
|
||||||
#ifndef CONFIG_CAN_DRIVER
|
#ifndef CONFIG_CAN_DRIVER
|
||||||
if ((board_type != 'L') &&
|
if ((board_type != 'L') &&
|
||||||
(board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
|
(board_type != 'M') &&
|
||||||
|
(board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
|
||||||
memctl->memc_or3 = CFG_OR3_PRELIM;
|
memctl->memc_or3 = CFG_OR3_PRELIM;
|
||||||
memctl->memc_br3 = CFG_BR3_PRELIM;
|
memctl->memc_br3 = CFG_BR3_PRELIM;
|
||||||
}
|
}
|
||||||
|
|
@ -197,7 +202,8 @@ long int initdram (int board_type)
|
||||||
|
|
||||||
#ifndef CONFIG_CAN_DRIVER
|
#ifndef CONFIG_CAN_DRIVER
|
||||||
if ((board_type != 'L') &&
|
if ((board_type != 'L') &&
|
||||||
(board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
|
(board_type != 'M') &&
|
||||||
|
(board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
|
||||||
memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
|
memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
|
||||||
udelay (1);
|
udelay (1);
|
||||||
memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
|
memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
|
||||||
|
|
@ -255,7 +261,8 @@ long int initdram (int board_type)
|
||||||
|
|
||||||
#ifndef CONFIG_CAN_DRIVER
|
#ifndef CONFIG_CAN_DRIVER
|
||||||
if ((board_type != 'L') &&
|
if ((board_type != 'L') &&
|
||||||
(board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
|
(board_type != 'M') &&
|
||||||
|
(board_type != 'D') ) { /* "L" and "M" type boards have only one bank SDRAM */
|
||||||
/*
|
/*
|
||||||
* Check Bank 1 Memory Size
|
* Check Bank 1 Memory Size
|
||||||
* use current column settings
|
* use current column settings
|
||||||
|
|
|
||||||
|
|
@ -161,6 +161,7 @@ void cpu_init_f (volatile immap_t * immr)
|
||||||
defined(CONFIG_RMU) || \
|
defined(CONFIG_RMU) || \
|
||||||
defined(CONFIG_RPXCLASSIC) || \
|
defined(CONFIG_RPXCLASSIC) || \
|
||||||
defined(CONFIG_RPXLITE) || \
|
defined(CONFIG_RPXLITE) || \
|
||||||
|
defined(CONFIG_SPC1920) || \
|
||||||
defined(CONFIG_SPD823TS)
|
defined(CONFIG_SPD823TS)
|
||||||
|
|
||||||
memctl->memc_br0 = CFG_BR0_PRELIM;
|
memctl->memc_br0 = CFG_BR0_PRELIM;
|
||||||
|
|
|
||||||
|
|
@ -396,8 +396,10 @@ static void fec_pin_init(int fecidx)
|
||||||
* * to 2.5 MHz.
|
* * to 2.5 MHz.
|
||||||
* * This MDC frequency is equal to system clock / (2 * MII_SPEED).
|
* * This MDC frequency is equal to system clock / (2 * MII_SPEED).
|
||||||
* * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
|
* * Then MII_SPEED = system_clock / 2 * 2,5 Mhz.
|
||||||
|
*
|
||||||
|
* All MII configuration is done via FEC1 registers:
|
||||||
*/
|
*/
|
||||||
fecp->fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
|
immr->im_cpm.cp_fec1.fec_mii_speed = ((bd->bi_intfreq + 4999999) / 5000000) << 1;
|
||||||
|
|
||||||
#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
|
#if defined(CONFIG_NETTA) || defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2)
|
||||||
/* our PHYs are the limit at 2.5 MHz */
|
/* our PHYs are the limit at 2.5 MHz */
|
||||||
|
|
@ -508,8 +510,6 @@ static void fec_pin_init(int fecidx)
|
||||||
#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
|
#if defined(CONFIG_MPC885_FAMILY) /* MPC87x/88x have got 2 FECs and different pinout */
|
||||||
|
|
||||||
#if !defined(CONFIG_RMII)
|
#if !defined(CONFIG_RMII)
|
||||||
|
|
||||||
#warning this configuration is not tested; please report if it works
|
|
||||||
immr->im_cpm.cp_pepar |= 0x0003fffc;
|
immr->im_cpm.cp_pepar |= 0x0003fffc;
|
||||||
immr->im_cpm.cp_pedir |= 0x0003fffc;
|
immr->im_cpm.cp_pedir |= 0x0003fffc;
|
||||||
immr->im_cpm.cp_peso &= ~0x000087fc;
|
immr->im_cpm.cp_peso &= ~0x000087fc;
|
||||||
|
|
@ -822,6 +822,7 @@ static void fec_halt(struct eth_device* dev)
|
||||||
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
#define PHY_ID_LSI80225 0x0016f870 /* LSI 80225 */
|
||||||
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
#define PHY_ID_LSI80225B 0x0016f880 /* LSI 80225/B */
|
||||||
#define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */
|
#define PHY_ID_DM9161 0x0181B880 /* Davicom DM9161 */
|
||||||
|
#define PHY_ID_KSM8995M 0x00221450 /* MICREL KS8995MA */
|
||||||
|
|
||||||
/* send command to phy using mii, wait for result */
|
/* send command to phy using mii, wait for result */
|
||||||
static uint
|
static uint
|
||||||
|
|
@ -907,6 +908,9 @@ static int mii_discover_phy(struct eth_device *dev)
|
||||||
case PHY_ID_DM9161:
|
case PHY_ID_DM9161:
|
||||||
printf("Davicom DM9161\n");
|
printf("Davicom DM9161\n");
|
||||||
break;
|
break;
|
||||||
|
case PHY_ID_KSM8995M:
|
||||||
|
printf("MICREL KS8995M\n");
|
||||||
|
break;
|
||||||
default:
|
default:
|
||||||
printf("0x%08x\n", phytype);
|
printf("0x%08x\n", phytype);
|
||||||
break;
|
break;
|
||||||
|
|
|
||||||
|
|
@ -227,9 +227,12 @@ static int smc_init (void)
|
||||||
sp->smc_smcm = 0;
|
sp->smc_smcm = 0;
|
||||||
sp->smc_smce = 0xff;
|
sp->smc_smce = 0xff;
|
||||||
|
|
||||||
/* Set up the baud rate generator.
|
#ifdef CFG_SPC1920_SMC1_CLK4 /* clock source is PLD */
|
||||||
*/
|
*((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0xff;
|
||||||
|
#else
|
||||||
|
/* Set up the baud rate generator */
|
||||||
smc_setbrg ();
|
smc_setbrg ();
|
||||||
|
#endif
|
||||||
|
|
||||||
/* Make the first buffer the only buffer.
|
/* Make the first buffer the only buffer.
|
||||||
*/
|
*/
|
||||||
|
|
|
||||||
|
|
@ -259,7 +259,11 @@ int get_clocks_866 (void)
|
||||||
*/
|
*/
|
||||||
sccr_reg = immr->im_clkrst.car_sccr;
|
sccr_reg = immr->im_clkrst.car_sccr;
|
||||||
sccr_reg &= ~SCCR_EBDF11;
|
sccr_reg &= ~SCCR_EBDF11;
|
||||||
|
#if defined(CONFIG_TQM885D)
|
||||||
|
if (gd->cpu_clk <= 80000000) {
|
||||||
|
#else
|
||||||
if (gd->cpu_clk <= 66000000) {
|
if (gd->cpu_clk <= 66000000) {
|
||||||
|
#endif
|
||||||
sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */
|
sccr_reg |= SCCR_EBDF00; /* bus division factor = 1 */
|
||||||
gd->bus_clk = gd->cpu_clk;
|
gd->bus_clk = gd->cpu_clk;
|
||||||
} else {
|
} else {
|
||||||
|
|
@ -360,7 +364,8 @@ static long init_pll_866 (long clk)
|
||||||
|
|
||||||
#endif /* CONFIG_8xx_CPUCLK_DEFAULT */
|
#endif /* CONFIG_8xx_CPUCLK_DEFAULT */
|
||||||
|
|
||||||
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
|
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
|
||||||
|
&& !defined(CONFIG_TQM885D)
|
||||||
/*
|
/*
|
||||||
* Adjust sdram refresh rate to actual CPU clock
|
* Adjust sdram refresh rate to actual CPU clock
|
||||||
* and set timebase source according to actual CPU clock
|
* and set timebase source according to actual CPU clock
|
||||||
|
|
@ -384,6 +389,6 @@ int adjust_sdram_tbs_8xx (void)
|
||||||
|
|
||||||
return (0);
|
return (0);
|
||||||
}
|
}
|
||||||
#endif /* CONFIG_TQM8xxL/M, !TQM866M */
|
#endif /* CONFIG_TQM8xxL/M, !TQM866M, !TQM885D */
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
|
||||||
|
|
@ -116,12 +116,13 @@ typedef void (interrupt_handler_t)(void *);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* enable common handling for all TQM8xxL/M boards:
|
* enable common handling for all TQM8xxL/M boards:
|
||||||
* - CONFIG_TQM8xxM will be defined for all TQM8xxM boards
|
* - CONFIG_TQM8xxM will be defined for all TQM8xxM and TQM885D boards
|
||||||
* - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards
|
* - CONFIG_TQM8xxL will be defined for all TQM8xxL _and_ TQM8xxM boards
|
||||||
*/
|
*/
|
||||||
#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \
|
#if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \
|
||||||
defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \
|
defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \
|
||||||
defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M)
|
defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M) || \
|
||||||
|
defined(CONFIG_TQM885D)
|
||||||
# ifndef CONFIG_TQM8xxM
|
# ifndef CONFIG_TQM8xxM
|
||||||
# define CONFIG_TQM8xxM
|
# define CONFIG_TQM8xxM
|
||||||
# endif
|
# endif
|
||||||
|
|
|
||||||
|
|
@ -1405,15 +1405,16 @@ typedef struct scc_enet {
|
||||||
|
|
||||||
#endif /* CONFIG_SXNI855T */
|
#endif /* CONFIG_SXNI855T */
|
||||||
|
|
||||||
/*** MVS1, TQM823L/M, TQM850L/M, ETX094, R360MPI *******************/
|
/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/
|
||||||
|
|
||||||
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
|
#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
|
||||||
defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
|
defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \
|
||||||
defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
|
defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \
|
||||||
defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
|
defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \
|
||||||
defined(CONFIG_ETX094) || defined(CONFIG_RRVISION)|| \
|
defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \
|
||||||
defined(CONFIG_VIRTLAB2)|| \
|
defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \
|
||||||
(defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
|
(defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
|
||||||
|
|
||||||
/* Bits in parallel I/O port registers that have to be set/cleared
|
/* Bits in parallel I/O port registers that have to be set/cleared
|
||||||
* to configure the pins for SCC2 use.
|
* to configure the pins for SCC2 use.
|
||||||
*/
|
*/
|
||||||
|
|
@ -1438,6 +1439,11 @@ typedef struct scc_enet {
|
||||||
*/
|
*/
|
||||||
#define SICR_ENET_MASK ((uint)0x0000ff00)
|
#define SICR_ENET_MASK ((uint)0x0000ff00)
|
||||||
#define SICR_ENET_CLKRT ((uint)0x00002600)
|
#define SICR_ENET_CLKRT ((uint)0x00002600)
|
||||||
|
|
||||||
|
# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */
|
||||||
|
#define FEC_ENET
|
||||||
|
# endif /* CONFIG_FEC_ENET */
|
||||||
|
|
||||||
#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
|
#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
|
||||||
|
|
||||||
/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/
|
/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/
|
||||||
|
|
|
||||||
492
include/configs/TQM885D.h
Normal file
492
include/configs/TQM885D.h
Normal file
|
|
@ -0,0 +1,492 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2000-2005
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* (C) Copyright 2006
|
||||||
|
* Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* board/config.h - configuration options, board specific
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CONFIG_H
|
||||||
|
#define __CONFIG_H
|
||||||
|
|
||||||
|
/*
|
||||||
|
* High Level Configuration Options
|
||||||
|
* (easy to change)
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CONFIG_MPC885 1 /* This is a MPC885 CPU */
|
||||||
|
#define CONFIG_TQM885D 1 /* ...on a TQM88D module */
|
||||||
|
|
||||||
|
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
|
||||||
|
#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
|
||||||
|
#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
|
||||||
|
#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 50 MHz - CPU default clock */
|
||||||
|
/* (it will be used if there is no */
|
||||||
|
/* 'cpuclk' variable with valid value) */
|
||||||
|
|
||||||
|
#define CFG_MEASURE_CPUCLK /* Measure real cpu clock */
|
||||||
|
/* (function measure_gclk() */
|
||||||
|
/* will be called) */
|
||||||
|
#ifdef CFG_MEASURE_CPUCLK
|
||||||
|
#define CFG_8XX_XIN 10000000 /* measure_gclk() needs this */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
|
||||||
|
|
||||||
|
#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
|
||||||
|
|
||||||
|
#define CONFIG_BOOTCOUNT_LIMIT
|
||||||
|
|
||||||
|
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||||
|
|
||||||
|
#define CONFIG_BOARD_TYPES 1 /* support board types */
|
||||||
|
|
||||||
|
#define CONFIG_PREBOOT "echo;" \
|
||||||
|
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
|
||||||
|
"echo"
|
||||||
|
|
||||||
|
#undef CONFIG_BOOTARGS
|
||||||
|
|
||||||
|
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||||
|
"netdev=eth0\0" \
|
||||||
|
"nfsargs=setenv bootargs root=/dev/nfs rw " \
|
||||||
|
"nfsroot=${serverip}:${rootpath}\0" \
|
||||||
|
"ramargs=setenv bootargs root=/dev/ram rw\0" \
|
||||||
|
"addip=setenv bootargs ${bootargs} " \
|
||||||
|
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
|
||||||
|
":${hostname}:${netdev}:off panic=1\0" \
|
||||||
|
"flash_nfs=run nfsargs addip;" \
|
||||||
|
"bootm ${kernel_addr}\0" \
|
||||||
|
"flash_self=run ramargs addip;" \
|
||||||
|
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
|
||||||
|
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
|
||||||
|
"rootpath=/opt/eldk/ppc_8xx\0" \
|
||||||
|
"bootfile=/tftpboot/TQM866M/uImage\0" \
|
||||||
|
"kernel_addr=40080000\0" \
|
||||||
|
"ramdisk_addr=40180000\0" \
|
||||||
|
""
|
||||||
|
#define CONFIG_BOOTCOMMAND "run flash_self"
|
||||||
|
|
||||||
|
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||||
|
#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
|
||||||
|
|
||||||
|
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||||
|
|
||||||
|
#define CONFIG_STATUS_LED 1 /* Status LED enabled */
|
||||||
|
|
||||||
|
#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
|
||||||
|
|
||||||
|
/* enable I2C and select the hardware/software driver */
|
||||||
|
#undef CONFIG_HARD_I2C /* I2C with hardware support */
|
||||||
|
#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
|
||||||
|
|
||||||
|
#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
|
||||||
|
#define CFG_I2C_SLAVE 0xFE
|
||||||
|
|
||||||
|
#ifdef CONFIG_SOFT_I2C
|
||||||
|
/*
|
||||||
|
* Software (bit-bang) I2C driver configuration
|
||||||
|
*/
|
||||||
|
#define PB_SCL 0x00000020 /* PB 26 */
|
||||||
|
#define PB_SDA 0x00000010 /* PB 27 */
|
||||||
|
|
||||||
|
#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
|
||||||
|
#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
|
||||||
|
#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
|
||||||
|
#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
|
||||||
|
#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
|
||||||
|
else immr->im_cpm.cp_pbdat &= ~PB_SDA
|
||||||
|
#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
|
||||||
|
else immr->im_cpm.cp_pbdat &= ~PB_SCL
|
||||||
|
#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
|
||||||
|
#endif /* CONFIG_SOFT_I2C */
|
||||||
|
|
||||||
|
#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */
|
||||||
|
#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */
|
||||||
|
#define CFG_EEPROM_PAGE_WRITE_BITS 4
|
||||||
|
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
|
||||||
|
|
||||||
|
# define CONFIG_RTC_DS1337 1
|
||||||
|
# define CFG_I2C_RTC_ADDR 0x68
|
||||||
|
|
||||||
|
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
|
||||||
|
|
||||||
|
#define CONFIG_MAC_PARTITION
|
||||||
|
#define CONFIG_DOS_PARTITION
|
||||||
|
|
||||||
|
#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
|
||||||
|
|
||||||
|
#define CONFIG_TIMESTAMP /* but print image timestmps */
|
||||||
|
|
||||||
|
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
|
||||||
|
CFG_CMD_ASKENV | \
|
||||||
|
CFG_CMD_DATE | \
|
||||||
|
CFG_CMD_DHCP | \
|
||||||
|
CFG_CMD_EEPROM | \
|
||||||
|
CFG_CMD_I2C | \
|
||||||
|
CFG_CMD_IDE | \
|
||||||
|
CFG_CMD_MII | \
|
||||||
|
CFG_CMD_NFS | \
|
||||||
|
CFG_CMD_PING )
|
||||||
|
|
||||||
|
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||||
|
#include <cmd_confdefs.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Miscellaneous configurable options
|
||||||
|
*/
|
||||||
|
#define CFG_LONGHELP /* undef to save memory */
|
||||||
|
#define CFG_PROMPT "=> " /* Monitor Command Prompt */
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
|
||||||
|
#endif
|
||||||
|
#ifdef CFG_HUSH_PARSER
|
||||||
|
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||||
|
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||||
|
#else
|
||||||
|
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||||
|
#endif
|
||||||
|
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
|
||||||
|
#define CFG_MAXARGS 16 /* max number of command args */
|
||||||
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||||
|
|
||||||
|
#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
|
||||||
|
#define CFG_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */
|
||||||
|
#define CFG_ALT_MEMTEST /* alternate, more extensive
|
||||||
|
memory test.*/
|
||||||
|
|
||||||
|
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||||
|
|
||||||
|
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||||
|
|
||||||
|
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Enable loopw commando. This has only effect, if CFG_CMD_MEM is defined,
|
||||||
|
* which is normally part of the default commands (CFV_CMD_DFL)
|
||||||
|
*/
|
||||||
|
#define CONFIG_LOOPW
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Low Level Configuration Settings
|
||||||
|
* (address mappings, register initial values, etc.)
|
||||||
|
* You should know what you are doing if you make changes here.
|
||||||
|
*/
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Internal Memory Mapped Register
|
||||||
|
*/
|
||||||
|
#define CFG_IMMR 0xFFF00000
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||||
|
*/
|
||||||
|
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||||
|
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
|
||||||
|
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
||||||
|
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||||
|
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Start addresses for the final memory configuration
|
||||||
|
* (Set up by the startup code)
|
||||||
|
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||||
|
*/
|
||||||
|
#define CFG_SDRAM_BASE 0x00000000
|
||||||
|
#define CFG_FLASH_BASE 0x40000000
|
||||||
|
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
|
||||||
|
#define CFG_MONITOR_BASE CFG_FLASH_BASE
|
||||||
|
#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* For booting Linux, the board info and command line data
|
||||||
|
* have to be in the first 8 MB of memory, since this is
|
||||||
|
* the maximum mapped by the Linux kernel during initialization.
|
||||||
|
*/
|
||||||
|
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* FLASH organization
|
||||||
|
*/
|
||||||
|
#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
|
||||||
|
#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
|
||||||
|
|
||||||
|
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||||
|
#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||||
|
|
||||||
|
#define CFG_ENV_IS_IN_FLASH 1
|
||||||
|
#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
|
||||||
|
#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
|
||||||
|
#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
|
||||||
|
|
||||||
|
/* Address and size of Redundant Environment Sector */
|
||||||
|
#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
|
||||||
|
#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Hardware Information Block
|
||||||
|
*/
|
||||||
|
#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
|
||||||
|
#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
|
||||||
|
#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Cache Configuration
|
||||||
|
*/
|
||||||
|
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||||
|
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* SYPCR - System Protection Control 11-9
|
||||||
|
* SYPCR can only be written once after reset!
|
||||||
|
*-----------------------------------------------------------------------
|
||||||
|
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||||
|
*/
|
||||||
|
#if defined(CONFIG_WATCHDOG)
|
||||||
|
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||||
|
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||||
|
#else
|
||||||
|
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* SIUMCR - SIU Module Configuration 11-6
|
||||||
|
*-----------------------------------------------------------------------
|
||||||
|
* PCMCIA config., multi-function pin tri-state
|
||||||
|
*/
|
||||||
|
#ifndef CONFIG_CAN_DRIVER
|
||||||
|
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
|
||||||
|
#else /* we must activate GPL5 in the SIUMCR for CAN */
|
||||||
|
#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
|
||||||
|
#endif /* CONFIG_CAN_DRIVER */
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* TBSCR - Time Base Status and Control 11-26
|
||||||
|
*-----------------------------------------------------------------------
|
||||||
|
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||||
|
*/
|
||||||
|
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||||
|
*-----------------------------------------------------------------------
|
||||||
|
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||||
|
*/
|
||||||
|
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* SCCR - System Clock and reset Control Register 15-27
|
||||||
|
*-----------------------------------------------------------------------
|
||||||
|
* Set clock output, timebase and RTC source and divider,
|
||||||
|
* power management and some other internal clocks
|
||||||
|
*/
|
||||||
|
#define SCCR_MASK SCCR_EBDF11
|
||||||
|
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||||
|
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||||
|
SCCR_DFALCD00)
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* PCMCIA stuff
|
||||||
|
*-----------------------------------------------------------------------
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
|
||||||
|
#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
|
||||||
|
#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
|
||||||
|
#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
|
||||||
|
#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
|
||||||
|
#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
|
||||||
|
#define CFG_PCMCIA_IO_ADDR (0xEC000000)
|
||||||
|
#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
|
||||||
|
*-----------------------------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
|
||||||
|
|
||||||
|
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||||
|
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||||
|
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
||||||
|
|
||||||
|
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||||
|
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
|
||||||
|
|
||||||
|
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||||
|
|
||||||
|
#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
|
||||||
|
|
||||||
|
/* Offset for data I/O */
|
||||||
|
#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
|
||||||
|
|
||||||
|
/* Offset for normal register accesses */
|
||||||
|
#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
|
||||||
|
|
||||||
|
/* Offset for alternate registers */
|
||||||
|
#define CFG_ATA_ALT_OFFSET 0x0100
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
*
|
||||||
|
*-----------------------------------------------------------------------
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define CFG_DER 0
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Init Memory Controller:
|
||||||
|
*
|
||||||
|
* BR0/1 and OR0/1 (FLASH)
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
|
||||||
|
#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
|
||||||
|
|
||||||
|
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||||
|
* restrict access enough to keep SRAM working (if any)
|
||||||
|
* but not too much to meddle with FLASH accesses
|
||||||
|
*/
|
||||||
|
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||||
|
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FLASH timing: Default value of OR0 after reset
|
||||||
|
*/
|
||||||
|
#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \
|
||||||
|
OR_SCY_6_CLK | OR_TRLX)
|
||||||
|
|
||||||
|
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||||
|
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||||
|
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
|
||||||
|
|
||||||
|
#define CFG_OR1_REMAP CFG_OR0_REMAP
|
||||||
|
#define CFG_OR1_PRELIM CFG_OR0_PRELIM
|
||||||
|
#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* BR2/3 and OR2/3 (SDRAM)
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
|
||||||
|
#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
|
||||||
|
#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */
|
||||||
|
|
||||||
|
/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
|
||||||
|
#define CFG_OR_TIMING_SDRAM 0x00000A00
|
||||||
|
|
||||||
|
#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
|
||||||
|
#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||||||
|
|
||||||
|
#ifndef CONFIG_CAN_DRIVER
|
||||||
|
#define CFG_OR3_PRELIM CFG_OR2_PRELIM
|
||||||
|
#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
|
||||||
|
#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
|
||||||
|
#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
|
||||||
|
#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
|
||||||
|
#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
|
||||||
|
#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
|
||||||
|
BR_PS_8 | BR_MS_UPMB | BR_V )
|
||||||
|
#endif /* CONFIG_CAN_DRIVER */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* 4096 Rows from SDRAM example configuration
|
||||||
|
* 1000 factor s -> ms
|
||||||
|
* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
|
||||||
|
* 4 Number of refresh cycles per period
|
||||||
|
* 64 Refresh cycle in ms per number of rows
|
||||||
|
*/
|
||||||
|
#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Memory Periodic Timer Prescaler
|
||||||
|
* Periodic timer for refresh, start with refresh rate for 40 MHz clock
|
||||||
|
* (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
|
||||||
|
*/
|
||||||
|
#define CFG_MAMR_PTA 39
|
||||||
|
|
||||||
|
/*
|
||||||
|
* For 16 MBit, refresh rates could be 31.3 us
|
||||||
|
* (= 64 ms / 2K = 125 / quad bursts).
|
||||||
|
* For a simpler initialization, 15.6 us is used instead.
|
||||||
|
*
|
||||||
|
* #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
|
||||||
|
* #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
|
||||||
|
*/
|
||||||
|
#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
|
||||||
|
#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
|
||||||
|
|
||||||
|
/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
|
||||||
|
#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
|
||||||
|
#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* MAMR settings for SDRAM
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* 8 column SDRAM */
|
||||||
|
#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||||
|
MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
|
||||||
|
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||||
|
/* 9 column SDRAM */
|
||||||
|
#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||||
|
MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
|
||||||
|
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||||
|
/* 10 column SDRAM */
|
||||||
|
#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
|
||||||
|
MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \
|
||||||
|
MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Internal Definitions
|
||||||
|
*
|
||||||
|
* Boot Flags
|
||||||
|
*/
|
||||||
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||||
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Network configuration
|
||||||
|
*/
|
||||||
|
#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */
|
||||||
|
#define CONFIG_FEC_ENET /* enable ethernet on FEC */
|
||||||
|
#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */
|
||||||
|
#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */
|
||||||
|
|
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_MII)
|
||||||
|
#define CFG_DISCOVER_PHY
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before
|
||||||
|
switching to another netwok (if the
|
||||||
|
tried network is unreachable) */
|
||||||
|
|
||||||
|
#define CONFIG_ETHPRIME "SCC ETHERNET"
|
||||||
|
|
||||||
|
#endif /* __CONFIG_H */
|
||||||
362
include/configs/spc1920.h
Normal file
362
include/configs/spc1920.h
Normal file
|
|
@ -0,0 +1,362 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2006
|
||||||
|
* Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
|
||||||
|
*
|
||||||
|
* Configuation settings for the SPC1920 board.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __H
|
||||||
|
#define __CONFIG_H
|
||||||
|
|
||||||
|
#define CONFIG_SPC1920 1 /* SPC1920 board */
|
||||||
|
#define CONFIG_MPC885 1 /* MPC885 CPU */
|
||||||
|
|
||||||
|
#define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
|
||||||
|
#undef CONFIG_8xx_CONS_SMC2
|
||||||
|
#undef CONFIG_8xx_CONS_NONE
|
||||||
|
|
||||||
|
#define CONFIG_MII
|
||||||
|
/* #define MII_DEBUG */
|
||||||
|
/* #define CONFIG_FEC_ENET */
|
||||||
|
#undef CONFIG_ETHER_ON_FEC1
|
||||||
|
#define CONFIG_ETHER_ON_FEC2
|
||||||
|
#define FEC_ENET
|
||||||
|
/* #define CONFIG_FEC2_PHY_NORXERR */
|
||||||
|
/* #define CFG_DISCOVER_PHY */
|
||||||
|
/* #define CONFIG_PHY_ADDR 0x1 */
|
||||||
|
#define CONFIG_FEC2_PHY 1
|
||||||
|
|
||||||
|
#define CONFIG_BAUDRATE 19200
|
||||||
|
|
||||||
|
/* use PLD CLK4 instead of brg */
|
||||||
|
#undef CFG_SPC1920_SMC1_CLK4
|
||||||
|
|
||||||
|
#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
|
||||||
|
#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
|
||||||
|
#define CFG_8xx_CPUCLK_MIN 40000000
|
||||||
|
#define CFG_8xx_CPUCLK_MAX 133000000
|
||||||
|
|
||||||
|
#define CFG_RESET_ADDRESS 0xf8000000
|
||||||
|
|
||||||
|
#define CONFIG_BOARD_EARLY_INIT_F
|
||||||
|
|
||||||
|
|
||||||
|
#if 1
|
||||||
|
#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
|
||||||
|
#else
|
||||||
|
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
|
#define CONFIG_NFSBOOTCOMMAND \
|
||||||
|
"dhcp;" \
|
||||||
|
"setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
|
||||||
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
|
||||||
|
"bootm"
|
||||||
|
|
||||||
|
#define CONFIG_BOOTCOMMAND \
|
||||||
|
"setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
|
||||||
|
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
|
||||||
|
"bootm fe080000"
|
||||||
|
|
||||||
|
#undef CONFIG_BOOTARGS
|
||||||
|
|
||||||
|
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||||
|
#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
|
||||||
|
|
||||||
|
#ifndef CONFIG_COMMANDS
|
||||||
|
#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
|
||||||
|
| CFG_CMD_ASKENV \
|
||||||
|
| CFG_CMD_ECHO \
|
||||||
|
| CFG_CMD_IMMAP \
|
||||||
|
| CFG_CMD_JFFS2 \
|
||||||
|
| CFG_CMD_PING \
|
||||||
|
| CFG_CMD_DHCP \
|
||||||
|
| CFG_CMD_IMMAP \
|
||||||
|
| CFG_CMD_MII)
|
||||||
|
/* & ~( CFG_CMD_NET)) */
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* !CONFIG_COMMANDS */
|
||||||
|
|
||||||
|
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||||
|
#include <cmd_confdefs.h>
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Miscellaneous configurable options
|
||||||
|
*/
|
||||||
|
#define CFG_LONGHELP /* undef to save memory */
|
||||||
|
#define CFG_PROMPT "=>" /* Monitor Command Prompt */
|
||||||
|
#define CFG_HUSH_PARSER
|
||||||
|
#define CFG_PROMPT_HUSH_PS2 "> "
|
||||||
|
|
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
|
||||||
|
#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||||
|
#else
|
||||||
|
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size */
|
||||||
|
#define CFG_MAXARGS 16 /* max number of command args */
|
||||||
|
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
|
||||||
|
|
||||||
|
#define CFG_LOAD_ADDR 0x00100000
|
||||||
|
|
||||||
|
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||||
|
|
||||||
|
#define CFG_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 }
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Low Level Configuration Settings
|
||||||
|
* (address mappings, register initial values, etc.)
|
||||||
|
* You should know what you are doing if you make changes here.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Internal Memory Mapped Register
|
||||||
|
*/
|
||||||
|
#define CFG_IMMR 0xF0000000
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Definitions for initial stack pointer and data area (in DPRAM)
|
||||||
|
*/
|
||||||
|
#define CFG_INIT_RAM_ADDR CFG_IMMR
|
||||||
|
#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
|
||||||
|
#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
|
||||||
|
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
|
||||||
|
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Start addresses for the final memory configuration
|
||||||
|
* (Set up by the startup code)
|
||||||
|
* Please note that CFG_SDRAM_BASE _must_ start at 0
|
||||||
|
*/
|
||||||
|
#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
|
||||||
|
#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* For booting Linux, the board info and command line data
|
||||||
|
* have to be in the first 8 MB of memory, since this is
|
||||||
|
* the maximum mapped by the Linux kernel during initialization.
|
||||||
|
*/
|
||||||
|
#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
|
||||||
|
|
||||||
|
#define CFG_MONITOR_BASE TEXT_BASE
|
||||||
|
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
|
||||||
|
|
||||||
|
#ifdef CONFIG_BZIP2
|
||||||
|
#define CFG_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
|
||||||
|
#else
|
||||||
|
#define CFG_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
|
||||||
|
#endif /* CONFIG_BZIP2 */
|
||||||
|
|
||||||
|
#define CFG_ALLOC_DPRAM 1 /* use allocation routines */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Flash
|
||||||
|
*/
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Flash organisation
|
||||||
|
*/
|
||||||
|
#define CFG_FLASH_BASE 0xFE000000
|
||||||
|
#define CFG_FLASH_CFI /* The flash is CFI compatible */
|
||||||
|
#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
|
||||||
|
#define CFG_MAX_FLASH_BANKS 1 /* Max number of flash banks */
|
||||||
|
#define CFG_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
|
||||||
|
|
||||||
|
/* Environment is in flash */
|
||||||
|
#define CFG_ENV_IS_IN_FLASH
|
||||||
|
#define CFG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
|
||||||
|
#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
|
||||||
|
|
||||||
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* Cache Configuration
|
||||||
|
*/
|
||||||
|
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
|
||||||
|
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* I2C configuration
|
||||||
|
*/
|
||||||
|
#if (CONFIG_COMMANDS & CFG_CMD_I2C)
|
||||||
|
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
|
||||||
|
#define CFG_I2C_SPEED 400000 /* I2C speed and slave address defaults */
|
||||||
|
#define CFG_I2C_SLAVE 0x7F
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* SYPCR - System Protection Control 11-9
|
||||||
|
* SYPCR can only be written once after reset!
|
||||||
|
*-----------------------------------------------------------------------
|
||||||
|
* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
|
||||||
|
*/
|
||||||
|
#if defined(CONFIG_WATCHDOG)
|
||||||
|
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
|
||||||
|
SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
|
||||||
|
#else
|
||||||
|
#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* SIUMCR - SIU Module Configuration 11-6
|
||||||
|
*-----------------------------------------------------------------------
|
||||||
|
* PCMCIA config., multi-function pin tri-state
|
||||||
|
*/
|
||||||
|
#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* TBSCR - Time Base Status and Control 11-26
|
||||||
|
*-----------------------------------------------------------------------
|
||||||
|
* Clear Reference Interrupt Status, Timebase freezing enabled
|
||||||
|
*/
|
||||||
|
#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* PISCR - Periodic Interrupt Status and Control 11-31
|
||||||
|
*-----------------------------------------------------------------------
|
||||||
|
* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
|
||||||
|
*/
|
||||||
|
#define CFG_PISCR (PISCR_PS | PISCR_PITF)
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* SCCR - System Clock and reset Control Register 15-27
|
||||||
|
*-----------------------------------------------------------------------
|
||||||
|
* Set clock output, timebase and RTC source and divider,
|
||||||
|
* power management and some other internal clocks
|
||||||
|
*/
|
||||||
|
#define SCCR_MASK SCCR_EBDF11
|
||||||
|
/* #define CFG_SCCR SCCR_TBS */
|
||||||
|
#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
|
||||||
|
SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
|
||||||
|
SCCR_DFALCD00)
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------
|
||||||
|
* DER - Debug Enable Register
|
||||||
|
*-----------------------------------------------------------------------
|
||||||
|
* Set to zero to prevent the processor from entering debug mode
|
||||||
|
*/
|
||||||
|
#define CFG_DER 0
|
||||||
|
|
||||||
|
|
||||||
|
/* Because of the way the 860 starts up and assigns CS0 the entire
|
||||||
|
* address space, we have to set the memory controller differently.
|
||||||
|
* Normally, you write the option register first, and then enable the
|
||||||
|
* chip select by writing the base register. For CS0, you must write
|
||||||
|
* the base register first, followed by the option register.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Init Memory Controller:
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* BR0 and OR0 (FLASH) */
|
||||||
|
#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
|
||||||
|
|
||||||
|
|
||||||
|
/* used to re-map FLASH both when starting from SRAM or FLASH:
|
||||||
|
* restrict access enough to keep SRAM working (if any)
|
||||||
|
* but not too much to meddle with FLASH accesses
|
||||||
|
*/
|
||||||
|
#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
|
||||||
|
#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* FLASH timing:
|
||||||
|
*/
|
||||||
|
#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
|
||||||
|
OR_SCY_3_CLK | OR_EHTR | OR_BI)
|
||||||
|
|
||||||
|
#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
|
||||||
|
#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
|
||||||
|
#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* SDRAM CS1 UPMB
|
||||||
|
*/
|
||||||
|
#define CFG_SDRAM_BASE 0x00000000
|
||||||
|
#define CFG_SDRAM_BASE_PRELIM CFG_SDRAM_BASE
|
||||||
|
#define SDRAM_MAX_SIZE 0x4000000 /* max 64 MB */
|
||||||
|
|
||||||
|
#define CFG_PRELIM_OR1_AM 0xF0000000
|
||||||
|
/* #define CFG_OR1_TIMING OR_CSNT_SAM/\* | OR_G5LS /\\* *\\/ *\/ */
|
||||||
|
#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
|
||||||
|
|
||||||
|
#define CFG_OR1_PRELIM (CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
|
||||||
|
#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)
|
||||||
|
|
||||||
|
/* #define CFG_OR1_FINAL ((CFG_OR1_AM & OR_AM_MSK) | CFG_OR1_TIMING) */
|
||||||
|
/* #define CFG_BR1_FINAL ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */
|
||||||
|
|
||||||
|
#define CFG_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64))
|
||||||
|
#define CFG_PTA_PER_CLK 195
|
||||||
|
#define CFG_MBMR_PTB 195
|
||||||
|
#define CFG_MPTPR MPTPR_PTP_DIV16
|
||||||
|
#define CFG_MAR 0x88
|
||||||
|
|
||||||
|
#define CFG_MBMR_8COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
|
||||||
|
MBMR_AMB_TYPE_0 | \
|
||||||
|
MBMR_G0CLB_A10 | \
|
||||||
|
MBMR_DSB_1_CYCL | \
|
||||||
|
MBMR_RLFB_1X | \
|
||||||
|
MBMR_WLFB_1X | \
|
||||||
|
MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
|
||||||
|
|
||||||
|
#define CFG_MBMR_9COL ((CFG_MBMR_PTB << MBMR_PTB_SHIFT) | \
|
||||||
|
MBMR_AMB_TYPE_1 | \
|
||||||
|
MBMR_G0CLB_A10 | \
|
||||||
|
MBMR_DSB_1_CYCL | \
|
||||||
|
MBMR_RLFB_1X | \
|
||||||
|
MBMR_WLFB_1X | \
|
||||||
|
MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */
|
||||||
|
|
||||||
|
|
||||||
|
/* PLD CS5 */
|
||||||
|
#define CFG_SPC1920_PLD_BASE 0x80000000
|
||||||
|
#define CFG_PRELIM_OR5_AM 0xffff8000
|
||||||
|
|
||||||
|
#define CFG_OR5_PRELIM (CFG_PRELIM_OR5_AM | \
|
||||||
|
OR_CSNT_SAM | \
|
||||||
|
OR_ACS_DIV1 | \
|
||||||
|
OR_BI | \
|
||||||
|
OR_SCY_0_CLK | \
|
||||||
|
OR_TRLX)
|
||||||
|
|
||||||
|
#define CFG_BR5_PRELIM ((CFG_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
|
||||||
|
|
||||||
|
/* #define CFG_PLD_BASE 0x30000000 */
|
||||||
|
/* #define CFG_OR5_PRELIM 0xffff1110 */
|
||||||
|
/* #define CFG_BR5_PRELIM 0x30000401 */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Internal Definitions
|
||||||
|
*
|
||||||
|
* Boot Flags
|
||||||
|
*/
|
||||||
|
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
|
||||||
|
#define BOOTFLAG_WARM 0x02 /* Software reboot */
|
||||||
|
|
||||||
|
/* Machine type
|
||||||
|
*/
|
||||||
|
#define _MACH_8xx (_MACH_fads)
|
||||||
|
|
||||||
|
#endif /* __CONFIG_H */
|
||||||
|
|
@ -270,7 +270,8 @@ init_fnc_t *init_sequence[] = {
|
||||||
|
|
||||||
#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
|
#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
|
||||||
get_clocks, /* get CPU and bus clocks (etc.) */
|
get_clocks, /* get CPU and bus clocks (etc.) */
|
||||||
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
|
#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \
|
||||||
|
&& !defined(CONFIG_TQM885D)
|
||||||
adjust_sdram_tbs_8xx,
|
adjust_sdram_tbs_8xx,
|
||||||
#endif
|
#endif
|
||||||
init_timebase,
|
init_timebase,
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue