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https://github.com/AsahiLinux/u-boot
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Makefile: prepare for using Kbuild-style Makefile
Every makefile in sub directories has common lines
at the top and the bottom.
This commit pushes the common parts into script/Makefile.build.
Going forward sub-makefiles only need to describe this part:
COBJS := ...
COBJS += ...
SOBJS := ...
But using obj-y is preferable to prepare for switching to Kbuild.
The conventional (non-Kbuild) Makefile style is still supported.
This is achieved by greping the Makefile before entering into it.
U-Boot conventional sub makefiles always include some other makefiles.
So the build system searches a line beginning with "include" keyword
in the makefile in order to distinguish which style it is.
If the Makefile include a "include" line, we assume it is a conventional
U-Boot style. Otherwise, it is treated as a Kbuild-style makefile.
With this tweak, we can switch sub-makefiles
from U-Boot style to Kbuild style little by little.
obj-y := foo/
syntax (descending into the sub directory) is not supportd yet.
It will be implemented in the upcomming commit.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@ti.com>
This commit is contained in:
Masahiro Yamada
Tom Rini
parent
9d33fb4a5c
commit
ce28d7ac6d
3 changed files with 99 additions and 7 deletions
36
Makefile
36
Makefile
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@ -595,14 +595,32 @@ ifeq ($(CONFIG_KALLSYMS),y)
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$(GEN_UBOOT) $(obj)common/system_map.o
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endif
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# Tentative step for Kbuild-style makefiles coexist with conventional U-Boot style makefiles
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# U-Boot conventional sub makefiles always include some other makefiles.
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# So, the build system searches a line beginning with "include" before entering into the sub makefile
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# in order to distinguish which style it is.
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# If the Makefile include a "include" line, we assume it is an U-Boot style makefile.
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# Otherwise, it is treated as a Kbuild-style makefile.
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select_makefile = \
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+if grep -q "^include" $1/Makefile; then \
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$(MAKE) -C $1; \
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else \
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$(MAKE) -C $1 -f $(TOPDIR)/scripts/Makefile.build; \
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mv $(dir $@)built-in.o $@; \
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fi
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# We do not need to build $(OBJS) explicitly.
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# It is built while we are at $(CPUDIR)/lib$(CPU).o build.
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$(OBJS): depend
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$(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@))
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if grep -q "^include" $(CPUDIR)/Makefile; then \
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$(MAKE) -C $(CPUDIR) $(if $(REMOTE_BUILD),$@,$(notdir $@)); \
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fi
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$(LIBS): depend $(SUBDIR_TOOLS)
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$(MAKE) -C $(dir $(subst $(obj),,$@))
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+$(call select_makefile, $(dir $(subst $(obj),,$@)))
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$(LIBBOARD): depend $(LIBS)
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$(MAKE) -C $(dir $(subst $(obj),,$@))
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+$(call select_makefile, $(dir $(subst $(obj),,$@)))
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$(SUBDIRS): depend
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$(MAKE) -C $@ all
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@ -630,6 +648,13 @@ $(obj)tpl/u-boot-tpl.bin: $(SUBDIR_TOOLS) depend
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updater:
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$(MAKE) -C tools/updater all
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select_makefile2 = \
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if grep -q "^include" $1/Makefile; then \
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$(MAKE) -C $1 _depend; \
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else \
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$(MAKE) -C $1 -f $(TOPDIR)/scripts/Makefile.build _depend; \
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fi
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# Explicitly make _depend in subdirs containing multiple targets to prevent
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# parallel sub-makes creating .depend files simultaneously.
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depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \
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@ -638,8 +663,9 @@ depend dep: $(TIMESTAMP_FILE) $(VERSION_FILE) \
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$(obj)include/autoconf.mk \
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$(obj)include/generated/generic-asm-offsets.h \
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$(obj)include/generated/asm-offsets.h
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for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \
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$(MAKE) -C $$dir _depend ; done
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+for dir in $(SUBDIRS) $(CPUDIR) $(LDSCRIPT_MAKEFILE_DIR) ; do \
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$(call select_makefile2, $$dir); \
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done
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TAG_SUBDIRS = $(SUBDIRS)
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TAG_SUBDIRS += $(dir $(__LIBS))
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48
scripts/Makefile.build
Normal file
48
scripts/Makefile.build
Normal file
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@ -0,0 +1,48 @@
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# our default target
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.PHONY: all
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all:
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include $(TOPDIR)/config.mk
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LIB := $(obj)built-in.o
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LIBGCC = $(obj)libgcc.o
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SRCS :=
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include Makefile
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# Backward compatible: obj-y is preferable
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COBJS := $(sort $(COBJS) $(COBJS-y))
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SOBJS := $(sort $(SOBJS) $(SOBJS-y))
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# Going forward use the following
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obj-y := $(sort $(obj-y))
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extra-y := $(sort $(extra-y))
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lib-y := $(sort $(lib-y))
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SRCS += $(COBJS:.o=.c) $(SOBJS:.o=.S) \
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$(wildcard $(obj-y:.o=.c) $(obj-y:.o=.S) $(lib-y:.o=.c) $(lib-y:.o=.S) $(extra-y:.o=.c) $(extra-y:.o=.S))
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OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS) $(obj-y))
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LGOBJS := $(addprefix $(obj),$(sort $(GLSOBJS) $(GLCOBJS)) $(lib-y))
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all: $(LIB) $(addprefix $(obj),$(extra-y))
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$(LIB): $(obj).depend $(OBJS)
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$(call cmd_link_o_target, $(OBJS))
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ifneq ($(strip $(lib-y)),)
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all: $(LIBGCC)
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$(LIBGCC): $(obj).depend $(LGOBJS)
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$(call cmd_link_o_target, $(LGOBJS))
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endif
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#########################################################################
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# defines $(obj).depend target
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include $(TOPDIR)/rules.mk
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sinclude $(obj).depend
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#########################################################################
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22
spl/Makefile
22
spl/Makefile
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@ -200,11 +200,29 @@ GEN_UBOOT = \
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$(obj)$(SPL_BIN): depend $(START) $(LIBS) $(obj)u-boot-spl.lds
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$(GEN_UBOOT)
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# Tentative step for Kbuild-style makefiles coexist with conventional U-Boot style makefiles
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# U-Boot conventional sub makefiles always include some other makefiles.
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# So, the build system searches a line beginning with "include" before entering into the sub makefile
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# in order to distinguish which style it is.
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# If the Makefile include a "include" line, we assume it is an U-Boot style makefile.
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# Otherwise, it is treated as a Kbuild-style makefile.
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select_makefile = \
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if grep -q "^include" $1/Makefile; then \
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$(MAKE) -C $1; \
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else \
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$(MAKE) -C $1 -f $(TOPDIR)/scripts/Makefile.build; \
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mv $(dir $@)built-in.o $@; \
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fi
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# We do not need to build $(START) explicitly.
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# It is built while we are at $(CPUDIR)/lib$(CPU).o build.
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$(START): depend
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$(MAKE) -C $(SRCTREE)/$(START_PATH) $@
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if grep -q "^include" $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))Makefile; then \
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$(MAKE) -C $(SRCTREE)/$(START_PATH) $@; \
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fi
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$(LIBS): depend
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$(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))
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+$(call select_makefile, $(SRCTREE)$(dir $(subst $(SPLTREE),,$@)))
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$(obj)u-boot-spl.lds: $(LDSCRIPT) depend
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$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@
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