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clk: rockchip: rk3588: support aclk_top_root set 750M

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aclk_top_root choose a parent clock that does not change.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
This commit is contained in:
Elaine Zhang 2023-10-11 18:29:45 +08:00 • committed by Kever Yang
parent 39fb8acac4
commit cdf21a8696
1 changed files with 8 additions and 2 deletions
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10
drivers/clk/rockchip/clk_rk3588.c
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@ -306,12 +306,18 @@ static ulong rk3588_top_set_clk(struct rk3588_clk_priv *priv,
switch (clk_id) {
case ACLK_TOP_ROOT:
src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
if (!(priv->cpll_hz % rate)) {
src_clk = ACLK_TOP_ROOT_SRC_SEL_CPLL;
src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
} else {
src_clk = ACLK_TOP_ROOT_SRC_SEL_GPLL;
src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
}
assert(src_clk_div - 1 <= 31);
rk_clrsetreg(&cru->clksel_con[8],
ACLK_TOP_ROOT_DIV_MASK |
ACLK_TOP_ROOT_SRC_SEL_MASK,
(ACLK_TOP_ROOT_SRC_SEL_GPLL <<
(src_clk <<
ACLK_TOP_ROOT_SRC_SEL_SHIFT) |
(src_clk_div - 1) << ACLK_TOP_ROOT_DIV_SHIFT);
break;