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https://github.com/AsahiLinux/u-boot
synced 2024-09-29 02:42:16 +00:00
sunxi: cosmetic: Fix H616 DRAM driver code style
Fix code style for pointer declaration. This is just cosmetic change to avoid checkpatch errors in later commits. Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Jernej Skrabec
Andre Przywara
parent
7230bebfe3
commit
cdb5aadd59
1 changed files with 37 additions and 37 deletions
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@ -285,7 +285,7 @@ static bool mctl_phy_write_leveling(struct dram_para *para)
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else
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val = 3;
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mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x188), val, val);
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mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x188), val, val);
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clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4);
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@ -314,7 +314,7 @@ static bool mctl_phy_write_leveling(struct dram_para *para)
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else
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val = 3;
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mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x188), val, val);
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mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x188), val, val);
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clrbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 4);
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}
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@ -398,26 +398,26 @@ static bool mctl_phy_read_training(struct dram_para *para)
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setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 6);
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setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 1);
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mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x840), 0xc, 0xc);
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mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x840), 0xc, 0xc);
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if (readl(SUNXI_DRAM_PHY0_BASE + 0x840) & 3)
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result = false;
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if (para->bus_full_width) {
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mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0xa40), 0xc, 0xc);
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mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa40), 0xc, 0xc);
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if (readl(SUNXI_DRAM_PHY0_BASE + 0xa40) & 3)
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result = false;
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}
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ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x898);
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ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x850);
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ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x898);
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ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x850);
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for (i = 0; i < 9; i++) {
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val1 = readl(&ptr1[i]);
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val2 = readl(&ptr2[i]);
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if (val1 - val2 <= 6)
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result = false;
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}
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ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x8bc);
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ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x874);
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ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8bc);
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ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x874);
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for (i = 0; i < 9; i++) {
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val1 = readl(&ptr1[i]);
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val2 = readl(&ptr2[i]);
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@ -426,8 +426,8 @@ static bool mctl_phy_read_training(struct dram_para *para)
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}
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if (para->bus_full_width) {
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ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xa98);
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ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xa50);
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ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa98);
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ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa50);
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for (i = 0; i < 9; i++) {
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val1 = readl(&ptr1[i]);
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val2 = readl(&ptr2[i]);
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@ -435,8 +435,8 @@ static bool mctl_phy_read_training(struct dram_para *para)
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result = false;
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}
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ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xabc);
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ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xa74);
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ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xabc);
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ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa74);
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for (i = 0; i < 9; i++) {
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val1 = readl(&ptr1[i]);
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val2 = readl(&ptr2[i]);
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@ -454,12 +454,12 @@ static bool mctl_phy_read_training(struct dram_para *para)
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setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 6);
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setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 1);
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mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x840), 0xc, 0xc);
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mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x840), 0xc, 0xc);
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if (readl(SUNXI_DRAM_PHY0_BASE + 0x840) & 3)
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result = false;
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if (para->bus_full_width) {
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mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0xa40), 0xc, 0xc);
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mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xa40), 0xc, 0xc);
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if (readl(SUNXI_DRAM_PHY0_BASE + 0xa40) & 3)
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result = false;
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}
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@ -488,26 +488,26 @@ static bool mctl_phy_write_training(struct dram_para *para)
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setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
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setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x20);
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mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x8e0), 3, 3);
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mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8e0), 3, 3);
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if (readl(SUNXI_DRAM_PHY0_BASE + 0x8e0) & 0xc)
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result = false;
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if (para->bus_full_width) {
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mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0xae0), 3, 3);
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mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xae0), 3, 3);
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if (readl(SUNXI_DRAM_PHY0_BASE + 0xae0) & 0xc)
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result = false;
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}
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ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x938);
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ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x8f0);
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ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x938);
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ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8f0);
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for (i = 0; i < 9; i++) {
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val1 = readl(&ptr1[i]);
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val2 = readl(&ptr2[i]);
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if (val1 - val2 <= 6)
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result = false;
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}
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ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x95c);
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ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x914);
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ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x95c);
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ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x914);
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for (i = 0; i < 9; i++) {
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val1 = readl(&ptr1[i]);
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val2 = readl(&ptr2[i]);
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@ -516,16 +516,16 @@ static bool mctl_phy_write_training(struct dram_para *para)
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}
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if (para->bus_full_width) {
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ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xb38);
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ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xaf0);
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ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xb38);
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ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xaf0);
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for (i = 0; i < 9; i++) {
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val1 = readl(&ptr1[i]);
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val2 = readl(&ptr2[i]);
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if (val1 - val2 <= 6)
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result = false;
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}
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ptr1 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xb5c);
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ptr2 = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xb14);
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ptr1 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xb5c);
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ptr2 = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xb14);
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for (i = 0; i < 9; i++) {
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val1 = readl(&ptr1[i]);
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val2 = readl(&ptr2[i]);
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@ -542,12 +542,12 @@ static bool mctl_phy_write_training(struct dram_para *para)
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setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
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setbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x20);
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mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x8e0), 3, 3);
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mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x8e0), 3, 3);
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if (readl(SUNXI_DRAM_PHY0_BASE + 0x8e0) & 0xc)
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result = false;
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if (para->bus_full_width) {
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mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0xae0), 3, 3);
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mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0xae0), 3, 3);
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if (readl(SUNXI_DRAM_PHY0_BASE + 0xae0) & 0xc)
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result = false;
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}
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@ -569,7 +569,7 @@ static bool mctl_phy_bit_delay_compensation(struct dram_para *para)
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setbits_le32(SUNXI_DRAM_PHY0_BASE + 8, 8);
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clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 0x10);
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ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x484);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x484);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x16, ptr);
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writel_relaxed(0x16, ptr + 0x30);
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@ -580,7 +580,7 @@ static bool mctl_phy_bit_delay_compensation(struct dram_para *para)
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x4cc);
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writel_relaxed(0x1c, SUNXI_DRAM_PHY0_BASE + 0x58c);
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ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x4d8);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d8);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x1a, ptr);
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writel_relaxed(0x1a, ptr + 0x30);
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@ -591,7 +591,7 @@ static bool mctl_phy_bit_delay_compensation(struct dram_para *para)
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x520);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x5e0);
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ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x604);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x604);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x1a, ptr);
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writel_relaxed(0x1a, ptr + 0x30);
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@ -602,7 +602,7 @@ static bool mctl_phy_bit_delay_compensation(struct dram_para *para)
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x64c);
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writel_relaxed(0x1e, SUNXI_DRAM_PHY0_BASE + 0x70c);
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ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x658);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x658);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x1a, ptr);
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writel_relaxed(0x1a, ptr + 0x30);
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@ -621,7 +621,7 @@ static bool mctl_phy_bit_delay_compensation(struct dram_para *para)
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clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x54, 0x80);
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clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x190, 4);
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ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x480);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x480);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x10, ptr);
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writel_relaxed(0x10, ptr + 0x30);
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@ -632,7 +632,7 @@ static bool mctl_phy_bit_delay_compensation(struct dram_para *para)
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writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x4c8);
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writel_relaxed(0x18, SUNXI_DRAM_PHY0_BASE + 0x588);
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ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x4d4);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x4d4);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x12, ptr);
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writel_relaxed(0x12, ptr + 0x30);
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@ -643,7 +643,7 @@ static bool mctl_phy_bit_delay_compensation(struct dram_para *para)
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x51c);
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x5dc);
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ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x600);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x600);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x12, ptr);
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writel_relaxed(0x12, ptr + 0x30);
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@ -654,7 +654,7 @@ static bool mctl_phy_bit_delay_compensation(struct dram_para *para)
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x648);
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writel_relaxed(0x1a, SUNXI_DRAM_PHY0_BASE + 0x708);
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ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x654);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x654);
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for (i = 0; i < 9; i++) {
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writel_relaxed(0x14, ptr);
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writel_relaxed(0x14, ptr + 0x30);
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@ -702,12 +702,12 @@ static bool mctl_phy_init(struct dram_para *para)
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writel(9, SUNXI_DRAM_PHY0_BASE + 0x370);
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writel(9, SUNXI_DRAM_PHY0_BASE + 0x37c);
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ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0xc0);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xc0);
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for (i = 0; i < ARRAY_SIZE(phy_init); i++)
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writel(phy_init[i], &ptr[i]);
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if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_UNKNOWN_FEATURE)) {
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ptr = (u32*)(SUNXI_DRAM_PHY0_BASE + 0x780);
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ptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0x780);
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for (i = 0; i < 32; i++)
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writel(0x16, &ptr[i]);
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writel(0xe, SUNXI_DRAM_PHY0_BASE + 0x78c);
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@ -738,7 +738,7 @@ static bool mctl_phy_init(struct dram_para *para)
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clrbits_le32(SUNXI_DRAM_PHY0_BASE + 0x14c, 8);
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mctl_await_completion((u32*)(SUNXI_DRAM_PHY0_BASE + 0x180), 4, 4);
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mctl_await_completion((u32 *)(SUNXI_DRAM_PHY0_BASE + 0x180), 4, 4);
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writel(0x37, SUNXI_DRAM_PHY0_BASE + 0x58);
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clrbits_le32(&mctl_com->unk_0x500, 0x200);
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