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https://github.com/AsahiLinux/u-boot
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Coldfire MCF5249 support added
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stroese
parent
e2c22d780e
commit
cd42deebd2
5 changed files with 323 additions and 1 deletions
43
include/asm-m68k/immap_5249.h
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43
include/asm-m68k/immap_5249.h
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@ -0,0 +1,43 @@
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/*
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* MCF5249 Internal Memory Map
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*
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* Copyright (c) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __IMMAP_5249__
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#define __IMMAP_5249__
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/* Timer module registers
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*/
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typedef struct timer_ctrl {
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ushort timer_tmr;
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ushort res1;
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ushort timer_trr;
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ushort res2;
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ushort timer_tcap;
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ushort res3;
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ushort timer_tcn;
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ushort res4;
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ushort timer_ter;
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uchar res5[14];
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} timer_t;
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#endif /* __IMMAP_5249__ */
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189
include/asm-m68k/m5249.h
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189
include/asm-m68k/m5249.h
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@ -0,0 +1,189 @@
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/*
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* mcf5249.h -- Definitions for Motorola Coldfire 5249
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*
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* Based on mcf5272sim.h of uCLinux distribution:
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* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
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* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef mcf5249_h
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#define mcf5249_h
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/****************************************************************************/
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/*
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* useful definitions for reading/writing MBAR offset memory
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*/
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#define mbar_readLong(x) *((volatile unsigned long *) (CFG_MBAR + x))
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#define mbar_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR + x)) = y
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#define mbar_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR + x)) = y
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#define mbar_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR + x)) = y
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#define mbar2_readLong(x) *((volatile unsigned long *) (CFG_MBAR2 + x))
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#define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_MBAR2 + x)) = y
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#define mbar2_writeShort(x,y) *((volatile unsigned short *) (CFG_MBAR2 + x)) = y
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#define mbar2_writeByte(x,y) *((volatile unsigned char *) (CFG_MBAR2 + x)) = y
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/*
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* Size of internal RAM
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*/
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#define INT_RAM_SIZE 32768 /* RAMBAR0 - 32k */
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#define INT_RAM_SIZE2 65536 /* RAMBAR1 - 64k */
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/*
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* Define the 5249 SIM register set addresses.
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*/
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/*****************
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***** MBAR1 *****
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*****************/
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#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */
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#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w)*/
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#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */
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#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */
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#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */
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#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */
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#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */
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#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */
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#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */
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#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */
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#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */
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#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */
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#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */
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#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */
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#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */
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#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */
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#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */
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#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */
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#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */
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#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */
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#define MCFSIM_CSAR0 0x80 /* CS 0 Address 0 reg (r/w) */
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#define MCFSIM_CSMR0 0x84 /* CS 0 Mask 0 reg (r/w) */
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#define MCFSIM_CSCR0 0x8a /* CS 0 Control reg (r/w) */
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#define MCFSIM_CSAR1 0x8c /* CS 1 Address reg (r/w) */
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#define MCFSIM_CSMR1 0x90 /* CS 1 Mask reg (r/w) */
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#define MCFSIM_CSCR1 0x96 /* CS 1 Control reg (r/w) */
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#define MCFSIM_CSAR2 0x98 /* CS 2 Address reg (r/w) */
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#define MCFSIM_CSMR2 0x9c /* CS 2 Mask reg (r/w) */
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#define MCFSIM_CSCR2 0xa2 /* CS 2 Control reg (r/w) */
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#define MCFSIM_CSAR3 0xa4 /* CS 3 Address reg (r/w) */
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#define MCFSIM_CSMR3 0xa8 /* CS 3 Mask reg (r/w) */
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#define MCFSIM_CSCR3 0xae /* CS 3 Control reg (r/w) */
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#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */
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#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */
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#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */
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#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */
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#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */
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/** UART Bases **/
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#define MCFUART_BASE1 0x1c0 /* Base address of UART1 */
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#define MCFUART_BASE2 0x200 /* Base address of UART2 */
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/*****************
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***** MBAR2 *****
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*****************/
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/* GPIO Addresses
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* Note: These are offset from MBAR2!
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*/
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#define MCFSIM_GPIO_READ 0x00 /* Read-Only access to gpio 0-31 (MBAR2) (r) */
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#define MCFSIM_GPIO_OUT 0x04 /* Output register for gpio 0-31 (MBAR2) (r/w)*/
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#define MCFSIM_GPIO_EN 0x08 /* gpio 0-31 enable (r/w)*/
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#define MCFSIM_GPIO_FUNC 0x0c /* gpio 0-31 function select (r/w) */
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#define MCFSIM_GPIO1_READ 0xb0 /* Read-Only access to gpio 32-63 (MBAR2) (r) */
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#define MCFSIM_GPIO1_OUT 0xb4 /* Output register for gpio 32-63 (MBAR2) (r/w) */
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#define MCFSIM_GPIO1_EN 0xb8 /* gpio 32-63 enable (r/w) */
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#define MCFSIM_GPIO1_FUNC 0xbc /* gpio 32-63 function select (r/w) */
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#define MCFSIM_GPIO_INT_STAT 0xc0 /* Secondary Interrupt status (r) */
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#define MCFSIM_GPIO_INT_CLEAR 0xc0 /* Secondary Interrupt status (w) */
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#define MCFSIM_GPIO_INT_EN 0xc4 /* Secondary Interrupt status (r/w) */
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#define MCFSIM_INT_STAT3 0xe0 /* 3rd Interrupt ctrl status (r) */
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#define MCFSIM_INT_CLEAR3 0xe0 /* 3rd Interrupt ctrl clear (w) */
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#define MCFSIM_INT_EN3 0xe4 /* 3rd Interrupt ctrl enable (r/w) */
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#define MCFSIM_INTLEV1 0x140 /* Interrupts 0 - 7 (r/w) */
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#define MCFSIM_INTLEV2 0x144 /* Interrupts 8 -15 (r/w) */
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#define MCFSIM_INTLEV3 0x148 /* Interrupts 16-23 (r/w) */
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#define MCFSIM_INTLEV4 0x14c /* Interrupts 24-31 (r/w) */
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#define MCFSIM_INTLEV5 0x150 /* Interrupts 32-39 (r/w) */
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#define MCFSIM_INTLEV6 0x154 /* Interrupts 40-47 (r/w) */
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#define MCFSIM_INTLEV7 0x158 /* Interrupts 48-55 (r/w) */
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#define MCFSIM_INTLEV8 0x15c /* Interrupts 56-63 (r/w) */
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#define MCFSIM_SPURVEC 0x167 /* Spurious Vector Register (r/w) */
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#define MCFSIM_INTBASE 0x16b /* Software interrupt base address (r/w) */
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#define MCFSIM_IDECONFIG1 0x18c /* IDE config register 1 (r/w) */
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#define MCFSIM_IDECONFIG2 0x190 /* IDE config register 1 (r/w) */
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#define MCFSIM_PLLCR 0x180 /* PLL Control register */
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/*
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* Some symbol defines for the above...
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*/
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#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */
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#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */
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#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */
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#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */
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#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */
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#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */
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/* XXX - If needed, DMA ICRs go here */
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#define MCFSIM_QSPIICR MCFSIM_ICR10 /* QSPI ICR */
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/*
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* Bit definitions for the ICR family of registers.
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*/
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#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */
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#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */
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#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */
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#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */
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#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */
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#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */
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#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */
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#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */
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#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */
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#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */
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#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */
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#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */
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#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */
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/*
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* Macros to read/set IMR register. It is 32 bits on the 5249.
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*/
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#define mcf_getimr() \
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*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR))
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#define mcf_setimr(imr) \
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*((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr);
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#endif /* mcf5249_h */
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@ -87,6 +87,10 @@
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#define MCFUART_UOP1 0x38 /* Output Port Bit Set (w) */
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#define MCFUART_UOP0 0x3c /* Output Port Bit Reset (w) */
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#ifdef CONFIG_M5249
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/* Note: This isn't in the 5249 docs */
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#define MCFUART_UFPD 0x30 /* Frac Prec. Divider (r/w) */
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#endif
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/*
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* Define bit flags in Mode Register 1 (MR1).
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@ -43,7 +43,7 @@ struct pt_regs {
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ulong a4;
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ulong a5;
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ulong a6;
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#if defined(CONFIG_M5272) || defined(CONFIG_M5282)
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#if defined(CONFIG_M5272) || defined(CONFIG_M5282) || defined(CONFIG_M5249)
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unsigned format : 4; /* frame format specifier */
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unsigned vector : 12; /* vector offset */
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unsigned short sr;
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@ -36,6 +36,11 @@
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#include <asm/m5282.h>
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#endif
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#ifdef CONFIG_M5249
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#include <asm/m5249.h>
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#include <asm/immap_5249.h>
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#endif
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static ulong timestamp;
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#ifdef CONFIG_M5282
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@ -173,6 +178,87 @@ void wait_ticks (unsigned long ticks)
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#endif
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#if defined(CONFIG_M5249)
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/*
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* We use timer 1 which is running with a period of 1 us
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*/
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void udelay(unsigned long usec)
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{
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volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE1);
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uint start, now, tmp;
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while (usec > 0) {
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if (usec > 65000)
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tmp = 65000;
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else
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tmp = usec;
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usec = usec - tmp;
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/* Set up TIMER 1 as timebase clock */
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timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
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timerp->timer_tcn = 0;
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/* set period to 1 us */
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/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
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timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
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MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE;
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start = now = timerp->timer_tcn;
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while (now < start + tmp)
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now = timerp->timer_tcn;
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}
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}
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void mcf_timer_interrupt (void * not_used){
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volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);
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/* check for timer 2 interrupts */
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if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) {
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return;
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}
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/* reset timer */
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timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
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timestamp ++;
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}
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void timer_init (void) {
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volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);
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timestamp = 0;
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/* Set up TIMER 2 as clock */
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timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
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/* initialize and enable timer 2 interrupt */
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irq_install_handler (31, mcf_timer_interrupt, 0);
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mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
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mbar_writeByte(MCFSIM_TIMER2ICR, MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3);
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timerp->timer_tcn = 0;
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timerp->timer_trr = 1000; /* Interrupt every ms */
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/* set a period of 1us, set timer mode to restart and enable timer and interrupt */
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/* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
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timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
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MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
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}
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void reset_timer (void)
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{
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timestamp = 0;
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}
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ulong get_timer (ulong base)
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{
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return (timestamp - base);
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}
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void set_timer (ulong t)
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{
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timestamp = t;
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}
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#endif
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/*
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* This function is derived from PowerPC code (read timebase as long long).
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* On M68K it just returns the timer value.
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