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ARM: atmel: enable SPL on sama5d3_xplained board
It supports boot from NAND and SD/MMC card. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This commit is contained in:
Bo Shen
Andreas Bießmann
parent
12bbc0ba81
commit
cd23aac4bf
2 changed files with 137 additions and 0 deletions
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@ -17,6 +17,9 @@
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#include <atmel_mci.h>
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#include <net.h>
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#include <netdev.h>
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#include <spl.h>
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#include <asm/arch/atmel_mpddrc.h>
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#include <asm/arch/at91_wdt.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -128,3 +131,87 @@ int board_mmc_init(bd_t *bis)
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return 0;
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}
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#endif
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/* SPL */
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#ifdef CONFIG_SPL_BUILD
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void spl_board_init(void)
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{
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#ifdef CONFIG_SYS_USE_MMC
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sama5d3_xplained_mci0_hw_init();
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#elif CONFIG_SYS_USE_NANDFLASH
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sama5d3_xplained_nand_hw_init();
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#endif
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}
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static void ddr2_conf(struct atmel_mpddr *ddr2)
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{
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ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
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ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
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ATMEL_MPDDRC_CR_NR_ROW_14 |
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ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
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ATMEL_MPDDRC_CR_ENRDM_ON |
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ATMEL_MPDDRC_CR_NB_8BANKS |
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ATMEL_MPDDRC_CR_NDQS_DISABLED |
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ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
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ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
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/*
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* As the DDR2-SDRAm device requires a refresh time is 7.8125us
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* when DDR run at 133MHz, so it needs (7.8125us * 133MHz / 10^9) clocks
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*/
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ddr2->rtr = 0x411;
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ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
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8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
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2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
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ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
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200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
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28 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
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26 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
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ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
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2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
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2 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
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7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
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8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
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}
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void mem_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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struct atmel_mpddr ddr2;
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ddr2_conf(&ddr2);
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/* enable MPDDR clock */
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at91_periph_clk_enable(ATMEL_ID_MPDDRC);
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writel(0x4, &pmc->scer);
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/* DDRAM2 Controller initialize */
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ddr2_init(ATMEL_BASE_DDRCS, &ddr2);
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}
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void at91_pmc_init(void)
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{
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struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
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u32 tmp;
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tmp = AT91_PMC_PLLAR_29 |
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AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
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AT91_PMC_PLLXR_MUL(43) |
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AT91_PMC_PLLXR_DIV(1);
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at91_plla_init(tmp);
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writel(0x3 << 8, &pmc->pllicpr);
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tmp = AT91_PMC_MCKR_MDIV_4 |
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AT91_PMC_MCKR_CSS_PLLA;
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at91_mck_init(tmp);
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}
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#endif
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@ -20,7 +20,11 @@
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#define CONFIG_AT91FAMILY
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#define CONFIG_ARCH_CPU_INIT
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#endif
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_DISPLAY_CPUINFO
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@ -74,8 +78,12 @@
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#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
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#define CONFIG_SYS_SDRAM_SIZE 0x10000000
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_INIT_SP_ADDR 0x310000
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#else
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
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#endif
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/* NAND flash */
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#define CONFIG_CMD_NAND
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@ -199,4 +207,46 @@
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
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/* SPL */
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#define CONFIG_SPL
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x300000
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#define CONFIG_SPL_MAX_SIZE 0x10000
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#define CONFIG_SPL_BSS_START_ADDR 0x20000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
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#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
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#define CONFIG_SPL_LIBCOMMON_SUPPORT
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#define CONFIG_SPL_LIBGENERIC_SUPPORT
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#define CONFIG_SPL_GPIO_SUPPORT
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#define CONFIG_SPL_SERIAL_SUPPORT
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#define CONFIG_SPL_BOARD_INIT
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#define CONFIG_SYS_MONITOR_LEN (512 << 10)
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#ifdef CONFIG_SYS_USE_MMC
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#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds
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#define CONFIG_SPL_MMC_SUPPORT
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#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
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#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
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#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
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#define CONFIG_SPL_FAT_SUPPORT
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#define CONFIG_SPL_LIBDISK_SUPPORT
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#elif CONFIG_SYS_USE_NANDFLASH
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#define CONFIG_SPL_NAND_SUPPORT
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#define CONFIG_SPL_NAND_DRIVERS
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#define CONFIG_SPL_NAND_BASE
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
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#define CONFIG_SYS_NAND_PAGE_COUNT 64
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#define CONFIG_SYS_NAND_OOBSIZE 64
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#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
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#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
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#endif
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#endif
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