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https://github.com/AsahiLinux/u-boot
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* Patch by Yuli Barcohen, 23 Jun 2003:
Update for MPC8260ADS board * Patch by Murray Jensen, 23 Jun 2003: - cleanup of GCC 3.x compiler warnings
This commit is contained in:
wdenk
parent
3595ac4979
commit
cceb871fff
5 changed files with 46 additions and 43 deletions
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@ -2,6 +2,12 @@
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Changes since U-Boot 0.3.1:
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======================================================================
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* Patch by Yuli Barcohen, 23 Jun 2003:
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Update for MPC8260ADS board
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* Patch by Murray Jensen, 23 Jun 2003:
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- cleanup of GCC 3.x compiler warnings
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* Patch by Rune Torgersen, 4 Jun 2003:
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add large memory support for MPC8266ADS board
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@ -37,6 +37,7 @@
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#include <mpc8260.h>
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#include <i2c.h>
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#include <spd.h>
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#include <miiphy.h>
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/*
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* I/O Port configuration table
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@ -133,8 +134,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
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/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
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/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
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/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
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/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
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/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
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/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
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/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
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/* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
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/* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
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/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
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@ -142,8 +143,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
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/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
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/* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
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/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
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/* PC10 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDC */
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/* PC9 */ { 1, 1, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
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/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT970 FETHMDC */
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/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT970 FETHMDIO */
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/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
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/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
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/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
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@ -157,8 +158,8 @@ const iop_conf_t iop_conf_tab[4][32] = {
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/* Port D */
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{ /* conf ppar psor pdir podr pdat */
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/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
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/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
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/* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
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/* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
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/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
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/* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
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/* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
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@ -173,14 +174,14 @@ const iop_conf_t iop_conf_tab[4][32] = {
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/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
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/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
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/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
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/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
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/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
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/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
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/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
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/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
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/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
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/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
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/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
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/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
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/* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
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/* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
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/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
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/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
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/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
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@ -192,32 +193,33 @@ const iop_conf_t iop_conf_tab[4][32] = {
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}
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};
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typedef struct bscr_ {
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unsigned long bcsr0;
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unsigned long bcsr1;
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unsigned long bcsr2;
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unsigned long bcsr3;
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unsigned long bcsr4;
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unsigned long bcsr5;
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unsigned long bcsr6;
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unsigned long bcsr7;
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} bcsr_t;
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void reset_phy (void)
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{
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volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
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vu_long *bcsr = (vu_long *)CFG_BCSR;
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/* reset the FEC port */
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bcsr->bcsr1 &= ~FETH_RST;
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bcsr->bcsr1 |= FETH_RST;
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bcsr[1] &= ~FETH_RST;
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udelay(2);
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bcsr[1] |= FETH_RST;
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udelay(1000);
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#ifdef CONFIG_MII
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/*
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* Ethernet PHY is configured (by means of configuration pins)
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* to work at 10Mb/s only. We reconfigure it using MII
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* to advertise all capabilities, including 100Mb/s, and
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* restart autonegotiation.
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*/
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miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
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miiphy_write(0, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */
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miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
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#endif /* CONFIG_MII */
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}
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int board_pre_init (void)
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{
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volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
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vu_long *bcsr = (vu_long *)CFG_BCSR;
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bcsr->bcsr1 = ~FETHIEN & ~RS232EN_1;
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bcsr[1] = ~FETHIEN & ~RS232EN_1;
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return 0;
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}
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@ -792,15 +792,7 @@ ide_inb(int dev, int port)
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#endif /* __PPC__ */
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#ifdef __PPC__
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__inline__ unsigned ld_le16(const volatile unsigned short *addr)
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{
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unsigned val;
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__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r"(val) : "r"(addr), "m"(*addr));
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return val;
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}
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#ifdef CONFIG_AMIGAONEG3SE
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# ifdef CONFIG_AMIGAONEG3SE
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static void
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output_data_short(int dev, ulong *sect_buf, int words)
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{
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@ -818,7 +810,7 @@ output_data_short(int dev, ulong *sect_buf, int words)
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if (words&1)
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*pbuf = 0;
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}
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#endif
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# endif /* CONFIG_AMIGAONEG3SE */
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static void
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input_swap_data(int dev, ulong *sect_buf, int words)
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@ -131,10 +131,10 @@ int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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ulong addr;
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/* Interrupts off, enable reset */
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__asm__ volatile (" mtspr 81, %r0 \n\t
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mfmsr %r3 \n\t
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rlwinm %r31,%r3,0,25,23\n\t
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mtmsr %r31 \n\t");
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__asm__ volatile (" mtspr 81, %r0 \n\t"
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" mfmsr %r3 \n\t"
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" rlwinm %r31,%r3,0,25,23\n\t"
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" mtmsr %r31 \n\t");
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/*
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* Trying to execute the next instruction at a non-existing address
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* should cause a machine check, resulting in reset
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@ -7,6 +7,10 @@
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* Note: my board is a PILOT rev.
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* Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
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*
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* (C) Copyright 2003 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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* Added support for SDRAM DIMMs SPD EEPROM, MII.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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@ -145,9 +149,8 @@
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CFG_CMD_IDE | \
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CFG_CMD_JFFS2 | \
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CFG_CMD_KGDB | \
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CFG_CMD_NAND | \
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CFG_CMD_MII | \
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CFG_CMD_MMC | \
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CFG_CMD_NAND | \
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CFG_CMD_PCI | \
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CFG_CMD_PCMCIA | \
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CFG_CMD_SCSI | \
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