Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-26 06:30:39 +00:00
Code Issues Projects Releases Packages Wiki Activity

mpc8[5/6]xx: Ensure POST word does not get reset

Browse source 
The POST word is stored in a spare register in the PIC on MPC8[5/6]xx
processors.  When interrupt_init() is called, this register gets reset
which resulted in all POST_RAM POSTs not being ran due to the corrupted
POST word.  To resolve this, store off POST word before the PIC is
reset, and restore it after the PIC has been initialized.

Signed-off-by: John Schmoller <jschmoller@xes-inc.com>
Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
John Schmoller 2011-03-10 16:09:26 -06:00 committed by Kumar Gala
parent b71ea33699
commit cc1dd33f27
2 changed files with 32 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
arch/powerpc/cpu/mpc85xx/interrupts.c
View file

@ -32,11 +32,23 @@
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
#ifdef CONFIG_POST
#include <post.h>
#endif
int interrupt_init_cpu(unsigned int *decrementer_count)
{
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
#ifdef CONFIG_POST
/*
* The POST word is stored in the PIC's TFRR register which gets
* cleared when the PIC is reset. Save it off so we can restore it
* later.
*/
ulong post_word = post_word_load();
#endif
out_be32(&pic->gcr, MPC85xx_PICGCR_RST);
while (in_be32(&pic->gcr) & MPC85xx_PICGCR_RST)
;
@ -78,6 +90,10 @@ int interrupt_init_cpu(unsigned int *decrementer_count)
pic->ctpr=0; /* 40080 clear current task priority register */
#endif
#ifdef CONFIG_POST
post_word_store(post_word);
#endif
return (0);
}

16
arch/powerpc/cpu/mpc86xx/interrupts.c
View file

@ -35,12 +35,24 @@
#include <mpc86xx.h>
#include <command.h>
#include <asm/processor.h>
#ifdef CONFIG_POST
#include <post.h>
#endif
int interrupt_init_cpu(unsigned long *decrementer_count)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile ccsr_pic_t *pic = &immr->im_pic;
#ifdef CONFIG_POST
/*
* The POST word is stored in the PIC's TFRR register which gets
* cleared when the PIC is reset. Save it off so we can restore it
* later.
*/
ulong post_word = post_word_load();
#endif
pic->gcr = MPC86xx_PICGCR_RST;
while (pic->gcr & MPC86xx_PICGCR_RST)
;
@ -74,6 +86,10 @@ int interrupt_init_cpu(unsigned long *decrementer_count)
pic->ctpr = 0; /* 40080 clear current task priority register */
#endif
#ifdef CONFIG_POST
post_word_store(post_word);
#endif
return 0;
}