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mpc85xx: Base emulator support

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Prepare for emulator support for mpc85xx parts.
Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers.
These two registers improve stability but not supported by emulator.
Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base.

Signed-off-by: York Sun <yorksun@freescale.com>
This commit is contained in:
York Sun 2013-06-25 11:37:41 -07:00
parent 7adefb55ad
commit cb93071bb6
5 changed files with 23 additions and 1 deletions
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4
README
View file

@ -413,6 +413,10 @@ The following options need to be configured:
CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
This value denotes start offset of DSP CCSR space. This value denotes start offset of DSP CCSR space.
CONFIG_SYS_FSL_DDR_EMU
Specify emulator support for DDR. Some DDR features such as
deskew training are not available.
- Generic CPU options: - Generic CPU options:
CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN

2
arch/powerpc/cpu/mpc85xx/cpu_init.c
View file

@ -532,8 +532,10 @@ skip_l2:
enable_cpc(); enable_cpc();
#ifndef CONFIG_SYS_FSL_NO_SERDES
/* needs to be in ram since code uses global static vars */ /* needs to be in ram since code uses global static vars */
fsl_serdes_init(); fsl_serdes_init();
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A005871 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
if (IS_SVR_REV(svr, 1, 0)) { if (IS_SVR_REV(svr, 1, 0)) {

7
arch/powerpc/cpu/mpc85xx/ddr-gen3.c
View file

@ -123,10 +123,17 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl); out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl); out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
#ifndef CONFIG_SYS_FSL_DDR_EMU
/*
* Skip these two registers if running on emulator
* because emulator doesn't have skew between bytes.
*/
if (regs->ddr_wrlvl_cntl_2) if (regs->ddr_wrlvl_cntl_2)
out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2); out_be32(&ddr->ddr_wrlvl_cntl_2, regs->ddr_wrlvl_cntl_2);
if (regs->ddr_wrlvl_cntl_3) if (regs->ddr_wrlvl_cntl_3)
out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3);
#endif
out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr); out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1); out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);

6
arch/powerpc/cpu/mpc85xx/fdt.c
View file

@ -604,8 +604,12 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_add_enet_stashing(blob); fdt_add_enet_stashing(blob);
#ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
#define CONFIG_FSL_TBCLK_EXTRA_DIV 1
#endif
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"timebase-frequency", get_tbclk(), 1); "timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
1);
do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
"bus-frequency", bd->bi_busfreq, 1); "bus-frequency", bd->bi_busfreq, 1);
get_sys_info(&sysinfo); get_sys_info(&sysinfo);

5
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
View file

@ -1638,5 +1638,10 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts,
set_ddr_sdram_rcw(ddr, popts, common_dimm); set_ddr_sdram_rcw(ddr, popts, common_dimm);
#ifdef CONFIG_SYS_FSL_DDR_EMU
/* disble DDR training for emulator */
ddr->debug[2] = 0x00000400;
ddr->debug[4] = 0xff800000;
#endif
return check_fsl_memctl_config_regs(ddr); return check_fsl_memctl_config_regs(ddr);
} }