mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
nhk8815: remove platform.S, which was unused at link time
This source file, which I got by the vendor in their own port, was not actually executing because lib-based compilation didn't call lowlevel_init (we have CONFIG_SKIP_LOWLEVEL_INIT). With the change to object-based linking, an undefined symbol in this file started hitting in the final link. Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
This commit is contained in:
Alessandro Rubini
Albert ARIBAUD
parent
632f8fdf4c
commit
cb8948ee52
2 changed files with 1 additions and 341 deletions
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@ -30,7 +30,7 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).o
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COBJS := nhk8815.o
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SOBJS := platform.o
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SOBJS :=
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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@ -1,340 +0,0 @@
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/*
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* Board specific setup info
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*
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* (C) Copyright 2005
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* STMicrolelctronics, <www.st.com>
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*
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* (C) Copyright 2004, ARM Ltd.
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* Philippe Robin, <philippe.robin@arm.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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.globl lowlevel_init
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lowlevel_init:
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/* Jump to the flash address */
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ldr r0, =CFG_ONENAND_BASE
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/*
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* Make it independent whether we boot from 0x0 or 0x30000000.
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* Non-portable: it relies on the knowledge that ip has to be updated
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*/
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orr ip, ip, r0 /* adjust return address of cpu_init_crit */
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orr lr, lr, r0 /* adjust return address */
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orr pc, pc, r0 /* jump to the normal address */
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nop
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/* Initialize PLL, Remap clear, FSMC, MPMC here! */
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/* What about GPIO, CLCD and UART */
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/* PLL Initialization */
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/* Prog the PLL1 @ 266 MHz ==> SDRAM Clock = 100.8 MHz */
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ldr r0, =NOMADIK_SRC_BASE
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ldr r1, =0x2B013502
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str r1, [r0, #0x14]
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/* Used to set all the timers clock to 2.4MHZ */
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ldr r1, =0x2AAAA004
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str r1, [r0]
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ldr r1, =0x10000000
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str r1, [r0, #0x10]
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/* FSMC setup ---- */
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ldr r0, =NOMADIK_FSMC_BASE
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ldr r1, =0x10DB /* For 16-bit NOR flash */
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str r1, [r0, #0x08]
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ldr r1, =0x03333333 /* For 16-bit NOR flash */
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str r1, [r0, #0xc]
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/* oneNAND setting */
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ldr r1, =0x0000105B /* BCR0 Prog control register */
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str r1, [r0]
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ldr r1, =0x0A200551 /* BTR0 Prog timing register */
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str r1, [r0, #0x04]
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/* preload the instructions into icache */
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add r0, pc, #0x1F
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bic r0, r0, #0x1F
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mcr p15, 0, r0, c7, c13, 1
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add r0, r0, #0x20
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mcr p15, 0, r0, c7, c13, 1
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/* Now Clear Remap */
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ldr r0, =NOMADIK_SRC_BASE
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ldr r1, =0x2004
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str r1, [r0]
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ldr r1, =0x10000000
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str r1, [r0, #0x10]
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ldr r0, =0x101E9000
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ldr r1, =0x2004
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str r1, [r0]
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ldr r0, =NOMADIK_SRC_BASE
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ldr r1, =0x2104
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str r1, [r0]
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/* FSMC setup -- */
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mov r0, #(NOMADIK_FSMC_BASE & 0x10000000)
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orr r0, r0, #(NOMADIK_FSMC_BASE & 0x0FFFFFFF)
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ldr r1, =0x10DB /* For 16-bit NOR flash */
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str r1, [r0, #0x8]
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ldr r1, =0x03333333 /* For 16-bit NOR flash */
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str r1, [r0, #0xc]
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/* MPMC Setup */
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ldr r0, =NOMADIK_MPMC_BASE
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ldr r1, =0xF00003
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str r1, [r0] /* Enable the MPMC and the DLL */
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ldr r1, =0x183
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str r1, [r0, #0x20]
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ldr r2, =NOMADIK_PMU_BASE
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ldr r1, =0x1111
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str r1, [r2]
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ldr r1, =0x1111 /* Prog the, mand delay strategy */
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str r1, [r0, #0x28]
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ldr r1, =0x103 /* NOP ,mand */
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str r1, [r0, #0x20]
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/* FIXME -- Wait required here */
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ldr r1, =0x103 /* PALL ,mand*/
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str r1, [r0, #0x20]
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ldr r1, =0x1
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str r1, [r0, #0x24] /* To do at least two auto-refresh */
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/* FIXME -- Wait required here */
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/* Auto-refresh period = 7.8us @ SDRAM Clock = 100.8 MHz */
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ldr r1, =0x31
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str r1, [r0, #0x24]
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/* Prog Little Endian, Not defined in 8800 board */
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ldr r1, =0x0
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str r1, [r0, #0x8]
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ldr r1, =0x2
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str r1, [r0, #0x30] /* Prog tRP timing */
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ldr r1, =0x4 /* Change for 8815 */
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str r1, [r0, #0x34] /* Prog tRAS timing */
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ldr r1, =0xB
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str r1, [r0, #0x38] /* Prog tSREX timing */
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ldr r1, =0x1
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str r1, [r0, #0x44] /* Prog tWR timing */
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ldr r1, =0x8
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str r1, [r0, #0x48] /* Prog tRC timing */
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ldr r1, =0xA
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str r1, [r0, #0x4C] /* Prog tRFC timing */
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ldr r1, =0xB
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str r1, [r0, #0x50] /* Prog tXSR timing */
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ldr r1, =0x1
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str r1, [r0, #0x54] /* Prog tRRD timing */
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ldr r1, =0x1
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str r1, [r0, #0x58] /* Prog tMRD timing */
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ldr r1, =0x1
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str r1, [r0, #0x5C] /* Prog tCDLR timing */
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/* DDR-SDRAM MEMORY IS ON BANK0 8815 */
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ldr r1, =0x304 /* Prog RAS and CAS for CS 0 */
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str r1, [r0, #0x104]
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/* SDR-SDRAM MEMORY IS ON BANK1 8815 */
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ldr r1, =0x304 /* Prog RAS and CAS for CS 1 */
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str r1, [r0, #0x124]
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/* THE DATA BUS WIDE IS PROGRAM FOR 16-BITS */
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/* DDR-SDRAM MEMORY IS ON BANK0*/
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ldr r1, =0x884 /* 8815 : config reg in BRC for CS0 */
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str r1, [r0, #0x100]
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/*SDR-SDRAM MEMORY IS ON BANK1*/
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ldr r1, =0x884 /* 8815 : config reg in BRC for CS1 */
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str r1, [r0, #0x120]
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ldr r1, =0x83 /*MODE Mand*/
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str r1, [r0, #0x20]
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/* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK0 */
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ldr r1, =0x62000 /*Data in*/
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ldr r1, [r1]
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/* LOAD MODE REGISTER FOR 2 bursts of 16b, with DDR mem ON BANK1 */
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ldr r1, =0x8062000
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ldr r1, [r1]
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ldr r1, =0x003
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str r1, [r0, #0x20]
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/* ENABLE ALL THE BUFFER FOR EACH AHB PORT*/
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ldr r1, =0x01 /* Enable buffer 0 */
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str r1, [r0, #0x400]
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ldr r1, =0x01 /* Enable buffer 1 */
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str r1, [r0, #0x420]
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ldr r1, =0x01 /* Enable buffer 2 */
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str r1, [r0, #0x440]
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ldr r1, =0x01 /* Enable buffer 3 */
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str r1, [r0, #0x460]
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ldr r1, =0x01 /* Enable buffer 4 */
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str r1, [r0, #0x480]
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ldr r1, =0x01 /* Enable buffer 5 */
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str r1, [r0, #0x4A0]
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/* GPIO settings */
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ldr r0, =NOMADIK_GPIO1_BASE
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ldr r1, =0xC0600000
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str r1, [r0, #0x20]
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ldr r1, =0x3F9FFFFF /* ABHI change this for uart1 */
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str r1, [r0, #0x24]
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ldr r1, =0x3F9FFFFF /* ABHI change this for uart1 */
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str r1, [r0, #0x28]
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ldr r0, =NOMADIK_GPIO0_BASE
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ldr r1, =0xFFFFFFFF
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str r1, [r0, #0x20]
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ldr r1, =0x00
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str r1, [r0, #0x24]
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ldr r1, =0x00
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str r1, [r0, #0x28]
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/* Configure CPLD_CTRL register for enabling MUX logic for UART0/UART2 */
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ldr r0, =NOMADIK_FSMC_BASE
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ldr r1, =0x10DB /* INIT FSMC bank 0 */
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str r1, [r0, #0x00]
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ldr r1, =0x0FFFFFFF
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str r1, [r0, #0x04]
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ldr r1, =0x010DB /* INIT FSMC bank 1 */
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str r1, [r0, #0x08]
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ldr r1, =0x00FFFFFFF
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str r1, [r0, #0x0C]
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ldr r0, =NOMADIK_UART0_BASE
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ldr r1, =0x00000000
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str r1, [r0, #0x30]
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ldr r1, =0x0000004e
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str r1, [r0, #0x24]
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ldr r1, =0x00000008
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str r1, [r0, #0x28]
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ldr r1, =0x00000060
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str r1, [r0, #0x2C]
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ldr r1, =0x00000301
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str r1, [r0, #0x30]
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ldr r1, =0x00000066
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str r1, [r0]
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ldr r0, =NOMADIK_UART1_BASE
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ldr r1, =0x00000000
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str r1, [r0, #0x30]
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ldr r1, =0x0000004e
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str r1, [r0, #0x24]
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ldr r1, =0x00000008
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str r1, [r0, #0x28]
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ldr r1, =0x00000060
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str r1, [r0, #0x2C]
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ldr r1, =0x00000301
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str r1, [r0, #0x30]
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ldr r1, =0x00000066
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str r1, [r0]
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ldr r0, =NOMADIK_UART2_BASE
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ldr r1, =0x00000000
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str r1, [r0, #0x30]
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ldr r1, =0x0000004e
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str r1, [r0, #0x24]
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ldr r1, =0x00000008
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str r1, [r0, #0x28]
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ldr r1, =0x00000060
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str r1, [r0, #0x2C]
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ldr r1, =0x00000301
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str r1, [r0, #0x30]
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ldr r1, =0x00000066
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str r1, [r0]
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/* Configure CPLD to enable UART0 */
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mov pc, lr
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