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https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
i2c: Remove non-DM_I2C support from davinci_i2c.c
As the migration deadline has passed, and all platforms have been migrated, remove the non-DM code here. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
parent
ba39d90728
commit
cb42c1f9b1
6 changed files with 2 additions and 128 deletions
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@ -404,24 +404,11 @@ static void init_ddr3param(struct ddr3_spd_cb *spd_cb,
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static int ddr3_read_spd(ddr3_spd_eeprom_t *spd_params)
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{
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int ret;
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#if !CONFIG_IS_ENABLED(DM_I2C)
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int old_bus;
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i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE);
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old_bus = i2c_get_bus_num();
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i2c_set_bus_num(1);
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ret = i2c_read(0x53, 0, 1, (unsigned char *)spd_params, 256);
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i2c_set_bus_num(old_bus);
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#else
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struct udevice *dev;
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ret = i2c_get_chip_for_busnum(1, 0x53, 1, &dev);
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if (!ret)
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ret = dm_i2c_read(dev, 0, (unsigned char *)spd_params, 256);
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#endif
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if (ret) {
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printf("Cannot read DIMM params\n");
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return 1;
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@ -687,9 +687,9 @@ config SYS_I2C_SPEED
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config SYS_I2C_BUS_MAX
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int "Max I2C busses"
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depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
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depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA
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default 2 if TI816X
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default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
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default 3 if OMAP34XX || AM33XX || AM43XX
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default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
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default 5 if OMAP54XX
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help
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@ -21,14 +21,12 @@
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#include <linux/delay.h>
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#include "davinci_i2c.h"
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#if CONFIG_IS_ENABLED(DM_I2C)
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/* Information about i2c controller */
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struct i2c_bus {
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int id;
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uint speed;
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struct i2c_regs *regs;
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};
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#endif
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#define CHECK_NACK() \
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do {\
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@ -340,99 +338,6 @@ static int _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, uint8_t chip)
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return rc;
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}
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#if !CONFIG_IS_ENABLED(DM_I2C)
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static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
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{
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switch (adap->hwadapnr) {
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#if CONFIG_SYS_I2C_BUS_MAX >= 3
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case 2:
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return (struct i2c_regs *)I2C2_BASE;
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#endif
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#if CONFIG_SYS_I2C_BUS_MAX >= 2
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case 1:
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return (struct i2c_regs *)I2C1_BASE;
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#endif
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case 0:
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return (struct i2c_regs *)I2C_BASE;
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default:
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printf("wrong hwadapnr: %d\n", adap->hwadapnr);
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}
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return NULL;
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}
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static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
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{
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struct i2c_regs *i2c_base = davinci_get_base(adap);
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uint ret;
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adap->speed = speed;
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ret = _davinci_i2c_setspeed(i2c_base, speed);
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return ret;
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}
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static void davinci_i2c_init(struct i2c_adapter *adap, int speed,
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int slaveadd)
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{
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struct i2c_regs *i2c_base = davinci_get_base(adap);
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adap->speed = speed;
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_davinci_i2c_init(i2c_base, speed, slaveadd);
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return;
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}
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static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
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uint32_t addr, int alen, uint8_t *buf, int len)
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{
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struct i2c_regs *i2c_base = davinci_get_base(adap);
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return _davinci_i2c_read(i2c_base, chip, addr, alen, buf, len);
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}
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static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
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uint32_t addr, int alen, uint8_t *buf, int len)
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{
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struct i2c_regs *i2c_base = davinci_get_base(adap);
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return _davinci_i2c_write(i2c_base, chip, addr, alen, buf, len);
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}
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static int davinci_i2c_probe_chip(struct i2c_adapter *adap, uint8_t chip)
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{
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struct i2c_regs *i2c_base = davinci_get_base(adap);
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return _davinci_i2c_probe_chip(i2c_base, chip);
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}
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U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe_chip,
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davinci_i2c_read, davinci_i2c_write,
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davinci_i2c_setspeed,
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CONFIG_SYS_DAVINCI_I2C_SPEED,
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CONFIG_SYS_DAVINCI_I2C_SLAVE,
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0)
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#if CONFIG_SYS_I2C_BUS_MAX >= 2
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U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe_chip,
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davinci_i2c_read, davinci_i2c_write,
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davinci_i2c_setspeed,
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CONFIG_SYS_DAVINCI_I2C_SPEED1,
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CONFIG_SYS_DAVINCI_I2C_SLAVE1,
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1)
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#endif
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#if CONFIG_SYS_I2C_BUS_MAX >= 3
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U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe_chip,
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davinci_i2c_read, davinci_i2c_write,
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davinci_i2c_setspeed,
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CONFIG_SYS_DAVINCI_I2C_SPEED2,
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CONFIG_SYS_DAVINCI_I2C_SLAVE2,
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2)
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#endif
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#else /* CONFIG_DM_I2C */
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static int davinci_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
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int nmsgs)
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{
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@ -507,5 +412,3 @@ U_BOOT_DRIVER(i2c_davinci) = {
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.priv_auto = sizeof(struct i2c_bus),
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.ops = &davinci_i2c_ops,
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};
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#endif /* CONFIG_DM_I2C */
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@ -41,12 +41,6 @@
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#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
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/*
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* I2C Configuration
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*/
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#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
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#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
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/*
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* U-Boot general configuration
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*/
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@ -99,8 +99,6 @@
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/*
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* I2C Configuration
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*/
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#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000
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#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
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#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
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/*
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@ -59,14 +59,6 @@
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#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE
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#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES
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/* I2C Configuration */
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#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000
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#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
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#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000
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#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */
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#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000
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#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */
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/* EEPROM definitions */
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/* NAND Configuration */
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