Mirrors/u-boot
2
0
Fork 0
mirror of https://github.com/AsahiLinux/u-boot synced 2024-11-11 07:34:31 +00:00
Code Issues Projects Releases Packages Wiki Activity

arm: socfpga: Fix QSPI doesn't work on socdk board

Browse source 
Updated pinmux group MIXED1IO[15-20] for QSPI.
Updated QSPI clock.

Signed-off-by: shengjiangwu <shengjiangwu@icloud.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
This commit is contained in:
shengjiangwu 2015-12-22 17:18:09 +08:00 committed by Marek Vasut
parent b0808b912d
commit caee45ecc3
2 changed files with 7 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

12
board/altera/cyclone5-socdk/qts/pinmux_config.h
View file

@ -87,12 +87,12 @@ const u8 sys_mgr_init_table[] = {
2, /* MIXED1IO12 */ 2, /* MIXED1IO12 */
2, /* MIXED1IO13 */ 2, /* MIXED1IO13 */
0, /* MIXED1IO14 */ 0, /* MIXED1IO14 */
1, /* MIXED1IO15 */ 3, /* MIXED1IO15 */
1, /* MIXED1IO16 */ 3, /* MIXED1IO16 */
1, /* MIXED1IO17 */ 3, /* MIXED1IO17 */
1, /* MIXED1IO18 */ 3, /* MIXED1IO18 */
0, /* MIXED1IO19 */ 3, /* MIXED1IO19 */
0, /* MIXED1IO20 */ 3, /* MIXED1IO20 */
0, /* MIXED1IO21 */ 0, /* MIXED1IO21 */
0, /* MIXED2IO0 */ 0, /* MIXED2IO0 */
0, /* MIXED2IO1 */ 0, /* MIXED2IO1 */

2
board/altera/cyclone5-socdk/qts/pll_config.h
View file

@ -14,7 +14,7 @@
#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 #define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3
#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 #define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15
#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1