mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 22:20:45 +00:00
PXA: cerf250: Fix for reloc
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
This commit is contained in:
Marek Vasut
parent
4abf2f7a23
commit
caeb8c0ac2
5 changed files with 22 additions and 440 deletions
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@ -26,17 +26,15 @@ include $(TOPDIR)/config.mk
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LIB = $(obj)lib$(BOARD).a
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COBJS := cerf250.o flash.o
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SOBJS := lowlevel_init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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SRCS := $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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$(LIB): $(obj).depend $(OBJS) $(SOBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
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$(LIB): $(obj).depend $(OBJS)
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$(AR) $(ARFLAGS) $@ $(OBJS)
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clean:
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rm -f $(SOBJS) $(OBJS)
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rm -f $(OBJS)
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distclean: clean
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rm -f $(LIB) core *.bak $(obj).depend
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@ -39,8 +39,9 @@ DECLARE_GLOBAL_DATA_PTR;
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int board_init (void)
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{
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/* memory and cpu-speed are setup before relocation */
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/* so we do _nothing_ here */
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/* We have RAM, disable cache */
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dcache_disable();
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icache_disable();
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/* arch number of cerf PXA Board */
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gd->bd->bi_arch_number = MACH_TYPE_PXA_CERF;
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@ -58,19 +59,18 @@ int board_late_init(void)
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return 0;
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}
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extern void pxa_dram_init(void);
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int dram_init(void)
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{
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pxa_dram_init();
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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int dram_init (void)
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
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gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
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gd->bd->bi_dram[3].start = PHYS_SDRAM_4;
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gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE;
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return 0;
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}
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#ifdef CONFIG_CMD_NET
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@ -1,5 +0,0 @@
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#
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# Cerf board with PXA250 cpu
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#
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#
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CONFIG_SYS_TEXT_BASE = 0xa3080000
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@ -1,411 +0,0 @@
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/*
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* Most of this taken from Redboot hal_platform_setup.h with cleanup
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*
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* NOTE: I haven't clean this up considerably, just enough to get it
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* running. See hal_platform_setup.h for the source. See
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* board/cradle/lowlevel_init.S for another PXA250 setup that is
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* much cleaner.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/pxa-regs.h>
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DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
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/* wait for coprocessor write complete */
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.macro CPWAIT reg
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mrc p15,0,\reg,c2,c0,0
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mov \reg,\reg
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sub pc,pc,#4
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.endm
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/*
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* Memory setup
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*/
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.globl lowlevel_init
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lowlevel_init:
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/* Set up GPIO pins first ----------------------------------------- */
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ldr r0, =GPSR0
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ldr r1, =CONFIG_SYS_GPSR0_VAL
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str r1, [r0]
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ldr r0, =GPSR1
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ldr r1, =CONFIG_SYS_GPSR1_VAL
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str r1, [r0]
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ldr r0, =GPSR2
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ldr r1, =CONFIG_SYS_GPSR2_VAL
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str r1, [r0]
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ldr r0, =GPCR0
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ldr r1, =CONFIG_SYS_GPCR0_VAL
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str r1, [r0]
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ldr r0, =GPCR1
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ldr r1, =CONFIG_SYS_GPCR1_VAL
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str r1, [r0]
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ldr r0, =GPCR2
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ldr r1, =CONFIG_SYS_GPCR2_VAL
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str r1, [r0]
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ldr r0, =GPDR0
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ldr r1, =CONFIG_SYS_GPDR0_VAL
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str r1, [r0]
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ldr r0, =GPDR1
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ldr r1, =CONFIG_SYS_GPDR1_VAL
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str r1, [r0]
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ldr r0, =GPDR2
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ldr r1, =CONFIG_SYS_GPDR2_VAL
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str r1, [r0]
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ldr r0, =GAFR0_L
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ldr r1, =CONFIG_SYS_GAFR0_L_VAL
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str r1, [r0]
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ldr r0, =GAFR0_U
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ldr r1, =CONFIG_SYS_GAFR0_U_VAL
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str r1, [r0]
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ldr r0, =GAFR1_L
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ldr r1, =CONFIG_SYS_GAFR1_L_VAL
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str r1, [r0]
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ldr r0, =GAFR1_U
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ldr r1, =CONFIG_SYS_GAFR1_U_VAL
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str r1, [r0]
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ldr r0, =GAFR2_L
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ldr r1, =CONFIG_SYS_GAFR2_L_VAL
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str r1, [r0]
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ldr r0, =GAFR2_U
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ldr r1, =CONFIG_SYS_GAFR2_U_VAL
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str r1, [r0]
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ldr r0, =PSSR /* enable GPIO pins */
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ldr r1, =CONFIG_SYS_PSSR_VAL
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str r1, [r0]
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/* ---------------------------------------------------------------- */
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/* Enable memory interface */
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/* */
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/* The sequence below is based on the recommended init steps */
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/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
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/* Chapter 10. */
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/* ---------------------------------------------------------------- */
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/* ---------------------------------------------------------------- */
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/* Step 1: Wait for at least 200 microsedonds to allow internal */
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/* clocks to settle. Only necessary after hard reset... */
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/* FIXME: can be optimized later */
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/* ---------------------------------------------------------------- */
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ldr r3, =OSCR /* reset the OS Timer Count to zero */
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mov r2, #0
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str r2, [r3]
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ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
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/* so 0x300 should be plenty */
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1:
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ldr r2, [r3]
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cmp r4, r2
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bgt 1b
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mem_init:
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ldr r1, =MEMC_BASE /* get memory controller base addr. */
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/* ---------------------------------------------------------------- */
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/* Step 2a: Initialize Asynchronous static memory controller */
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/* ---------------------------------------------------------------- */
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/* MSC registers: timing, bus width, mem type */
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/* MSC0: nCS(0,1) */
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ldr r2, =CONFIG_SYS_MSC0_VAL
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str r2, [r1, #MSC0_OFFSET]
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ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
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/* that data latches */
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/* MSC1: nCS(2,3) */
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ldr r2, =CONFIG_SYS_MSC1_VAL
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str r2, [r1, #MSC1_OFFSET]
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ldr r2, [r1, #MSC1_OFFSET]
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/* MSC2: nCS(4,5) */
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ldr r2, =CONFIG_SYS_MSC2_VAL
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str r2, [r1, #MSC2_OFFSET]
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ldr r2, [r1, #MSC2_OFFSET]
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/* ---------------------------------------------------------------- */
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/* Step 2b: Initialize Card Interface */
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/* ---------------------------------------------------------------- */
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/* MECR: Memory Expansion Card Register */
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ldr r2, =CONFIG_SYS_MECR_VAL
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str r2, [r1, #MECR_OFFSET]
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ldr r2, [r1, #MECR_OFFSET]
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/* MCMEM0: Card Interface slot 0 timing */
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ldr r2, =CONFIG_SYS_MCMEM0_VAL
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str r2, [r1, #MCMEM0_OFFSET]
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ldr r2, [r1, #MCMEM0_OFFSET]
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/* MCMEM1: Card Interface slot 1 timing */
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ldr r2, =CONFIG_SYS_MCMEM1_VAL
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str r2, [r1, #MCMEM1_OFFSET]
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ldr r2, [r1, #MCMEM1_OFFSET]
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/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
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ldr r2, =CONFIG_SYS_MCATT0_VAL
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str r2, [r1, #MCATT0_OFFSET]
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ldr r2, [r1, #MCATT0_OFFSET]
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/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
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ldr r2, =CONFIG_SYS_MCATT1_VAL
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str r2, [r1, #MCATT1_OFFSET]
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ldr r2, [r1, #MCATT1_OFFSET]
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/* MCIO0: Card Interface I/O Space Timing, slot 0 */
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ldr r2, =CONFIG_SYS_MCIO0_VAL
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str r2, [r1, #MCIO0_OFFSET]
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ldr r2, [r1, #MCIO0_OFFSET]
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/* MCIO1: Card Interface I/O Space Timing, slot 1 */
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ldr r2, =CONFIG_SYS_MCIO1_VAL
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str r2, [r1, #MCIO1_OFFSET]
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ldr r2, [r1, #MCIO1_OFFSET]
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/* ---------------------------------------------------------------- */
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/* Step 2c: Write FLYCNFG FIXME: what's that??? */
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/* ---------------------------------------------------------------- */
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/* ---------------------------------------------------------------- */
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/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
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/* ---------------------------------------------------------------- */
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/* Before accessing MDREFR we need a valid DRI field, so we set */
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/* this to power on defaults + DRI field, set SDRAM clocks free running */
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ldr r3, =CONFIG_SYS_MDREFR_VAL
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ldr r2, =0xFFF
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and r3, r3, r2
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ldr r0, [r1, #MDREFR_OFFSET]
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bic r0, r0, r2
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bic r0, r0, #(MDREFR_K0FREE|MDREFR_K1FREE|MDREFR_K2FREE)
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orr r0, r0, r3
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str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
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/* ---------------------------------------------------------------- */
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/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
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/* ---------------------------------------------------------------- */
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/* Initialize SXCNFG register. Assert the enable bits */
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/* Write SXMRS to cause an MRS command to all enabled banks of */
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/* synchronous static memory. Note that SXLCR need not be written */
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/* at this time. */
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/* FIXME: we use async mode for now */
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/* ---------------------------------------------------------------- */
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/* Step 4: Initialize SDRAM */
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/* ---------------------------------------------------------------- */
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/* set MDREFR according to user define with exception of a few bits */
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ldr r4, =CONFIG_SYS_MDREFR_VAL
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ldr r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
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MDREFR_K2RUN |MDREFR_K2DB2)
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and r4, r4, r2
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bic r0, r0, r2
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orr r0, r0, r4
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str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
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ldr r0, [r1, #MDREFR_OFFSET]
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/* Step 4b: de-assert MDREFR:SLFRSH. */
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bic r0, r0, #(MDREFR_SLFRSH)
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str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
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ldr r0, [r1, #MDREFR_OFFSET]
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/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE */
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ldr r4, =CONFIG_SYS_MDREFR_VAL
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ldr r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
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MDREFR_K1FREE | MDREFR_K2FREE)
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and r4, r4, r2
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orr r0, r0, r4
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str r0, [r1, #MDREFR_OFFSET] /* write back MDREFR */
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ldr r0, [r1, #MDREFR_OFFSET]
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/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
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/* configure but not enable each SDRAM partition pair. */
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ldr r4, =CONFIG_SYS_MDCNFG_VAL
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bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
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bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
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str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
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ldr r4, [r1, #MDCNFG_OFFSET]
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/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
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/* 100..200 µsec. */
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ldr r3, =OSCR /* reset the OS Timer Count to zero */
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mov r2, #0
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str r2, [r3]
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ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
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/* so 0x300 should be plenty */
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1:
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ldr r2, [r3]
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cmp r4, r2
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bgt 1b
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/* Step 4f: Trigger a number (usually 8) refresh cycles by */
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/* attempting non-burst read or write accesses to disabled */
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/* SDRAM, as commonly specified in the power up sequence */
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/* documented in SDRAM data sheets. The address(es) used */
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/* for this purpose must not be cacheable. */
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ldr r3, =CONFIG_SYS_DRAM_BASE
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.rept 8
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str r2, [r3]
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.endr
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/* Step 4g: Write MDCNFG with enable bits asserted */
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/* (MDCNFG:DEx set to 1). */
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ldr r3, [r1, #MDCNFG_OFFSET]
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orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1)
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str r3, [r1, #MDCNFG_OFFSET]
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/* Step 4h: Write MDMRS. */
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ldr r2, =CONFIG_SYS_MDMRS_VAL
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str r2, [r1, #MDMRS_OFFSET]
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/* We are finished with Intel's memory controller initialisation */
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/* ---------------------------------------------------------------- */
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/* Disable (mask) all interrupts at interrupt controller */
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/* ---------------------------------------------------------------- */
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initirqs:
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mov r1, #0 /* clear int. level register (IRQ, not FIQ) */
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ldr r2, =ICLR
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str r1, [r2]
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ldr r2, =ICMR /* mask all interrupts at the controller */
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str r1, [r2]
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/* ---------------------------------------------------------------- */
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/* Clock initialisation */
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/* ---------------------------------------------------------------- */
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initclks:
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/* Disable the peripheral clocks, and set the core clock frequency */
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/* Turn Off ALL on-chip peripheral clocks for re-configuration */
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/* Note: See label 'ENABLECLKS' for the re-enabling */
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ldr r1, =CKEN
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mov r2, #0
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str r2, [r1]
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/* default value in case no valid rotary switch setting is found */
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ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */
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/* ... and write the core clock config register */
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ldr r1, =CCCR
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str r2, [r1]
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#ifdef RTC
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/* enable the 32Khz oscillator for RTC and PowerManager */
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ldr r1, =OSCC
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mov r2, #OSCC_OON
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str r2, [r1]
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/* NOTE: spin here until OSCC.OOK get set, meaning the PLL */
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/* has settled. */
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60:
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ldr r2, [r1]
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ands r2, r2, #1
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beq 60b
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#endif
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/* ---------------------------------------------------------------- */
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/* */
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/* ---------------------------------------------------------------- */
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/* Save SDRAM size */
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ldr r1, =DRAM_SIZE
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str r8, [r1]
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/* Interrupt init: Mask all interrupts */
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ldr r0, =ICMR /* enable no sources */
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mov r1, #0
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str r1, [r0]
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/* FIXME */
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#define NODEBUG
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#ifdef NODEBUG
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/*Disable software and data breakpoints */
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mov r0,#0
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mcr p15,0,r0,c14,c8,0 /* ibcr0 */
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mcr p15,0,r0,c14,c9,0 /* ibcr1 */
|
||||
mcr p15,0,r0,c14,c4,0 /* dbcon */
|
||||
|
||||
/*Enable all debug functionality */
|
||||
mov r0,#0x80000000
|
||||
mcr p14,0,r0,c10,c0,0 /* dcsr */
|
||||
|
||||
#endif
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* End lowlevel_init */
|
||||
/* ---------------------------------------------------------------- */
|
||||
|
||||
endlowlevel_init:
|
||||
|
||||
mov pc, lr
|
||||
|
|
@ -38,6 +38,7 @@
|
|||
#define CONFIG_CERF250 1 /* on Cerf PXA Board */
|
||||
#define BOARD_LATE_INIT 1
|
||||
#define CONFIG_BAUDRATE 38400
|
||||
#define CONFIG_SYS_TEXT_BASE 0x0
|
||||
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
|
||||
|
|
@ -140,15 +141,9 @@
|
|||
/*
|
||||
* Physical Memory Map
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
|
||||
#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
|
||||
#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
|
||||
#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
|
||||
#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
|
||||
#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
|
||||
#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
|
||||
#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
|
||||
#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
|
||||
#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
|
||||
|
||||
#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
|
||||
#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
|
||||
|
|
@ -187,6 +182,9 @@
|
|||
|
||||
#define CONFIG_SYS_PSSR_VAL 0x20
|
||||
|
||||
#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
|
||||
#define CONFIG_SYS_CKEN 0x0
|
||||
|
||||
/*
|
||||
* Memory settings
|
||||
*/
|
||||
|
|
@ -196,6 +194,8 @@
|
|||
#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9
|
||||
#define CONFIG_SYS_MDREFR_VAL 0x03CDC017
|
||||
#define CONFIG_SYS_MDMRS_VAL 0x00000000
|
||||
#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
|
||||
#define CONFIG_SYS_SXCNFG_VAL 0x00000000
|
||||
|
||||
/*
|
||||
* PCMCIA and CF Interfaces
|
||||
|
|
|
|||
Loading…
Reference in a new issue