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https://github.com/AsahiLinux/u-boot
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Merge tag 'arc-fixes-for-2020.07-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-arc
Here we improve clock support for recently introduced HSDK-4xD board as well as finally enable external reset for the USB controller, which is needed to recover USB functionality after "usb reset".
This commit is contained in:
Tom Rini
commit
cae802924e
5 changed files with 220 additions and 164 deletions
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@ -62,12 +62,12 @@
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max-speed = <100>;
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};
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ehci@0x40000 {
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ehci@40000 {
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compatible = "generic-ehci";
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reg = < 0x40000 0x100 >;
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};
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ohci@0x60000 {
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ohci@60000 {
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compatible = "generic-ohci";
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reg = < 0x60000 0x100 >;
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};
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@ -84,12 +84,19 @@
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phy-mode = "gmii";
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};
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ehci@0xf0040000 {
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ehci@f0040000 {
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compatible = "generic-ehci";
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reg = <0xf0040000 0x100>;
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/*
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* OHCI and EHCI have reset line shared so we don't add
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* reset property to OHCI node as it is probed later and
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* it will reset sucessfuly probed and configured EHCI HW.
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*/
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resets = <&cgu_rst HSDK_USB_RESET>;
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};
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ohci@0xf0060000 {
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ohci@f0060000 {
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compatible = "generic-ohci";
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reg = <0xf0060000 0x100>;
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};
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@ -42,6 +42,8 @@ DECLARE_GLOBAL_DATA_PTR;
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#define CREG_CPU_START_MASK 0xF
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#define CREG_CPU_START_POL BIT(4)
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#define CREG_CORE_BOOT_IMAGE GENMASK(5, 4)
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#define CREG_CPU_0_ENTRY (CREG_BASE + 0x404)
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#define SDIO_BASE (ARC_PERIPHERAL_BASE + 0xA000)
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@ -1241,11 +1243,16 @@ int board_late_init(void)
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int checkboard(void)
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{
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u32 reg;
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printf("Board: Synopsys %s\n", board_name(get_board_type_runtime()));
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if (board_mismatch())
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printf("WARN: U-boot is configured NOT for this board but for %s!\n",
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board_name(get_board_type_config()));
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reg = readl(CREG_AXI_M_HS_CORE_BOOT) & CREG_CORE_BOOT_IMAGE;
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printf("U-boot autostart: %s\n", reg ? "enabled" : "disabled");
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return 0;
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};
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@ -100,10 +100,11 @@ config CLK_TI_SCI
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managed by the TI System Controller, say Y here. Otherwise, say N.
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config CLK_HSDK
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bool "Enable cgu clock driver for HSDK"
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depends on CLK
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bool "Enable cgu clock driver for HSDK boards"
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depends on CLK && TARGET_HSDK
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help
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Enable this to support the cgu clocks on Synopsys ARC HSDK
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Enable this to support the cgu clocks on Synopsys ARC HSDK and
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Synopsys ARC HSDK-4xD boards
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config CLK_VERSAL
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bool "Enable clock driver support for Versal"
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@ -14,6 +14,9 @@
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#include <div64.h>
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#include <dm.h>
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#include <linux/io.h>
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#include <asm/arcregs.h>
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#include <dt-bindings/clock/snps,hsdk-cgu.h>
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/*
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* Synopsys ARC HSDK clock tree.
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@ -126,45 +129,41 @@
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#define PARENT_RATE_27 27000000 /* fixed clock - xtal */
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#define CGU_MAX_CLOCKS 27
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#define CGU_SYS_CLOCKS 16
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#define MAX_AXI_CLOCKS 4
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#define MAX_FREQ_VARIATIONS 6
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#define CGU_TUN_CLOCKS 4
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#define MAX_TUN_CLOCKS 6
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struct hsdk_tun_idiv_cfg {
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u32 oft;
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u8 val[MAX_TUN_CLOCKS];
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struct hsdk_idiv_cfg {
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const u32 oft;
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const u8 val[MAX_FREQ_VARIATIONS];
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};
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struct hsdk_tun_clk_cfg {
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const u32 clk_rate[MAX_TUN_CLOCKS];
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const u32 pll_rate[MAX_TUN_CLOCKS];
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const struct hsdk_tun_idiv_cfg idiv[CGU_TUN_CLOCKS];
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struct hsdk_div_full_cfg {
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const u32 clk_rate[MAX_FREQ_VARIATIONS];
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const u32 pll_rate[MAX_FREQ_VARIATIONS];
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const struct hsdk_idiv_cfg idiv[];
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};
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static const struct hsdk_tun_clk_cfg tun_clk_cfg = {
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static const struct hsdk_div_full_cfg hsdk_4xd_tun_clk_cfg = {
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{ 25000000, 50000000, 75000000, 100000000, 125000000, 150000000 },
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{ 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
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{ CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
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{ CGU_TUN_IDIV_ROM, { 4, 4, 4, 4, 5, 4 } },
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{ CGU_TUN_IDIV_PWM, { 8, 8, 8, 8, 10, 8 } },
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{ CGU_TUN_IDIV_TIMER, { 12, 12, 12, 12, 15, 12 } }
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{ CGU_TUN_IDIV_TIMER, { 12, 12, 12, 12, 15, 12 } },
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{ /* last one */ }
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}
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};
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struct hsdk_sys_idiv_cfg {
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u32 oft;
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u8 val[MAX_AXI_CLOCKS];
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static const struct hsdk_div_full_cfg hsdk_tun_clk_cfg = {
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{ 25000000, 50000000, 75000000, 100000000, 125000000, 150000000 },
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{ 600000000, 600000000, 600000000, 600000000, 750000000, 600000000 }, {
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{ CGU_TUN_IDIV_TUN, { 24, 12, 8, 6, 6, 4 } },
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{ CGU_TUN_IDIV_ROM, { 4, 4, 4, 4, 5, 4 } },
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{ CGU_TUN_IDIV_PWM, { 8, 8, 8, 8, 10, 8 } },
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{ /* last one */ }
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}
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};
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struct hsdk_axi_clk_cfg {
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const u32 clk_rate[MAX_AXI_CLOCKS];
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const u32 pll_rate[MAX_AXI_CLOCKS];
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const struct hsdk_sys_idiv_cfg idiv[CGU_SYS_CLOCKS];
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};
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static const struct hsdk_axi_clk_cfg axi_clk_cfg = {
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static const struct hsdk_div_full_cfg axi_clk_cfg = {
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{ 200000000, 400000000, 600000000, 800000000 },
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{ 800000000, 800000000, 600000000, 800000000 }, {
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{ CGU_SYS_IDIV_APB, { 4, 4, 3, 4 } }, /* APB */
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@ -182,16 +181,17 @@ static const struct hsdk_axi_clk_cfg axi_clk_cfg = {
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{ CGU_SYS_IDIV_SPI_REF, { 24, 24, 18, 24 } }, /* SPI-REF */
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{ CGU_SYS_IDIV_I2C_REF, { 4, 4, 3, 4 } }, /* I2C-REF */
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{ CGU_SYS_IDIV_UART_REF, { 24, 24, 18, 24 } }, /* UART-REF */
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{ CGU_SYS_IDIV_EBI_REF, { 16, 16, 12, 16 } } /* EBI-REF */
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{ CGU_SYS_IDIV_EBI_REF, { 16, 16, 12, 16 } }, /* EBI-REF */
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{ /* last one */ }
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}
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};
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struct hsdk_pll_cfg {
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u32 rate;
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u32 idiv;
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u32 fbdiv;
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u32 odiv;
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u32 band;
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const u32 rate;
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const u8 idiv;
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const u8 fbdiv;
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const u8 odiv;
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const u8 band;
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};
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static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
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@ -227,28 +227,35 @@ static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
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{}
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};
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struct hsdk_cgu_clk {
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/* CGU block register */
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void __iomem *cgu_regs;
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/* CREG block register */
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void __iomem *creg_regs;
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struct hsdk_cgu_domain {
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/* PLLs registers */
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void __iomem *regs;
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void __iomem *pll_regs;
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/* PLLs special registers */
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void __iomem *spec_regs;
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/* PLLs devdata */
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const struct hsdk_pll_devdata *pll_devdata;
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const struct hsdk_pll_devdata *pll;
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/* Dividers registers */
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void __iomem *idiv_regs;
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};
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struct hsdk_cgu_clk {
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const struct cgu_clk_map *map;
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/* CGU block register */
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void __iomem *cgu_regs;
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/* CREG block register */
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void __iomem *creg_regs;
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/* The domain we are working with */
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struct hsdk_cgu_domain curr_domain;
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};
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struct hsdk_pll_devdata {
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const u32 parent_rate;
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const struct hsdk_pll_cfg *pll_cfg;
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int (*update_rate)(struct hsdk_cgu_clk *clk, unsigned long rate,
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const struct hsdk_pll_cfg *cfg);
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const struct hsdk_pll_cfg *const pll_cfg;
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const int (*const update_rate)(struct hsdk_cgu_clk *clk,
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unsigned long rate,
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const struct hsdk_pll_cfg *cfg);
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};
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static int hsdk_pll_core_update_rate(struct hsdk_cgu_clk *, unsigned long,
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@ -277,80 +284,110 @@ static const struct hsdk_pll_devdata hdmi_pll_dat = {
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static ulong idiv_set(struct clk *, ulong);
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static ulong cpu_clk_set(struct clk *, ulong);
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static ulong axi_clk_set(struct clk *, ulong);
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static ulong tun_clk_set(struct clk *, ulong);
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static ulong tun_hsdk_set(struct clk *, ulong);
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static ulong tun_h4xd_set(struct clk *, ulong);
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static ulong idiv_get(struct clk *);
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static int idiv_off(struct clk *);
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static ulong pll_set(struct clk *, ulong);
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static ulong pll_get(struct clk *);
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struct hsdk_cgu_clock_map {
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u32 cgu_pll_oft;
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u32 creg_div_oft;
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u32 cgu_div_oft;
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const struct hsdk_pll_devdata *pll_devdata;
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ulong (*get_rate)(struct clk *clk);
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ulong (*set_rate)(struct clk *clk, ulong rate);
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int (*disable)(struct clk *clk);
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struct cgu_clk_map {
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const u32 cgu_pll_oft;
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const u32 cgu_div_oft;
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const struct hsdk_pll_devdata *const pll_devdata;
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const ulong (*const get_rate)(struct clk *clk);
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const ulong (*const set_rate)(struct clk *clk, ulong rate);
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const int (*const disable)(struct clk *clk);
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};
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static const struct hsdk_cgu_clock_map clock_map[] = {
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{ CGU_ARC_PLL, 0, 0, &core_pll_dat, pll_get, pll_set, NULL },
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{ CGU_ARC_PLL, 0, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off },
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{ CGU_DDR_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
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{ CGU_SYS_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_HDMI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_DMA, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_GFX_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_DMAC_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_SDIO_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_SPI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_I2C_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_SYS_PLL, 0, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_TUN_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
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{ CGU_TUN_PLL, 0, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_clk_set, idiv_off },
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{ CGU_TUN_PLL, 0, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_TUN_PLL, 0, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_TUN_PLL, 0, CGU_TUN_IDIV_TIMER, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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{ CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
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{ CGU_HDMI_PLL, 0, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
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static const struct cgu_clk_map hsdk_clk_map[] = {
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[CLK_ARC_PLL] = { CGU_ARC_PLL, 0, &core_pll_dat, pll_get, pll_set, NULL },
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[CLK_ARC] = { CGU_ARC_PLL, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off },
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[CLK_DDR_PLL] = { CGU_DDR_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
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[CLK_SYS_PLL] = { CGU_SYS_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
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[CLK_SYS_APB] = { CGU_SYS_PLL, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_SYS_AXI] = { CGU_SYS_PLL, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off },
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[CLK_SYS_ETH] = { CGU_SYS_PLL, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_SYS_USB] = { CGU_SYS_PLL, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_SYS_SDIO] = { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_SYS_HDMI] = { CGU_SYS_PLL, CGU_SYS_IDIV_HDMI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_SYS_GFX_CORE] = { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_SYS_GFX_DMA] = { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_DMA, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_SYS_GFX_CFG] = { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_SYS_DMAC_CORE] = { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_SYS_DMAC_CFG] = { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_SYS_SDIO_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_SYS_SPI_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_SPI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_SYS_I2C_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_I2C_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_SYS_UART_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_SYS_EBI_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_TUN_PLL] = { CGU_TUN_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
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[CLK_TUN_TUN] = { CGU_TUN_PLL, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_hsdk_set, idiv_off },
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[CLK_TUN_ROM] = { CGU_TUN_PLL, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_TUN_PWM] = { CGU_TUN_PLL, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
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[CLK_TUN_TIMER] = { /* missing in HSDK */ },
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[CLK_HDMI_PLL] = { CGU_HDMI_PLL, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
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[CLK_HDMI] = { CGU_HDMI_PLL, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
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};
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static const struct cgu_clk_map hsdk_4xd_clk_map[] = {
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[CLK_ARC_PLL] = { CGU_ARC_PLL, 0, &core_pll_dat, pll_get, pll_set, NULL },
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[CLK_ARC] = { CGU_ARC_PLL, CGU_ARC_IDIV, &core_pll_dat, idiv_get, cpu_clk_set, idiv_off },
|
||||
[CLK_DDR_PLL] = { CGU_DDR_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
|
||||
[CLK_SYS_PLL] = { CGU_SYS_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
|
||||
[CLK_SYS_APB] = { CGU_SYS_PLL, CGU_SYS_IDIV_APB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
|
||||
[CLK_SYS_AXI] = { CGU_SYS_PLL, CGU_SYS_IDIV_AXI, &sdt_pll_dat, idiv_get, axi_clk_set, idiv_off },
|
||||
[CLK_SYS_ETH] = { CGU_SYS_PLL, CGU_SYS_IDIV_ETH, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
|
||||
[CLK_SYS_USB] = { CGU_SYS_PLL, CGU_SYS_IDIV_USB, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
|
||||
[CLK_SYS_SDIO] = { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
|
||||
[CLK_SYS_HDMI] = { CGU_SYS_PLL, CGU_SYS_IDIV_HDMI, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
|
||||
[CLK_SYS_GFX_CORE] = { CGU_SYS_PLL, CGU_SYS_IDIV_GFX_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
|
||||
[CLK_SYS_GFX_DMA] = { /* missing in HSDK-4xD */ },
|
||||
[CLK_SYS_GFX_CFG] = { /* missing in HSDK-4xD */ },
|
||||
[CLK_SYS_DMAC_CORE] = { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CORE, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
|
||||
[CLK_SYS_DMAC_CFG] = { CGU_SYS_PLL, CGU_SYS_IDIV_DMAC_CFG, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
|
||||
[CLK_SYS_SDIO_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_SDIO_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
|
||||
[CLK_SYS_SPI_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_SPI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
|
||||
[CLK_SYS_I2C_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_I2C_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
|
||||
[CLK_SYS_UART_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_UART_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
|
||||
[CLK_SYS_EBI_REF] = { CGU_SYS_PLL, CGU_SYS_IDIV_EBI_REF, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
|
||||
[CLK_TUN_PLL] = { CGU_TUN_PLL, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
|
||||
[CLK_TUN_TUN] = { CGU_TUN_PLL, CGU_TUN_IDIV_TUN, &sdt_pll_dat, idiv_get, tun_h4xd_set, idiv_off },
|
||||
[CLK_TUN_ROM] = { CGU_TUN_PLL, CGU_TUN_IDIV_ROM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
|
||||
[CLK_TUN_PWM] = { CGU_TUN_PLL, CGU_TUN_IDIV_PWM, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
|
||||
[CLK_TUN_TIMER] = { CGU_TUN_PLL, CGU_TUN_IDIV_TIMER, &sdt_pll_dat, idiv_get, idiv_set, idiv_off },
|
||||
[CLK_HDMI_PLL] = { CGU_HDMI_PLL, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
|
||||
[CLK_HDMI] = { CGU_HDMI_PLL, CGU_HDMI_IDIV_APB, &hdmi_pll_dat, idiv_get, idiv_set, idiv_off }
|
||||
};
|
||||
|
||||
static inline void hsdk_idiv_write(struct hsdk_cgu_clk *clk, u32 val)
|
||||
{
|
||||
iowrite32(val, clk->idiv_regs);
|
||||
iowrite32(val, clk->curr_domain.idiv_regs);
|
||||
}
|
||||
|
||||
static inline u32 hsdk_idiv_read(struct hsdk_cgu_clk *clk)
|
||||
{
|
||||
return ioread32(clk->idiv_regs);
|
||||
return ioread32(clk->curr_domain.idiv_regs);
|
||||
}
|
||||
|
||||
static inline void hsdk_pll_write(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
|
||||
{
|
||||
iowrite32(val, clk->regs + reg);
|
||||
iowrite32(val, clk->curr_domain.pll_regs + reg);
|
||||
}
|
||||
|
||||
static inline u32 hsdk_pll_read(struct hsdk_cgu_clk *clk, u32 reg)
|
||||
{
|
||||
return ioread32(clk->regs + reg);
|
||||
return ioread32(clk->curr_domain.pll_regs + reg);
|
||||
}
|
||||
|
||||
static inline void hsdk_pll_spcwrite(struct hsdk_cgu_clk *clk, u32 reg, u32 val)
|
||||
{
|
||||
iowrite32(val, clk->spec_regs + reg);
|
||||
iowrite32(val, clk->curr_domain.spec_regs + reg);
|
||||
}
|
||||
|
||||
static inline u32 hsdk_pll_spcread(struct hsdk_cgu_clk *clk, u32 reg)
|
||||
{
|
||||
return ioread32(clk->spec_regs + reg);
|
||||
return ioread32(clk->curr_domain.spec_regs + reg);
|
||||
}
|
||||
|
||||
static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk *clk,
|
||||
|
|
@ -359,10 +396,10 @@ static inline void hsdk_pll_set_cfg(struct hsdk_cgu_clk *clk,
|
|||
u32 val = 0;
|
||||
|
||||
/* Powerdown and Bypass bits should be cleared */
|
||||
val |= cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
|
||||
val |= cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
|
||||
val |= cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
|
||||
val |= cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
|
||||
val |= (u32)cfg->idiv << CGU_PLL_CTRL_IDIV_SHIFT;
|
||||
val |= (u32)cfg->fbdiv << CGU_PLL_CTRL_FBDIV_SHIFT;
|
||||
val |= (u32)cfg->odiv << CGU_PLL_CTRL_ODIV_SHIFT;
|
||||
val |= (u32)cfg->band << CGU_PLL_CTRL_BAND_SHIFT;
|
||||
|
||||
pr_debug("write configurarion: %#x\n", val);
|
||||
|
||||
|
|
@ -385,7 +422,7 @@ static ulong pll_get(struct clk *sclk)
|
|||
u64 rate;
|
||||
u32 idiv, fbdiv, odiv;
|
||||
struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
|
||||
u32 parent_rate = clk->pll_devdata->parent_rate;
|
||||
u32 parent_rate = clk->curr_domain.pll->parent_rate;
|
||||
|
||||
val = hsdk_pll_read(clk, CGU_PLL_CTRL);
|
||||
|
||||
|
|
@ -417,7 +454,7 @@ static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate)
|
|||
int i;
|
||||
unsigned long best_rate;
|
||||
struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
|
||||
const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
|
||||
const struct hsdk_pll_cfg *pll_cfg = clk->curr_domain.pll->pll_cfg;
|
||||
|
||||
if (pll_cfg[0].rate == 0)
|
||||
return -EINVAL;
|
||||
|
|
@ -493,19 +530,17 @@ static ulong pll_set(struct clk *sclk, ulong rate)
|
|||
int i;
|
||||
unsigned long best_rate;
|
||||
struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
|
||||
const struct hsdk_pll_cfg *pll_cfg = clk->pll_devdata->pll_cfg;
|
||||
const struct hsdk_pll_devdata *pll = clk->curr_domain.pll;
|
||||
const struct hsdk_pll_cfg *pll_cfg = pll->pll_cfg;
|
||||
|
||||
best_rate = hsdk_pll_round_rate(sclk, rate);
|
||||
|
||||
for (i = 0; pll_cfg[i].rate != 0; i++) {
|
||||
if (pll_cfg[i].rate == best_rate) {
|
||||
return clk->pll_devdata->update_rate(clk, best_rate,
|
||||
&pll_cfg[i]);
|
||||
}
|
||||
}
|
||||
for (i = 0; pll_cfg[i].rate != 0; i++)
|
||||
if (pll_cfg[i].rate == best_rate)
|
||||
return pll->update_rate(clk, best_rate, &pll_cfg[i]);
|
||||
|
||||
pr_err("invalid rate=%ld Hz, parent_rate=%d Hz\n", best_rate,
|
||||
clk->pll_devdata->parent_rate);
|
||||
pll->parent_rate);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
@ -546,8 +581,13 @@ static ulong cpu_clk_set(struct clk *sclk, ulong rate)
|
|||
return ret;
|
||||
}
|
||||
|
||||
/* Special behavior: wen we set this clock we set both idiv and pll and all pll dividers */
|
||||
static ulong axi_clk_set(struct clk *sclk, ulong rate)
|
||||
/*
|
||||
* Special behavior:
|
||||
* when we set these clocks we set both PLL and all idiv dividers related to
|
||||
* this PLL domain.
|
||||
*/
|
||||
static ulong common_div_clk_set(struct clk *sclk, ulong rate,
|
||||
const struct hsdk_div_full_cfg *cfg)
|
||||
{
|
||||
struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
|
||||
ulong pll_rate;
|
||||
|
|
@ -556,71 +596,52 @@ static ulong axi_clk_set(struct clk *sclk, ulong rate)
|
|||
|
||||
pll_rate = pll_get(sclk);
|
||||
|
||||
for (i = 0; i < MAX_AXI_CLOCKS; i++) {
|
||||
if (axi_clk_cfg.clk_rate[i] == rate) {
|
||||
for (i = 0; i < MAX_FREQ_VARIATIONS; i++) {
|
||||
/* unused freq variations are filled with 0 */
|
||||
if (!cfg->clk_rate[i])
|
||||
break;
|
||||
|
||||
if (cfg->clk_rate[i] == rate) {
|
||||
freq_idx = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (freq_idx < 0) {
|
||||
pr_err("axi clk: invalid rate=%ld Hz\n", rate);
|
||||
pr_err("clk: invalid rate=%ld Hz\n", rate);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* configure PLL before dividers */
|
||||
if (axi_clk_cfg.pll_rate[freq_idx] < pll_rate)
|
||||
ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
|
||||
if (cfg->pll_rate[freq_idx] < pll_rate)
|
||||
ret = pll_set(sclk, cfg->pll_rate[freq_idx]);
|
||||
|
||||
/* configure SYS dividers */
|
||||
for (i = 0; i < CGU_SYS_CLOCKS; i++) {
|
||||
clk->idiv_regs = clk->cgu_regs + axi_clk_cfg.idiv[i].oft;
|
||||
hsdk_idiv_write(clk, axi_clk_cfg.idiv[i].val[freq_idx]);
|
||||
for (i = 0; cfg->idiv[i].oft != 0; i++) {
|
||||
clk->curr_domain.idiv_regs = clk->cgu_regs + cfg->idiv[i].oft;
|
||||
hsdk_idiv_write(clk, cfg->idiv[i].val[freq_idx]);
|
||||
}
|
||||
|
||||
/* configure PLL after dividers */
|
||||
if (axi_clk_cfg.pll_rate[freq_idx] >= pll_rate)
|
||||
ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]);
|
||||
if (cfg->pll_rate[freq_idx] >= pll_rate)
|
||||
ret = pll_set(sclk, cfg->pll_rate[freq_idx]);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static ulong tun_clk_set(struct clk *sclk, ulong rate)
|
||||
static ulong axi_clk_set(struct clk *sclk, ulong rate)
|
||||
{
|
||||
struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
|
||||
ulong pll_rate;
|
||||
int i, freq_idx = -1;
|
||||
ulong ret = 0;
|
||||
return common_div_clk_set(sclk, rate, &axi_clk_cfg);
|
||||
}
|
||||
|
||||
pll_rate = pll_get(sclk);
|
||||
static ulong tun_hsdk_set(struct clk *sclk, ulong rate)
|
||||
{
|
||||
return common_div_clk_set(sclk, rate, &hsdk_tun_clk_cfg);
|
||||
}
|
||||
|
||||
for (i = 0; i < MAX_TUN_CLOCKS; i++) {
|
||||
if (tun_clk_cfg.clk_rate[i] == rate) {
|
||||
freq_idx = i;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (freq_idx < 0) {
|
||||
pr_err("tun clk: invalid rate=%ld Hz\n", rate);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* configure PLL before dividers */
|
||||
if (tun_clk_cfg.pll_rate[freq_idx] < pll_rate)
|
||||
ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
|
||||
|
||||
/* configure SYS dividers */
|
||||
for (i = 0; i < CGU_TUN_CLOCKS; i++) {
|
||||
clk->idiv_regs = clk->cgu_regs + tun_clk_cfg.idiv[i].oft;
|
||||
hsdk_idiv_write(clk, tun_clk_cfg.idiv[i].val[freq_idx]);
|
||||
}
|
||||
|
||||
/* configure PLL after dividers */
|
||||
if (tun_clk_cfg.pll_rate[freq_idx] >= pll_rate)
|
||||
ret = pll_set(sclk, tun_clk_cfg.pll_rate[freq_idx]);
|
||||
|
||||
return ret;
|
||||
static ulong tun_h4xd_set(struct clk *sclk, ulong rate)
|
||||
{
|
||||
return common_div_clk_set(sclk, rate, &hsdk_4xd_tun_clk_cfg);
|
||||
}
|
||||
|
||||
static ulong idiv_set(struct clk *sclk, ulong rate)
|
||||
|
|
@ -661,37 +682,50 @@ static int hsdk_prepare_clock_tree_branch(struct clk *sclk)
|
|||
if (sclk->id >= CGU_MAX_CLOCKS)
|
||||
return -EINVAL;
|
||||
|
||||
clk->pll_devdata = clock_map[sclk->id].pll_devdata;
|
||||
clk->regs = clk->cgu_regs + clock_map[sclk->id].cgu_pll_oft;
|
||||
clk->spec_regs = clk->creg_regs + clock_map[sclk->id].creg_div_oft;
|
||||
clk->idiv_regs = clk->cgu_regs + clock_map[sclk->id].cgu_div_oft;
|
||||
/* clocks missing in current map have their entry zeroed */
|
||||
if (!clk->map[sclk->id].pll_devdata)
|
||||
return -EINVAL;
|
||||
|
||||
clk->curr_domain.pll = clk->map[sclk->id].pll_devdata;
|
||||
clk->curr_domain.pll_regs = clk->cgu_regs + clk->map[sclk->id].cgu_pll_oft;
|
||||
clk->curr_domain.spec_regs = clk->creg_regs;
|
||||
clk->curr_domain.idiv_regs = clk->cgu_regs + clk->map[sclk->id].cgu_div_oft;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static ulong hsdk_cgu_get_rate(struct clk *sclk)
|
||||
{
|
||||
struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
|
||||
|
||||
if (hsdk_prepare_clock_tree_branch(sclk))
|
||||
return -EINVAL;
|
||||
|
||||
return clock_map[sclk->id].get_rate(sclk);
|
||||
return clk->map[sclk->id].get_rate(sclk);
|
||||
}
|
||||
|
||||
static ulong hsdk_cgu_set_rate(struct clk *sclk, ulong rate)
|
||||
{
|
||||
struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
|
||||
|
||||
if (hsdk_prepare_clock_tree_branch(sclk))
|
||||
return -EINVAL;
|
||||
|
||||
return clock_map[sclk->id].set_rate(sclk, rate);
|
||||
if (clk->map[sclk->id].set_rate)
|
||||
return clk->map[sclk->id].set_rate(sclk, rate);
|
||||
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static int hsdk_cgu_disable(struct clk *sclk)
|
||||
{
|
||||
struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
|
||||
|
||||
if (hsdk_prepare_clock_tree_branch(sclk))
|
||||
return -EINVAL;
|
||||
|
||||
if (clock_map[sclk->id].disable)
|
||||
return clock_map[sclk->id].disable(sclk);
|
||||
if (clk->map[sclk->id].disable)
|
||||
return clk->map[sclk->id].disable(sclk);
|
||||
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
|
@ -704,16 +738,23 @@ static const struct clk_ops hsdk_cgu_ops = {
|
|||
|
||||
static int hsdk_cgu_clk_probe(struct udevice *dev)
|
||||
{
|
||||
struct hsdk_cgu_clk *pll_clk = dev_get_priv(dev);
|
||||
struct hsdk_cgu_clk *hsdk_clk = dev_get_priv(dev);
|
||||
|
||||
BUILD_BUG_ON(ARRAY_SIZE(clock_map) != CGU_MAX_CLOCKS);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(hsdk_clk_map) != CGU_MAX_CLOCKS);
|
||||
BUILD_BUG_ON(ARRAY_SIZE(hsdk_4xd_clk_map) != CGU_MAX_CLOCKS);
|
||||
|
||||
pll_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
|
||||
if (!pll_clk->cgu_regs)
|
||||
/* Choose which clock map to use in runtime */
|
||||
if ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF) == 0x52)
|
||||
hsdk_clk->map = hsdk_clk_map;
|
||||
else
|
||||
hsdk_clk->map = hsdk_4xd_clk_map;
|
||||
|
||||
hsdk_clk->cgu_regs = (void __iomem *)devfdt_get_addr_index(dev, 0);
|
||||
if (!hsdk_clk->cgu_regs)
|
||||
return -EINVAL;
|
||||
|
||||
pll_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
|
||||
if (!pll_clk->creg_regs)
|
||||
hsdk_clk->creg_regs = (void __iomem *)devfdt_get_addr_index(dev, 1);
|
||||
if (!hsdk_clk->creg_regs)
|
||||
return -EINVAL;
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
Loading…
Reference in a new issue