From ca729cd16cca26a8d8a1746e3080937206aca615 Mon Sep 17 00:00:00 2001
From: Ye Li <ye.li@nxp.com>
Date: Thu, 8 Aug 2019 09:59:02 +0000
Subject: [PATCH] ddr: imx8m: Fix ddr4 driver build issue

Since the parameter of dram_pll_init is changed, update to use new.
Also remove non-existed header file.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/ddr/imx/imx8m/ddr4_init.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/ddr/imx/imx8m/ddr4_init.c b/drivers/ddr/imx/imx8m/ddr4_init.c
index 031cdc57e1..b8aa104536 100644
--- a/drivers/ddr/imx/imx8m/ddr4_init.c
+++ b/drivers/ddr/imx/imx8m/ddr4_init.c
@@ -8,7 +8,6 @@
 #include <asm/io.h>
 #include <asm/arch/ddr.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/imx8m_ddr.h>
 #include <asm/arch/sys_proto.h>
 
 void ddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
@@ -41,7 +40,7 @@ void ddr_init(struct dram_timing_info *dram_timing)
 			     CLK_ROOT_SOURCE_SEL(4) |
 			     CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
 
-	dram_pll_init(DRAM_PLL_OUT_600M);
+	dram_pll_init(MHZ(600));
 
 	reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
 	reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */