mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-27 15:12:21 +00:00
Merge branch 'master' of /home/wd/git/u-boot/custodians
This commit is contained in:
commit
c90d115913
18 changed files with 39 additions and 26 deletions
2
MAKEALL
2
MAKEALL
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@ -691,7 +691,7 @@ LIST_coldfire=" \
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M52277EVB \
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M5235EVB \
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M5249EVB \
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M5253EVB \
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M5253EVBE \
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M5271EVB \
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M5272C3 \
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M5275EVB \
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@ -201,7 +201,7 @@ int mii_discover_phy(struct eth_device *dev)
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}
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#endif /* CFG_DISCOVER_PHY */
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int mii_init(void) __attribute__((weak,alias("__mii_init")));
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void mii_init(void) __attribute__((weak,alias("__mii_init")));
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void __mii_init(void)
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{
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@ -200,7 +200,7 @@ int mii_discover_phy(struct eth_device *dev)
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}
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#endif /* CFG_DISCOVER_PHY */
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int mii_init(void) __attribute__((weak,alias("__mii_init")));
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void mii_init(void) __attribute__((weak,alias("__mii_init")));
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void __mii_init(void)
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{
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@ -75,9 +75,11 @@ phys_size_t initdram(int board_type)
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sdram->dacr0 =
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SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
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SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
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asm("nop");
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/* Initialize DMR0 */
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sdram->dmr0 = ((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V;
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asm("nop");
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/* Set IP (bit 3) in DACR */
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sdram->dacr0 |= SDRAMC_DARCn_IP;
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@ -100,6 +102,7 @@ phys_size_t initdram(int board_type)
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/* Finish the configuration by issuing the MRS. */
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sdram->dacr0 |= SDRAMC_DARCn_IMRS;
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asm("nop");
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/* Write to the SDRAM Mode Register */
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*(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
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@ -106,7 +106,7 @@ void cpu_init_f(void)
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*/
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int cpu_init_r(void)
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{
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#ifdef CONFIG_MCFTMR
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#ifdef CONFIG_MCFRTC
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volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
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volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
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u32 oscillator = CFG_RTC_OSCILLATOR;
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@ -419,8 +419,7 @@ void cpu_init_f(void)
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else is doing it! */
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#if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
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defined(CFG_CS0_WIDTH) & defined(CFG_CS0_RO) & \
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defined(CFG_CS0_WS)
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defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS)
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MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
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@ -447,8 +446,7 @@ void cpu_init_f(void)
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#endif
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#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
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defined(CFG_CS1_WIDTH) & defined(CFG_CS1_RO) & \
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defined(CFG_CS1_WS)
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defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS)
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MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
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@ -476,8 +474,7 @@ void cpu_init_f(void)
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#endif
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#if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
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defined(CFG_CS2_WIDTH) & defined(CFG_CS2_RO) & \
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defined(CFG_CS2_WS)
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defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS)
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MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
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@ -505,8 +502,7 @@ void cpu_init_f(void)
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#endif
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#if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
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defined(CFG_CS3_WIDTH) & defined(CFG_CS3_RO) & \
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defined(CFG_CS3_WS)
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defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS)
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MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
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@ -69,7 +69,7 @@ int get_clocks (void)
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/* Setup PLL */
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pll->syncr = 0x01080000;
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while (!(pll->synsr & FMPLL_SYNSR_LOCK)
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while (!(pll->synsr & FMPLL_SYNSR_LOCK))
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;
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pll->syncr = 0x01000000;
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while (!(pll->synsr & FMPLL_SYNSR_LOCK))
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@ -29,3 +29,9 @@ PLATFORM_CPPFLAGS += -mcpu=54455 -fPIC
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else
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PLATFORM_CPPFLAGS += -m5407 -fPIC
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endif
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ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
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ifneq (,$(findstring GOT,$(shell $(LD) --help)))
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PLATFORM_LDFLAGS += --got=single
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endif
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endif
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@ -110,7 +110,7 @@ void cpu_init_f(void)
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*/
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int cpu_init_r(void)
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{
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#ifdef CONFIG_MCFTMR
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#ifdef CONFIG_MCFRTC
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volatile rtc_t *rtc = (volatile rtc_t *)(CFG_MCFRTC_BASE);
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volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
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@ -253,7 +253,7 @@ clear_bss:
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/* exception code */
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.globl _fault
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_fault:
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jmp _fault
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bra _fault
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.globl _exc_handler
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_exc_handler:
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@ -29,3 +29,9 @@ PLATFORM_CPPFLAGS += -mcpu=5485 -fPIC
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else
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PLATFORM_CPPFLAGS += -m5407 -fPIC
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endif
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ifneq (,$(findstring -linux-,$(shell $(CC) --version)))
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ifneq (,$(findstring GOT,$(shell $(LD) --help)))
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PLATFORM_LDFLAGS += --got=single
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endif
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endif
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@ -259,7 +259,7 @@ clear_bss:
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/* exception code */
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.globl _fault
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_fault:
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jmp _fault
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bra _fault
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.globl _exc_handler
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_exc_handler:
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@ -63,8 +63,8 @@ int serial_init(void)
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uart->umr = UART_UMR_SB_STOP_BITS_1;
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/* Setting up BaudRate */
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counter = (u32) (gd->bus_clk / (gd->baudrate));
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counter >>= 5;
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counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
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counter = counter / gd->baudrate;
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/* write to CTUR: divide counter upper byte */
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uart->ubg1 = (u8) ((counter & 0xff00) >> 8);
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@ -33,7 +33,7 @@
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/****************************************************************************/
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/* DMA Timer module registers */
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typedef struct dtimer_ctrl {
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#if defined(CONFIG_M5249) || defined(CONFIG_M5253)
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#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5272)
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u16 tmr; /* 0x00 Mode register */
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u16 res1; /* 0x02 */
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u16 trr; /* 0x04 Reference register */
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@ -84,6 +84,8 @@
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NET
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#define CONFIG_MCFTMR
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#define CONFIG_MCFFEC
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#ifdef CONFIG_MCFFEC
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# define CONFIG_NET_MULTI 1
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@ -303,9 +303,9 @@
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#define CFG_CS0_CTRL 0x00101980
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#ifdef CFG_NOR1SZ
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#define CFG_CS1_BASE 0xF8000000
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#define CFG_CS1_BASE 0xE0000000
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#define CFG_CS1_MASK (((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
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#define CFG_CS1_CTRL 0x00000D80
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#define CFG_CS1_CTRL 0x00101D80
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#endif
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#endif /* _M5475EVB_H */
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@ -289,9 +289,9 @@
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#define CFG_CS0_CTRL 0x00101980
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#ifdef CFG_NOR1SZ
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#define CFG_CS1_BASE 0xF8000000
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#define CFG_CS1_BASE 0xE0000000
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#define CFG_CS1_MASK (((CFG_NOR1SZ << 20) - 1) & 0xFFFF0001)
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#define CFG_CS1_CTRL 0x00000D80
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#define CFG_CS1_CTRL 0x00101D80
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#endif
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#endif /* _M5485EVB_H */
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@ -176,7 +176,7 @@ typedef int (init_fnc_t) (void);
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static int init_baudrate (void)
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{
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uchar tmp[64]; /* long enough for environment variables */
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char tmp[64]; /* long enough for environment variables */
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int i = getenv_r ("baudrate", tmp, sizeof (tmp));
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gd->baudrate = (i > 0)
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#ifdef CONFIG_PRAM
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int i;
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ulong reg;
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uchar tmp[64]; /* long enough for environment variables */
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char tmp[64]; /* long enough for environment variables */
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#endif
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/* Pointer is writable since we allocated a register for it */
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*/
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{
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ulong pram;
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uchar memsz[32];
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char memsz[32];
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#ifdef CONFIG_PRAM
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char *s;
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