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Merge with /home/wd/git/u-boot/custodian/u-boot-microblaze

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This commit is contained in:
Wolfgang Denk 2007-04-04 02:05:48 +02:00
commit c8f2280162
38 changed files with 2131 additions and 42 deletions
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5
CREDITS
View file

@ -474,3 +474,8 @@ N: Timur Tabi
E: timur@freescale.com
D: Support for MPC8349E-mITX
W: www.freescale.com
N: Michal Simek
E: monstr@monstr.eu
D: Support for Microblaze, ML401, XUPV2P board
W: www.monstr.eu

5
MAINTAINERS
View file

@ -564,6 +564,11 @@ Yasushi Shoji <yashi@atmark-techno.com>
SUZAKU MicroBlaze
Michal Simek <monstr@monstr.eu>
ML401 MicroBlaze
XUPV2P MicroBlaze
#########################################################################
# Coldfire Systems: #
# #

2
MAKEALL
View file

@ -293,7 +293,7 @@ LIST_nios2=" \
#########################################################################
LIST_microblaze=" \
suzaku
suzaku ml401 xupv2p
"
#########################################################################

11
Makefile
View file

@ -2358,6 +2358,16 @@ suzaku_config: unconfig
@echo "#define CONFIG_SUZAKU 1" >> $(obj)include/config.h
@$(MKCONFIG) -a $(@:_config=) microblaze microblaze suzaku AtmarkTechno
ml401_config: unconfig
@ >include/config.h
@echo "#define CONFIG_ML401 1" >> include/config.h
@./mkconfig -a $(@:_config=) microblaze microblaze ml401 xilinx
xupv2p_config: unconfig
@ >include/config.h
@echo "#define CONFIG_XUPV2P 1" >> include/config.h
@./mkconfig -a $(@:_config=) microblaze microblaze xupv2p xilinx
#########################################################################
## Blackfin
#########################################################################
@ -2440,3 +2450,4 @@ backup:
gtar --force-local -zcvf `date "+$$F-%Y-%m-%d-%T.tar.gz"` $$F
#########################################################################

2
board/AtmarkTechno/suzaku/suzaku.c
View file

@ -24,7 +24,7 @@
/* This is a board specific file. It's OK to include board specific
* header files */
#include <asm/suzaku.h>
#include <config.h>
void do_reset(void)
{

3
board/AtmarkTechno/suzaku/u-boot.lds
View file

@ -61,6 +61,7 @@ SECTIONS
{
__bss_start = .;
*(.bss)
__bss_start = .;
__bss_end = .;
}
__end = . ;
}

65
board/xilinx/ml401/Makefile Normal file
View file

@ -0,0 +1,65 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
$(shell mkdir -p $(obj)../xilinx_enet)
endif
INCS := -I../common -I../xilinx_enet
CFLAGS += $(INCS)
HOST_CFLAGS += $(INCS)
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o \
../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \
../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \
../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \
../xilinx_enet/xemac_intr_dma.o ../common/xipif_v1_23_b.o \
../common/xbasic_types.o ../common/xdma_channel.o \
../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \
../common/xversion.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

32
board/xilinx/ml401/config.mk Normal file
View file

@ -0,0 +1,32 @@
#
# (C) Copyright 2007 Michal Simek
#
# Michal SIMEK <monstr@monstr.eu>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 6.3 EDK_Gmm.12.3
#
TEXT_BASE = 0x12000000
PLATFORM_CPPFLAGS += -mno-xl-soft-mul
PLATFORM_CPPFLAGS += -mno-xl-soft-div
PLATFORM_CPPFLAGS += -mxl-barrel-shift

49
board/xilinx/ml401/ml401.c Normal file
View file

@ -0,0 +1,49 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* This is a board specific file. It's OK to include board specific
* header files */
#include <common.h>
#include <config.h>
void do_reset (void)
{
#ifdef CFG_GPIO_0
*((unsigned long *)(CFG_GPIO_0_ADDR)) =
++(*((unsigned long *)(CFG_GPIO_0_ADDR)));
#endif
#ifdef CFG_RESET_ADDRESS
puts ("Reseting board\n");
asm ("bra r0");
#endif
}
int gpio_init (void)
{
#ifdef CFG_GPIO_0
*((unsigned long *)(CFG_GPIO_0_ADDR)) = 0x0;
#endif
return 0;
}

46
include/asm-microblaze/suzaku.h → board/xilinx/ml401/u-boot.lds
View file

@ -22,6 +22,46 @@
* MA 02111-1307 USA
*/
/* System Register (GPIO) */
#define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000
#define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0)
OUTPUT_ARCH(microblaze)
ENTRY(_start)
SECTIONS
{
.text ALIGN(0x4):
{
__text_start = .;
cpu/microblaze/start.o (.text)
*(.text)
__text_end = .;
}
.rodata ALIGN(0x4):
{
__rodata_start = .;
*(.rodata)
__rodata_end = .;
}
.data ALIGN(0x4):
{
__data_start = .;
*(.data)
__data_end = .;
}
.u_boot_cmd ALIGN(0x4):
{
. = .;
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
.bss ALIGN(0x4):
{
__bss_start = .;
*(.bss)
__bss_end = .;
}
__end = . ;
}

67
board/xilinx/ml401/xparameters.h Normal file
View file

@ -0,0 +1,67 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 6.3 EDK_Gmm.12.3
*/
/* System Clock Frequency */
#define XILINX_CLOCK_FREQ 66666667
/* Interrupt controller is intc_0 */
#define XILINX_INTC_BASEADDR 0xd1000fc0
#define XILINX_INTC_NUM_INTR_INPUTS 12
/* Timer pheriphery is opb_timer_0 */
#define XILINX_TIMER_BASEADDR 0xa2000000
#define XILINX_TIMER_IRQ 0
/* Uart pheriphery is console_uart */
#define XILINX_UART_BASEADDR 0xa0000000
#define XILINX_UART_BAUDRATE 115200
/* GPIO is opb_gpio_0*/
#define XILINX_GPIO_BASEADDR 0x90000000
/* Flash Memory is opb_emc_0 */
#define XILINX_FLASH_START 0x28000000
#define XILINX_FLASH_SIZE 0x00800000
/* Main Memory is plb_ddr_0 */
#define XILINX_RAM_START 0x10000000
#define XILINX_RAM_SIZE 0x10000000
/* Sysace Controller is opb_sysace_0 */
#define XILINX_SYSACE_BASEADDR 0xCF000000
#define XILINX_SYSACE_HIGHADDR 0xCF0001FF
#define XILINX_SYSACE_MEM_WIDTH 16
/* Ethernet controller is opb_ethernet_0 */
#define XPAR_XEMAC_NUM_INSTANCES 1
#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
#define XPAR_OPB_ETHERNET_0_MII_EXIST 1

4
board/xilinx/xilinx_enet/emac_adapter.c
View file

@ -147,7 +147,11 @@ eth_rx(void)
RecvFrameLength = PKTSIZE;
Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength);
if (Result == XST_SUCCESS) {
#ifndef CONFIG_EMACLITE
NetReceive((uchar *)etherrxbuff, RecvFrameLength);
#else
NetReceive(etherrxbuff, RecvFrameLength);
#endif
return (1);
} else {
return (0);

65
board/xilinx/xupv2p/Makefile Normal file
View file

@ -0,0 +1,65 @@
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
ifneq ($(OBJTREE),$(SRCTREE))
$(shell mkdir -p $(obj)../common)
$(shell mkdir -p $(obj)../xilinx_enet)
endif
INCS := -I../common -I../xilinx_enet
CFLAGS += $(INCS)
HOST_CFLAGS += $(INCS)
LIB = $(obj)lib$(BOARD).a
COBJS = $(BOARD).o \
../xilinx_enet/emac_adapter.o ../xilinx_enet/xemac.o \
../xilinx_enet/xemac_options.o ../xilinx_enet/xemac_polled.o \
../xilinx_enet/xemac_intr.o ../xilinx_enet/xemac_g.o \
../xilinx_enet/xemac_intr_dma.o ../common/xipif_v1_23_b.o \
../common/xbasic_types.o ../common/xdma_channel.o \
../common/xdma_channel_sg.o ../common/xpacket_fifo_v1_00_b.o \
../common/xversion.o \
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

32
board/xilinx/xupv2p/config.mk Normal file
View file

@ -0,0 +1,32 @@
#
# (C) Copyright 2007 Michal Simek
#
# Michal SIMEK <monstr@monstr.eu>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# CAUTION: This file is automatically generated by libgen.
# Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
#
TEXT_BASE = 0x38000000
PLATFORM_CPPFLAGS += -mno-xl-soft-mul
PLATFORM_CPPFLAGS += -mno-xl-soft-div
PLATFORM_CPPFLAGS += -mxl-barrel-shift

67
board/xilinx/xupv2p/u-boot.lds Normal file
View file

@ -0,0 +1,67 @@
/*
* (C) Copyright 2004 Atmark Techno, Inc.
*
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(microblaze)
ENTRY(_start)
SECTIONS
{
.text ALIGN(0x4):
{
__text_start = .;
cpu/microblaze/start.o (.text)
*(.text)
__text_end = .;
}
.rodata ALIGN(0x4):
{
__rodata_start = .;
*(.rodata)
__rodata_end = .;
}
.data ALIGN(0x4):
{
__data_start = .;
*(.data)
__data_end = .;
}
.u_boot_cmd ALIGN(0x4):
{
. = .;
__u_boot_cmd_start = .;
*(.u_boot_cmd)
__u_boot_cmd_end = .;
}
.bss ALIGN(0x4):
{
__bss_start = .;
*(.bss)
__bss_end = .;
}
__end = . ;
}

64
board/xilinx/xupv2p/xparameters.h Normal file
View file

@ -0,0 +1,64 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 8.2.02 EDK_Im_Sp2.4
*/
/* System Clock Frequency */
#define XILINX_CLOCK_FREQ 100000000
/* Interrupt controller is opb_intc_0 */
#define XILINX_INTC_BASEADDR 0x41200000
#define XILINX_INTC_NUM_INTR_INPUTS 11
/* Timer pheriphery is opb_timer_1 */
#define XILINX_TIMER_BASEADDR 0x41c00000
#define XILINX_TIMER_IRQ 1
/* Uart pheriphery is RS232_Uart_1 */
#define XILINX_UART_BASEADDR 0x40600000
#define XILINX_UART_BAUDRATE 115200
/* GPIO is LEDs_4Bit*/
#define XILINX_GPIO_BASEADDR 0x40000000
/* FLASH doesn't exist none */
/* Main Memory is DDR_256MB_32MX64_rank1_row13_col10_cl2_5 */
#define XILINX_RAM_START 0x30000000
#define XILINX_RAM_SIZE 0x10000000
/* Sysace Controller is SysACE_CompactFlash */
#define XILINX_SYSACE_BASEADDR 0x41800000
#define XILINX_SYSACE_HIGHADDR 0x4180ffff
#define XILINX_SYSACE_MEM_WIDTH 16
/* Ethernet controller is Ethernet_MAC */
#define XPAR_XEMAC_NUM_INSTANCES 1
#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
#define XPAR_OPB_ETHERNET_0_BASEADDR 0x40c00000
#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x40c0ffff
#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
#define XPAR_OPB_ETHERNET_0_MII_EXIST 1

49
board/xilinx/xupv2p/xupv2p.c Normal file
View file

@ -0,0 +1,49 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* This is a board specific file. It's OK to include board specific
* header files */
#include <common.h>
#include <config.h>
void do_reset (void)
{
#ifdef CFG_GPIO_0
*((unsigned long *)(CFG_GPIO_0_ADDR)) =
++(*((unsigned long *)(CFG_GPIO_0_ADDR)));
#endif
#ifdef CFG_RESET_ADDRESS
puts ("Reseting board\n");
asm ("bra r0");
#endif
}
int gpio_init (void)
{
#ifdef CFG_GPIO_0
*((unsigned long *)(CFG_GPIO_0_ADDR)) = 0x0;
#endif
return 0;
}

26
common/cmd_bdinfo.c
View file

@ -180,6 +180,32 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 0;
}
#elif defined(CONFIG_MICROBLAZE) /* ! PPC, which leaves Microblaze */
int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
int i;
bd_t *bd = gd->bd;
print_num ("mem start ", (ulong)bd->bi_memstart);
print_num ("mem size ", (ulong)bd->bi_memsize);
print_num ("flash start ", (ulong)bd->bi_flashstart);
print_num ("flash size ", (ulong)bd->bi_flashsize);
print_num ("flash offset ", (ulong)bd->bi_flashoffset);
#if defined(CFG_SRAM_BASE)
print_num ("sram start ", (ulong)bd->bi_sramstart);
print_num ("sram size ", (ulong)bd->bi_sramsize);
#endif
#if defined(CFG_CMD_NET)
puts ("ethaddr =");
for (i=0; i<6; ++i) {
printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]);
}
puts ("\nip_addr = ");
print_IPaddr (bd->bi_ip_addr);
#endif
printf ("\nbaudrate = %d bps\n", (ulong)bd->bi_baudrate);
return 0;
}
#else /* ! PPC, which leaves MIPS */

3
cpu/microblaze/Makefile
View file

@ -26,7 +26,8 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(CPU).a
START = start.o
COBJS = cpu.o interrupts.o
SOBJS = dcache.o icache.o irq.o disable_int.o enable_int.o
COBJS = cpu.o interrupts.o cache.o exception.o timer.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

48
cpu/microblaze/cache.c Normal file
View file

@ -0,0 +1,48 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <moonstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if (CONFIG_COMMANDS & CFG_CMD_CACHE)
int dcache_status (void)
{
int i = 0;
int mask = 0x80;
__asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
/* i&=0x80 */
__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
return i;
}
int icache_status (void)
{
int i = 0;
int mask = 0x20;
__asm__ __volatile__ ("mfs %0,rmsr"::"r" (i):"memory");
/* i&=0x20 */
__asm__ __volatile__ ("and %0,%0,%1"::"r" (i), "r" (mask):"memory");
return i;
}
#endif

68
cpu/microblaze/dcache.S Normal file
View file

@ -0,0 +1,68 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
.text
.globl dcache_enable
.ent dcache_enable
.align 2
dcache_enable:
/* Make space on stack for a temporary */
addi r1, r1, -4
/* Save register r12 */
swi r12, r1, 0
/* Read the MSR register */
mfs r12, rmsr
/* Set the instruction enable bit */
ori r12, r12, 0x80
/* Save the MSR register */
mts rmsr, r12
/* Load register r12 */
lwi r12, r1, 0
/* Return */
rtsd r15, 8
/* Update stack in the delay slot */
addi r1, r1, 4
.end dcache_enable
.text
.globl dcache_disable
.ent dcache_disable
.align 2
dcache_disable:
/* Make space on stack for a temporary */
addi r1, r1, -4
/* Save register r12 */
swi r12, r1, 0
/* Read the MSR register */
mfs r12, rmsr
/* Clear the data cache enable bit */
andi r12, r12, ~0x80
/* Save the MSR register */
mts rmsr, r12
/* Load register r12 */
lwi r12, r1, 0
/* Return */
rtsd r15, 8
/* Update stack in the delay slot */
addi r1, r1, 4
.end dcache_disable

46
cpu/microblaze/disable_int.S Normal file
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@ -0,0 +1,46 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
.text
.globl microblaze_disable_interrupts
.ent microblaze_disable_interrupts
.align 2
microblaze_disable_interrupts:
#Make space on stack for a temporary
addi r1, r1, -4
#Save register r12
swi r12, r1, 0
#Read the MSR register
mfs r12, rmsr
#Clear the interrupt enable bit
andi r12, r12, ~2
#Save the MSR register
mts rmsr, r12
#Load register r12
lwi r12, r1, 0
#Return
rtsd r15, 8
#Update stack in the delay slot
addi r1, r1, 4
.end microblaze_disable_interrupts

25
include/asm-microblaze/platform.h → cpu/microblaze/enable_int.S
View file

@ -1,7 +1,7 @@
/*
* (C) Copyright 2004 Atmark Techno, Inc.
* (C) Copyright 2007 Michal Simek
*
* Yasushi SHOJI <yashi@atmark-techno.com>
* Michal SIMEK <monstrmonstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
@ -13,7 +13,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -22,8 +22,17 @@
* MA 02111-1307 USA
*/
#include <config.h>
#ifdef CONFIG_SUZAKU
#include <asm/suzaku.h>
#endif
.text
.globl microblaze_enable_interrupts
.ent microblaze_enable_interrupts
.align 2
microblaze_enable_interrupts:
addi r1, r1, -4
swi r12, r1, 0
mfs r12, rmsr
ori r12, r12, 2
mts rmsr, r12
lwi r12, r1, 0
rtsd r15, 8
addi r1, r1, 4
.end microblaze_enable_interrupts

68
cpu/microblaze/exception.c Normal file
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@ -0,0 +1,68 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
void _hw_exception_handler (void)
{
int address = 0;
int state = 0;
/* loading address of exception EAR */
__asm__ __volatile ("mfs %0,rear"::"r" (address):"memory");
/* loading excetpion state register ESR */
__asm__ __volatile ("mfs %0,resr"::"r" (state):"memory");
printf ("Hardware exception at 0x%x address\n", address);
switch (state & 0x1f) { /* mask on exception cause */
case 0x1:
puts ("Unaligned data access exception\n");
break;
case 0x2:
puts ("Illegal op-code exception\n");
break;
case 0x3:
puts ("Instruction bus error exception\n");
break;
case 0x4:
puts ("Data bus error exception\n");
break;
case 0x5:
puts ("Divide by zero exception\n");
break;
default:
puts ("Undefined cause\n");
break;
}
printf ("Unaligned %sword access\n", ((state & 0x800) ? "" : "half"));
printf ("Unaligned %s access\n", ((state & 0x400) ? "store" : "load"));
printf ("Register R%x\n", (state & 0x3E) >> 5);
hang ();
}
#ifdef CFG_USR_EXCEP
void _exception_handler (void)
{
puts ("User vector_exception\n");
hang ();
}
#endif

69
cpu/microblaze/icache.S Normal file
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@ -0,0 +1,69 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
.text
.globl icache_enable
.ent icache_enable
.align 2
icache_enable:
/* Make space on stack for a temporary */
addi r1, r1, -4
/* Save register r12 */
swi r12, r1, 0
/* Read the MSR register */
mfs r12, rmsr
/* Set the instruction enable bit */
ori r12, r12, 0x20
/* Save the MSR register */
mts rmsr, r12
/* Load register r12 */
lwi r12, r1, 0
/* Return */
rtsd r15, 8
/* Update stack in the delay slot */
addi r1, r1, 4
.end icache_enable
.text
.globl icache_disable
.ent icache_disable
.align 2
icache_disable:
/* Make space on stack for a temporary */
addi r1, r1, -4
/* Save register r12 */
swi r12, r1, 0
/* Read the MSR register */
mfs r12, rmsr
/* Clear the instruction enable bit */
andi r12, r12, ~0x20
/* Save the MSR register */
mts rmsr, r12
/* Load register r12 */
lwi r12, r1, 0
/* Return */
rtsd r15, 8
/* Update stack in the delay slot */
addi r1, r1, 4
.end icache_disable

182
cpu/microblaze/interrupts.c
View file

@ -1,6 +1,8 @@
/*
* (C) Copyright 2007 Michal Simek
* (C) Copyright 2004 Atmark Techno, Inc.
*
* Michal SIMEK <monstr@monstr.eu>
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
@ -13,7 +15,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -22,11 +24,185 @@
* MA 02111-1307 USA
*/
void enable_interrupts(void)
#include <common.h>
#include <command.h>
#include <asm/microblaze_intc.h>
#undef DEBUG_INT
extern void microblaze_disable_interrupts (void);
extern void microblaze_enable_interrupts (void);
void enable_interrupts (void)
{
microblaze_enable_interrupts ();
}
int disable_interrupts(void)
int disable_interrupts (void)
{
microblaze_disable_interrupts ();
return 0;
}
#ifdef CFG_INTC_0
#ifdef CFG_TIMER_0
extern void timer_init (void);
#endif
static struct irq_action vecs[CFG_INTC_0_NUM];
/* mapping structure to interrupt controller */
microblaze_intc_t *intc = (microblaze_intc_t *) (CFG_INTC_0_ADDR);
/* default handler */
void def_hdlr (void)
{
puts ("def_hdlr\n");
}
void enable_one_interrupt (int irq)
{
int mask;
int offset = 1;
offset <<= irq;
mask = intc->ier;
intc->ier = (mask | offset);
#ifdef DEBUG_INT
printf ("Enable one interrupt irq %x - mask %x,ier %x\n", offset, mask,
intc->ier);
printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
intc->iar, intc->mer);
#endif
}
void disable_one_interrupt (int irq)
{
int mask;
int offset = 1;
offset <<= irq;
mask = intc->ier;
intc->ier = (mask & ~offset);
#ifdef DEBUG_INT
printf ("Disable one interrupt irq %x - mask %x,ier %x\n", irq, mask,
intc->ier);
printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
intc->iar, intc->mer);
#endif
}
/* adding new handler for interrupt */
void install_interrupt_handler (int irq, interrupt_handler_t * hdlr, void *arg)
{
struct irq_action *act;
/* irq out of range */
if ((irq < 0) || (irq > CFG_INTC_0_NUM)) {
puts ("IRQ out of range\n");
return;
}
act = &vecs[irq];
if (hdlr) { /* enable */
act->handler = hdlr;
act->arg = arg;
act->count = 0;
enable_one_interrupt (irq);
} else { /* disable */
act->handler = (interrupt_handler_t *) def_hdlr;
act->arg = (void *)irq;
disable_one_interrupt (irq);
}
}
/* initialization interrupt controller - hardware */
void intc_init (void)
{
intc->mer = 0;
intc->ier = 0;
intc->iar = 0xFFFFFFFF;
/* XIntc_Start - hw_interrupt enable and all interrupt enable */
intc->mer = 0x3;
#ifdef DEBUG_INT
printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
intc->iar, intc->mer);
#endif
}
int interrupts_init (void)
{
int i;
/* initialize irq list */
for (i = 0; i < CFG_INTC_0_NUM; i++) {
vecs[i].handler = (interrupt_handler_t *) def_hdlr;
vecs[i].arg = (void *)i;
vecs[i].count = 0;
}
/* initialize intc controller */
intc_init ();
#ifdef CFG_TIMER_0
timer_init ();
#endif
enable_interrupts ();
return 0;
}
void interrupt_handler (void)
{
int irqs;
irqs = (intc->isr & intc->ier); /* find active interrupt */
#ifdef DEBUG_INT
printf ("INTC isr %x, ier %x, iar %x, mer %x\n", intc->isr, intc->ier,
intc->iar, intc->mer);
printf ("Interrupt handler on %x line, r14 %x\n", irqs, value);
#endif
struct irq_action *act = vecs;
while (irqs) {
if (irqs & 1) {
#ifdef DEBUG_INT
printf
("Jumping to interrupt handler rutine addr %x,count %x,arg %x\n",
act->handler, act->count, act->arg);
#endif
act->handler (act->arg);
act->count++;
}
irqs >>= 1;
act++;
}
intc->iar = 0xFFFFFFFF; /* erase all events */
#ifdef DEBUG
printf ("Dump INTC reg, isr %x, ier %x, iar %x, mer %x\n", intc->isr,
intc->ier, intc->iar, intc->mer);
printf ("Interrupt handler on %x line, r14\n", irqs);
#endif
}
#endif
#if (CONFIG_COMMANDS & CFG_CMD_IRQ)
#ifdef CFG_INTC_0
int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
int i;
struct irq_action *act = vecs;
puts ("\nInterrupt-Information:\n\n"
"Nr Routine Arg Count\n"
"-----------------------------\n");
for (i = 0; i < CFG_INTC_0_NUM; i++) {
if (act->handler != (interrupt_handler_t*) def_hdlr) {
printf ("%02d %08lx %08lx %d\n", i,
(int)act->handler, (int)act->arg, act->count);
}
act++;
}
puts ("\n");
return (0);
}
#else
int do_irqinfo (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
puts ("Undefined interrupt controller\n");
}
#endif
#endif /* CONFIG_COMMANDS & CFG_CMD_IRQ */

165
cpu/microblaze/irq.S Normal file
View file

@ -0,0 +1,165 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
.text
.global _interrupt_handler
_interrupt_handler:
addi r1, r1, -4
swi r2, r1, 0
addi r1, r1, -4
swi r3, r1, 0
addi r1, r1, -4
swi r4, r1, 0
addi r1, r1, -4
swi r5, r1, 0
addi r1, r1, -4
swi r6, r1, 0
addi r1, r1, -4
swi r7, r1, 0
addi r1, r1, -4
swi r8, r1, 0
addi r1, r1, -4
swi r9, r1, 0
addi r1, r1, -4
swi r10, r1, 0
addi r1, r1, -4
swi r11, r1, 0
addi r1, r1, -4
swi r12, r1, 0
addi r1, r1, -4
swi r13, r1, 0
addi r1, r1, -4
swi r14, r1, 0
addi r1, r1, -4
swi r15, r1, 0
addi r1, r1, -4
swi r16, r1, 0
addi r1, r1, -4
swi r17, r1, 0
addi r1, r1, -4
swi r18, r1, 0
addi r1, r1, -4
swi r19, r1, 0
addi r1, r1, -4
swi r20, r1, 0
addi r1, r1, -4
swi r21, r1, 0
addi r1, r1, -4
swi r22, r1, 0
addi r1, r1, -4
swi r23, r1, 0
addi r1, r1, -4
swi r24, r1, 0
addi r1, r1, -4
swi r25, r1, 0
addi r1, r1, -4
swi r26, r1, 0
addi r1, r1, -4
swi r27, r1, 0
addi r1, r1, -4
swi r28, r1, 0
addi r1, r1, -4
swi r29, r1, 0
addi r1, r1, -4
swi r30, r1, 0
addi r1, r1, -4
swi r31, r1, 0
brlid r15, interrupt_handler
nop
nop
lwi r31, r1, 0
addi r1, r1, 4
lwi r30, r1, 0
addi r1, r1, 4
lwi r29, r1, 0
addi r1, r1, 4
lwi r28, r1, 0
addi r1, r1, 4
lwi r27, r1, 0
addi r1, r1, 4
lwi r26, r1, 0
addi r1, r1, 4
lwi r25, r1, 0
addi r1, r1, 4
lwi r24, r1, 0
addi r1, r1, 4
lwi r23, r1, 0
addi r1, r1, 4
lwi r22, r1, 0
addi r1, r1, 4
lwi r21, r1, 0
addi r1, r1, 4
lwi r20, r1, 0
addi r1, r1, 4
lwi r19, r1, 0
addi r1, r1, 4
lwi r18, r1, 0
addi r1, r1, 4
lwi r17, r1, 0
addi r1, r1, 4
lwi r16, r1, 0
addi r1, r1, 4
lwi r15, r1, 0
addi r1, r1, 4
lwi r14, r1, 0
addi r1, r1, 4
lwi r13, r1, 0
addi r1, r1, 4
lwi r12, r1, 0
addi r1, r1, 4
lwi r11, r1, 0
addi r1, r1, 4
lwi r10, r1, 0
addi r1, r1, 4
lwi r9, r1, 0
addi r1, r1, 4
lwi r8, r1, 0
addi r1, r1, 4
lwi r7, r1, 0
addi r1, r1, 4
lwi r6, r1, 0
addi r1, r1, 4
lwi r5, r1, 0
addi r1, r1, 4
lwi r4, r1, 0
addi r1, r1, 4
lwi r3, r1, 0
addi r1, r1, 4
lwi r2, r1, 0
addi r1, r1, 4
/* enable_interrupt */
addi r1, r1, -4
swi r12, r1, 0
mfs r12, rmsr
ori r12, r12, 2
mts rmsr, r12
lwi r12, r1, 0
addi r1, r1, 4
nop
bra r14
nop
nop
.size _interrupt_handler,.-_interrupt_handler

91
cpu/microblaze/start.S
View file

@ -1,6 +1,8 @@
/*
* (C) Copyright 2007 Michal Simek
* (C) Copyright 2004 Atmark Techno, Inc.
*
* Michal SIMEK <monstr@monstr.eu>
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
@ -13,7 +15,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -27,10 +29,91 @@
.text
.global _start
_start:
mts rmsr, r0 /* disable cache */
addi r1, r0, CFG_INIT_SP_OFFSET
addi r1, r1, -4 /* Decrement SP to top of memory */
/* add opcode instruction for 32bit jump - 2 instruction imm & brai*/
addi r6, r0, 0xb000 /* hex b000 opcode imm */
bslli r6, r6, 16 /* shift */
swi r6, r0, 0x0 /* reset address */
swi r6, r0, 0x8 /* user vector exception */
swi r6, r0, 0x10 /* interrupt */
swi r6, r0, 0x20 /* hardware exception */
addi r1, r0, CFG_SDRAM_BASE /* init stack pointer */
addi r1, r1, CFG_SDRAM_SIZE /* set sp to high up */
addi r6, r0, 0xb808 /* hew b808 opcode brai*/
bslli r6, r6, 16
swi r6, r0, 0x4 /* reset address */
swi r6, r0, 0xC /* user vector exception */
swi r6, r0, 0x14 /* interrupt */
swi r6, r0, 0x24 /* hardware exception */
#ifdef CFG_RESET_ADDRESS
/* reset address */
addik r6, r0, CFG_RESET_ADDRESS
sw r6, r1, r0
lhu r7, r1, r0
shi r7, r0, 0x2
shi r6, r0, 0x6
/*
* Copy U-Boot code to TEXT_BASE
* solve problem with sbrk_base
*/
#if (CFG_RESET_ADDRESS != TEXT_BASE)
addi r4, r0, __end
addi r5, r0, __text_start
rsub r4, r5, r4 /* size = __end - __text_start */
addi r6, r0, CFG_RESET_ADDRESS /* source address */
addi r7, r0, 0 /* counter */
4:
lw r8, r6, r7
sw r8, r5, r7
addi r7, r7, 0x4
cmp r8, r4, r7
blti r8, 4b
#endif
#endif
#ifdef CFG_USR_EXCEP
/* user_vector_exception */
addik r6, r0, _exception_handler
sw r6, r1, r0
lhu r7, r1, r0
shi r7, r0, 0xa
shi r6, r0, 0xe
#endif
#ifdef CFG_INTC_0
/* interrupt_handler */
addik r6, r0, _interrupt_handler
sw r6, r1, r0
lhu r7, r1, r0
shi r7, r0, 0x12
shi r6, r0, 0x16
#endif
/* hardware exception */
addik r6, r0, _hw_exception_handler
sw r6, r1, r0
lhu r7, r1, r0
shi r7, r0, 0x22
shi r6, r0, 0x26
/* enable instruction and data cache */
mfs r12, rmsr
ori r12, r12, 0xa0
mts rmsr, r12
clear_bss:
/* clear BSS segments */
addi r5, r0, __bss_start
addi r4, r0, __bss_end
cmp r6, r5, r4
beqi r6, 3f
2:
swi r0, r5, 0 /* write zero to loc */
addi r5, r5, 4 /* increment to next loc */
cmp r6, r5, r4 /* check if we have reach the end */
bnei r6, 2b
3: /* jumping to board_init */
brai board_init
1: bri 1b

68
cpu/microblaze/timer.c Normal file
View file

@ -0,0 +1,68 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/microblaze_timer.h>
volatile int timestamp = 0;
void reset_timer (void)
{
timestamp = 0;
}
ulong get_timer (ulong base)
{
return (timestamp - base);
}
void set_timer (ulong t)
{
timestamp = t;
}
#ifdef CFG_INTC_0
#ifdef CFG_TIMER_0
extern void install_interrupt_handler (int irq, interrupt_handler_t * hdlr,
void *arg);
microblaze_timer_t *tmr = (microblaze_timer_t *) (CFG_TIMER_0_ADDR);
void timer_isr (void *arg)
{
timestamp++;
tmr->control = tmr->control | TIMER_INTERRUPT;
}
void timer_init (void)
{
tmr->loadreg = CFG_TIMER_0_PRELOAD;
tmr->control = TIMER_INTERRUPT | TIMER_RESET;
tmr->control =
TIMER_ENABLE | TIMER_ENABLE_INTR | TIMER_RELOAD | TIMER_DOWN_COUNT;
reset_timer ();
install_interrupt_handler (CFG_TIMER_0_IRQ, timer_isr, (void *)tmr);
}
#endif
#endif

41
include/asm-microblaze/microblaze_intc.h Normal file
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@ -0,0 +1,41 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.cz>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
typedef volatile struct microblaze_intc_t {
int isr; /* interrupt status register */
int ipr; /* interrupt pending register */
int ier; /* interrupt enable register */
int iar; /* interrupt acknowledge register */
int sie; /* set interrupt enable bits */
int cie; /* clear interrupt enable bits */
int ivr; /* interrupt vector register */
int mer; /* master enable register */
} microblaze_intc_t;
struct irq_action {
interrupt_handler_t *handler; /* pointer to interrupt rutine */
void *arg;
int count; /* number of interrupt */
};

42
include/asm-microblaze/microblaze_timer.h Normal file
View file

@ -0,0 +1,42 @@
/*
* (C) Copyright 2007 Michal Simek
*
* Michal SIMEK <monstr@monstr.cz>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#define TIMER_ENABLE_ALL 0x400 /* ENALL */
#define TIMER_PWM 0x200 /* PWMA0 */
#define TIMER_INTERRUPT 0x100 /* T0INT */
#define TIMER_ENABLE 0x080 /* ENT0 */
#define TIMER_ENABLE_INTR 0x040 /* ENIT0 */
#define TIMER_RESET 0x020 /* LOAD0 */
#define TIMER_RELOAD 0x010 /* ARHT0 */
#define TIMER_EXT_CAPTURE 0x008 /* CAPT0 */
#define TIMER_EXT_COMPARE 0x004 /* GENT0 */
#define TIMER_DOWN_COUNT 0x002 /* UDT0 */
#define TIMER_CAPTURE_MODE 0x001 /* MDT0 */
typedef volatile struct microblaze_timer_t {
int control; /* control/statuc register TCSR */
int loadreg; /* load register TLR */
int counter; /* timer/counter register */
} microblaze_timer_t;

230
include/configs/ml401.h Normal file
View file

@ -0,0 +1,230 @@
/*
* (C) Copyright 2007 Czech Technical University.
*
* Michal SIMEK <monstr@seznam.cz>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "../board/xilinx/ml401/xparameters.h"
#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
#define CONFIG_ML401 1 /* ML401 Board */
/* uart */
#define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR
#define CONFIG_BAUDRATE XILINX_UART_BAUDRATE
#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
/* setting reset address */
#define CFG_RESET_ADDRESS TEXT_BASE
/* ethernet */
#define CONFIG_EMACLITE 1
#define XPAR_EMAC_0_DEVICE_ID XPAR_XEMAC_NUM_INSTANCES
/* gpio */
#define CFG_GPIO_0 1
#define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR
/* interrupt controller */
#define CFG_INTC_0 1
#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR
#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
/* timer */
#define CFG_TIMER_0 1
#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR
#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
#define FREQUENCE XILINX_CLOCK_FREQ
#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
/*
* memory layout - Example
* TEXT_BASE = 0x1200_0000;
* CFG_SRAM_BASE = 0x1000_0000;
* CFG_SRAM_SIZE = 0x0400_0000;
*
* CFG_GBL_DATA_OFFSET = 0x1000_0000 + 0x0400_0000 - 0x1000 = 0x13FF_F000
* CFG_MONITOR_BASE = 0x13FF_F000 - 0x40000 = 0x13FB_F000
* CFG_MALLOC_BASE = 0x13FB_F000 - 0x40000 = 0x13F7_F000
*
* 0x1000_0000 CFG_SDRAM_BASE
* FREE
* 0x1200_0000 TEXT_BASE
* U-BOOT code
* 0x1202_0000
* FREE
*
* STACK
* 0x13F7_F000 CFG_MALLOC_BASE
* MALLOC_AREA 256kB Alloc
* 0x11FB_F000 CFG_MONITOR_BASE
* MONITOR_CODE 256kB Env
* 0x13FF_F000 CFG_GBL_DATA_OFFSET
* GLOBAL_DATA 4kB bd, gd
* 0x1400_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
*/
/* ddr sdram - main memory */
#define CFG_SDRAM_BASE XILINX_RAM_START
#define CFG_SDRAM_SIZE XILINX_RAM_SIZE
#define CFG_MEMTEST_START CFG_SDRAM_BASE
#define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x1000)
/* global pointer */
#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
/* monitor code */
#define SIZE 0x40000
#define CFG_MONITOR_LEN SIZE
#define CFG_MONITOR_BASE (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
#define CFG_MONITOR_END (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_MALLOC_LEN SIZE
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
/* stack */
#define CFG_INIT_SP_OFFSET CFG_MONITOR_BASE
/*#define RAMENV */
#define FLASH
#ifdef FLASH
#define CFG_FLASH_BASE XILINX_FLASH_START
#define CFG_FLASH_SIZE XILINX_FLASH_SIZE
#define CFG_FLASH_CFI 1
#define CFG_FLASH_CFI_DRIVER 1
#define CFG_FLASH_EMPTY_INFO 1 /* ?empty sector */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
#ifdef RAMENV
#define CFG_ENV_IS_NOWHERE 1
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
#else /* !RAMENV */
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_ADDR 0x40000
#define CFG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
#define CFG_ENV_SIZE 0x2000
#endif /* !RAMBOOT */
#else /* !FLASH */
/* ENV in RAM */
#define CFG_NO_FLASH 1
#define CFG_ENV_IS_NOWHERE 1
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
#endif /* !FLASH */
#ifdef FLASH
#ifdef RAMENV
#define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
CFG_CMD_MEMORY |\
CFG_CMD_MISC |\
CFG_CMD_AUTOSCRIPT |\
CFG_CMD_IRQ |\
CFG_CMD_ASKENV |\
CFG_CMD_BDI |\
CFG_CMD_RUN |\
CFG_CMD_LOADS |\
CFG_CMD_LOADB |\
CFG_CMD_IMI |\
CFG_CMD_NET |\
CFG_CMD_CACHE |\
CFG_CMD_IMLS |\
CFG_CMD_FLASH |\
CFG_CMD_PING \
)
#else /* !RAMENV */
#define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
CFG_CMD_MEMORY |\
CFG_CMD_MISC |\
CFG_CMD_AUTOSCRIPT |\
CFG_CMD_IRQ |\
CFG_CMD_ASKENV |\
CFG_CMD_BDI |\
CFG_CMD_RUN |\
CFG_CMD_LOADS |\
CFG_CMD_LOADB |\
CFG_CMD_IMI |\
CFG_CMD_NET |\
CFG_CMD_CACHE |\
CFG_CMD_IMLS |\
CFG_CMD_FLASH |\
CFG_CMD_PING |\
CFG_CMD_ENV |\
CFG_CMD_SAVES \
)
#endif
#else /* !FLASH */
#define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
CFG_CMD_MEMORY |\
CFG_CMD_MISC |\
CFG_CMD_AUTOSCRIPT |\
CFG_CMD_IRQ |\
CFG_CMD_ASKENV |\
CFG_CMD_BDI |\
CFG_CMD_RUN |\
CFG_CMD_LOADS |\
CFG_CMD_LOADB |\
CFG_CMD_IMI |\
CFG_CMD_NET |\
CFG_CMD_CACHE |\
CFG_CMD_PING \
)
#endif /* !FLASH */
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/* Miscellaneous configurable options */
#define CFG_PROMPT "U-Boot-mONStR> "
#define CFG_CBSIZE 512 /* size of console buffer */
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
#define CFG_MAXARGS 15 /* max number of command args */
#define CFG_LONGHELP
#define CFG_LOAD_ADDR 0x12000000 /* default load address */
#define CONFIG_BOOTDELAY 30
#define CONFIG_BOOTARGS "root=romfs"
#define CONFIG_HOSTNAME "ml401"
#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
#define CONFIG_IPADDR 192.168.0.3
#define CONFIG_SERVERIP 192.168.0.5
#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
/* architecture dependent code */
#define CFG_USR_EXCEP /* user exception */
#define CFG_HZ 1000
/* system ace */
/*#define CONFIG_SYSTEMACE
#define DEBUG_SYSTEMACE
#define CFG_SYSTEMACE_BASE XILINX_SYSACE_BASEADDR
#define CFG_SYSTEMACE_WIDTH XILINX_SYSACE_MEM_WIDTH
#define CONFIG_DOS_PARTITION
*/
#endif /* __CONFIG_H */

7
include/configs/suzaku.h
View file

@ -44,12 +44,17 @@
#define CFG_FLASH_SIZE 0x00400000
#define CFG_RESET_ADDRESS 0xfff00100
#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
#define CFG_MONITOR_BASE (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - (1024 * 1024))
#define CFG_MONITOR_BASE (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - (1024 * 1024))
#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - (1024 * 1024))
#define CONFIG_BAUDRATE 115200
#define CFG_BAUDRATE_TABLE { 115200 }
/* System Register (GPIO) */
#define MICROBLAZE_SYSREG_BASE_ADDR 0xFFFFA000
#define MICROBLAZE_SYSREG_RECONFIGURE (1 << 0)
#define CONFIG_COMMANDS (CONFIG__CMD_DFL)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */

174
include/configs/xupv2p.h Normal file
View file

@ -0,0 +1,174 @@
/*
* (C) Copyright 2007 Czech Technical University.
*
* Michal SIMEK <monstr@monstr.eu>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#include "../board/xilinx/xupv2p/xparameters.h"
#define CONFIG_MICROBLAZE 1 /* MicroBlaze CPU */
#define CONFIG_XUPV2P 1
/* uart */
#define CONFIG_SERIAL_BASE XILINX_UART_BASEADDR
#define CONFIG_BAUDRATE XILINX_UART_BAUDRATE
#define CFG_BAUDRATE_TABLE { CONFIG_BAUDRATE }
/* ethernet */
#define CONFIG_EMAC 1
#define XPAR_EMAC_0_DEVICE_ID XPAR_XEMAC_NUM_INSTANCES
/*
* setting reset address
*
* TEXT_BASE is set to place, where the U-BOOT run in RAM, but
* if you want to store U-BOOT in flash, set CFG_RESET_ADDRESS
* to FLASH memory and after loading bitstream jump to FLASH.
* U-BOOT auto-relocate to TEXT_BASE. After RESET command Microblaze
* jump to CFG_RESET_ADDRESS where is the original U-BOOT code.
*/
#define CFG_RESET_ADDRESS 0x36000000
/* gpio */
#define CFG_GPIO_0 1
#define CFG_GPIO_0_ADDR XILINX_GPIO_BASEADDR
/* interrupt controller */
#define CFG_INTC_0 1
#define CFG_INTC_0_ADDR XILINX_INTC_BASEADDR
#define CFG_INTC_0_NUM XILINX_INTC_NUM_INTR_INPUTS
/* timer */
#define CFG_TIMER_0 1
#define CFG_TIMER_0_ADDR XILINX_TIMER_BASEADDR
#define CFG_TIMER_0_IRQ XILINX_TIMER_IRQ
#define FREQUENCE XILINX_CLOCK_FREQ
#define CFG_TIMER_0_PRELOAD ( FREQUENCE/1000 )
/*
* memory layout - Example
* TEXT_BASE = 0x3600_0000;
* CFG_SRAM_BASE = 0x3000_0000;
* CFG_SRAM_SIZE = 0x1000_0000;
*
* CFG_GBL_DATA_OFFSET = 0x3000_0000 + 0x1000_0000 - 0x1000 = 0x3FFF_F000
* CFG_MONITOR_BASE = 0x3FFF_F000 - 0x40000 = 0x3FFB_F000
* CFG_MALLOC_BASE = 0x3FFB_F000 - 0x40000 = 0x3FF7_F000
*
* 0x3000_0000 CFG_SDRAM_BASE
* FREE
* 0x3600_0000 TEXT_BASE
* U-BOOT code
* 0x3602_0000
* FREE
*
* STACK
* 0x3FF7_F000 CFG_MALLOC_BASE
* MALLOC_AREA 256kB Alloc
* 0x3FFB_F000 CFG_MONITOR_BASE
* MONITOR_CODE 256kB Env
* 0x3FFF_F000 CFG_GBL_DATA_OFFSET
* GLOBAL_DATA 4kB bd, gd
* 0x4000_0000 CFG_SDRAM_BASE + CFG_SDRAM_SIZE
*/
/* ddr sdram - main memory */
#define CFG_SDRAM_BASE XILINX_RAM_START
#define CFG_SDRAM_SIZE XILINX_RAM_SIZE
#define CFG_MEMTEST_START CFG_SDRAM_BASE
#define CFG_MEMTEST_END (CFG_SDRAM_BASE + 0x1000)
/* global pointer */
#define CFG_GBL_DATA_SIZE 0x1000 /* size of global data */
#define CFG_GBL_DATA_OFFSET (CFG_SDRAM_BASE + CFG_SDRAM_SIZE - CFG_GBL_DATA_SIZE) /* start of global data */
/* monitor code */
#define SIZE 0x40000
#define CFG_MONITOR_LEN SIZE
#define CFG_MONITOR_BASE (CFG_GBL_DATA_OFFSET - CFG_MONITOR_LEN)
#define CFG_MONITOR_END (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
#define CFG_MALLOC_LEN SIZE
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
/* stack */
#define CFG_INIT_SP_OFFSET CFG_MALLOC_BASE
#define CFG_NO_FLASH 1
#define CFG_ENV_IS_NOWHERE 1
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SIZE)
#define CONFIG_COMMANDS (CONFIG__CMD_DFL |\
CFG_CMD_MEMORY |\
CFG_CMD_IRQ |\
CFG_CMD_BDI |\
CFG_CMD_NET |\
CFG_CMD_IMI |\
CFG_CMD_ECHO |\
CFG_CMD_CACHE |\
CFG_CMD_RUN |\
CFG_CMD_AUTOSCRIPT |\
CFG_CMD_ASKENV |\
CFG_CMD_LOADS |\
CFG_CMD_LOADB |\
CFG_CMD_MISC |\
CFG_CMD_PING \
)
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/* Miscellaneous configurable options */
#define CFG_PROMPT "U-Boot-mONStR> "
#define CFG_CBSIZE 512 /* size of console buffer */
#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* print buffer size */
#define CFG_MAXARGS 15 /* max number of command args */
#define CFG_LONGHELP
#define CFG_LOAD_ADDR 0x12000000 /* default load address */
#define CONFIG_BOOTDELAY 30
#define CONFIG_BOOTARGS "root=romfs"
#define CONFIG_HOSTNAME "ml401"
#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm"
#define CONFIG_IPADDR 192.168.0.3
#define CONFIG_SERVERIP 192.168.0.5
#define CONFIG_GATEWAYIP 192.168.0.1
#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
/* architecture dependent code */
#define CFG_USR_EXCEP /* user exception */
#define CFG_HZ 1000
#define CONFIG_PREBOOT "echo U-BOOT by mONStR;" \
"base 0;" \
"echo"
/* system ace */
/*#define CONFIG_SYSTEMACE
#define DEBUG_SYSTEMACE
#define CFG_SYSTEMACE_BASE 0xCF000000
#define CFG_SYSTEMACE_WIDTH 16
#define CONFIG_DOS_PARTITION*/
#endif /* __CONFIG_H */

95
lib_microblaze/board.c
View file

@ -1,6 +1,8 @@
/*
* (C) Copyright 2007 Michal Simek
* (C) Copyright 2004 Atmark Techno, Inc.
*
* Michal SIMEK <monstr@monstr.eu>
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
@ -13,7 +15,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -30,8 +32,18 @@
DECLARE_GLOBAL_DATA_PTR;
const char version_string[] =
U_BOOT_VERSION" (" __DATE__ " - " __TIME__ ")";
const char version_string[] = U_BOOT_VERSION " (" __DATE__ " - " __TIME__ ")";
#ifdef CFG_GPIO_0
extern int gpio_init (void);
#endif
#ifdef CFG_INTC_0
extern int interrupts_init (void);
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NET)
extern int eth_init (bd_t * bis);
extern int getenv_IPaddr (char *);
#endif
/*
* Begin and End of memory area for malloc(), and current "brk"
@ -40,6 +52,18 @@ static ulong mem_malloc_start;
static ulong mem_malloc_end;
static ulong mem_malloc_brk;
/*
* The Malloc area is immediately below the monitor copy in DRAM
* aka CFG_MONITOR_BASE - Note there is no need for reloc_off
* as our monitory code is run from SDRAM
*/
static void mem_malloc_init (void)
{
mem_malloc_end = (CFG_MALLOC_BASE + CFG_MALLOC_LEN);
mem_malloc_start = CFG_MALLOC_BASE;
mem_malloc_brk = mem_malloc_start;
memset ((void *)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start);
}
void *sbrk (ptrdiff_t increment)
{
@ -50,7 +74,7 @@ void *sbrk (ptrdiff_t increment)
return (NULL);
}
mem_malloc_brk = new;
return ((void *) old);
return ((void *)old);
}
/*
@ -68,24 +92,36 @@ void *sbrk (ptrdiff_t increment)
typedef int (init_fnc_t) (void);
init_fnc_t *init_sequence[] = {
serial_init, /* serial communications setup */
env_init,
serial_init,
#ifdef CFG_GPIO_0
gpio_init,
#endif
#ifdef CFG_INTC_0
interrupts_init,
#endif
NULL,
};
void board_init(void)
void board_init (void)
{
bd_t *bd;
init_fnc_t **init_fnc_ptr;
/* Pointer is writable since we allocated a register for it. */
gd = (gd_t *)CFG_GBL_DATA_OFFSET;
memset((void *)gd, 0, CFG_GBL_DATA_SIZE);
gd->bd = (bd_t *)(gd+1); /* At end of global data */
gd = (gd_t *) CFG_GBL_DATA_OFFSET;
#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
ulong flash_size = 0;
#endif
asm ("nop"); /* FIXME gd is not initialize - wait */
memset ((void *)gd, 0, CFG_GBL_DATA_SIZE);
gd->bd = (bd_t *) (gd + 1); /* At end of global data */
gd->baudrate = CONFIG_BAUDRATE;
bd = gd->bd;
bd->bi_baudrate = CONFIG_BAUDRATE;
bd->bi_memstart = CFG_SDRAM_BASE;
bd->bi_memsize = CFG_SDRAM_SIZE;
/* Initialise malloc() area */
mem_malloc_init ();
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
WATCHDOG_RESET ();
@ -94,6 +130,37 @@ void board_init(void)
}
}
#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
bd->bi_flashstart = CFG_FLASH_BASE;
if (0 < (flash_size = flash_init ())) {
bd->bi_flashsize = flash_size;
bd->bi_flashoffset = CFG_FLASH_BASE + flash_size;
} else {
puts ("Flash init FAILED");
bd->bi_flashstart = 0;
bd->bi_flashsize = 0;
bd->bi_flashoffset = 0;
}
#endif
#if (CONFIG_COMMANDS & CFG_CMD_NET)
char *s, *e;
int i;
/* board MAC address */
s = getenv ("ethaddr");
for (i = 0; i < 6; ++i) {
bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
if (s)
s = (*e) ? e + 1 : e;
}
/* IP Address */
bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
eth_init (bd);
#endif
/* relocate environment function pointers etc. */
env_relocate ();
/* main_loop */
for (;;) {
WATCHDOG_RESET ();
@ -104,5 +171,5 @@ void board_init(void)
void hang (void)
{
puts ("### ERROR ### Please RESET the board ###\n");
for (;;);
for (;;) ;
}

146
lib_microblaze/microblaze_linux.c
View file

@ -1,6 +1,8 @@
/*
* (C) Copyright 2007 Michal Simek
* (C) Copyright 2004 Atmark Techno, Inc.
*
* Michal SIMEK <monstr@monstr.eu>
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
@ -13,7 +15,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
@ -24,8 +26,146 @@
#include <common.h>
#include <command.h>
#include <image.h>
#include <zlib.h>
#include <asm/byteorder.h>
void do_bootm_linux(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[],
ulong addr, ulong *len_ptr, int verify)
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_SHOW_BOOT_PROGRESS
# include <status_led.h>
# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
#else
# define SHOW_BOOT_PROGRESS(arg)
#endif
extern image_header_t header; /* from cmd_bootm.c */
/*cmd_boot.c*/
extern int do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]);
void do_bootm_linux (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[],
ulong addr, ulong * len_ptr, int verify)
{
ulong len = 0, checksum;
ulong initrd_start, initrd_end;
ulong data;
/* First parameter is mapped to $r5 for kernel boot args */
void (*theKernel) (char *);
image_header_t *hdr = &header;
char *commandline = getenv ("bootargs");
int i;
theKernel = (void (*)(char *))ntohl (hdr->ih_ep);
/* Check if there is an initrd image */
if (argc >= 3) {
SHOW_BOOT_PROGRESS (9);
addr = simple_strtoul (argv[2], NULL, 16);
printf ("## Loading Ramdisk Image at %08lx ...\n", addr);
/* Copy header so we can blank CRC field for re-calculation */
memcpy (&header, (char *)addr, sizeof (image_header_t));
if (ntohl (hdr->ih_magic) != IH_MAGIC) {
printf ("Bad Magic Number\n");
SHOW_BOOT_PROGRESS (-10);
do_reset (cmdtp, flag, argc, argv);
}
data = (ulong) & header;
len = sizeof (image_header_t);
checksum = ntohl (hdr->ih_hcrc);
hdr->ih_hcrc = 0;
if (crc32 (0, (char *)data, len) != checksum) {
printf ("Bad Header Checksum\n");
SHOW_BOOT_PROGRESS (-11);
do_reset (cmdtp, flag, argc, argv);
}
SHOW_BOOT_PROGRESS (10);
print_image_hdr (hdr);
data = addr + sizeof (image_header_t);
len = ntohl (hdr->ih_size);
if (verify) {
ulong csum = 0;
printf (" Verifying Checksum ... ");
csum = crc32 (0, (char *)data, len);
if (csum != ntohl (hdr->ih_dcrc)) {
printf ("Bad Data CRC\n");
SHOW_BOOT_PROGRESS (-12);
do_reset (cmdtp, flag, argc, argv);
}
printf ("OK\n");
}
SHOW_BOOT_PROGRESS (11);
if ((hdr->ih_os != IH_OS_LINUX) ||
(hdr->ih_arch != IH_CPU_MICROBLAZE) ||
(hdr->ih_type != IH_TYPE_RAMDISK)) {
printf ("No Linux Microblaze Ramdisk Image\n");
SHOW_BOOT_PROGRESS (-13);
do_reset (cmdtp, flag, argc, argv);
}
/*
* Now check if we have a multifile image
*/
} else if ((hdr->ih_type == IH_TYPE_MULTI) && (len_ptr[1])) {
ulong tail = ntohl (len_ptr[0]) % 4;
SHOW_BOOT_PROGRESS (13);
/* skip kernel length and terminator */
data = (ulong) (&len_ptr[2]);
/* skip any additional image length fields */
for (i = 1; len_ptr[i]; ++i)
data += 4;
/* add kernel length, and align */
data += ntohl (len_ptr[0]);
if (tail) {
data += 4 - tail;
}
len = ntohl (len_ptr[1]);
} else {
/*
* no initrd image
*/
SHOW_BOOT_PROGRESS (14);
data = 0;
}
#ifdef DEBUG
if (!data) {
printf ("No initrd\n");
}
#endif
if (data) {
initrd_start = data;
initrd_end = initrd_start + len;
} else {
initrd_start = 0;
initrd_end = 0;
}
SHOW_BOOT_PROGRESS (15);
#ifdef DEBUG
printf ("## Transferring control to Linux (at address %08lx) ...\n",
(ulong) theKernel);
#endif
theKernel (commandline);
}

9
lib_microblaze/time.c
View file

@ -1,6 +1,8 @@
/*
* (C) Copyright 2007 Michal Simek
* (C) Copyright 2004 Atmark Techno, Inc.
*
* Michal SIMEK <monstr@monstr.eu>
* Yasushi SHOJI <yashi@atmark-techno.com>
*
* See file CREDITS for list of people who contributed to this
@ -22,6 +24,11 @@
* MA 02111-1307 USA
*/
void udelay(unsigned long usec)
#include <common.h>
void udelay (unsigned long usec)
{
int i;
i = get_timer (0);
while ((get_timer (0) - i) < (usec / 1000)) ;
}

2
microblaze_config.mk
View file

@ -22,7 +22,7 @@
# MA 02111-1307 USA
#
PLATFORM_CPPFLAGS += -ffixed-r31
PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__
ifdef CONFIG_MICROBLAZE_HARD_MULT
PLATFORM_CPPFLAGS += -mno-xl-soft-mul