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https://github.com/AsahiLinux/u-boot
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armv8: ls1088aqds: Add support of I2C driver model.
Udate ls1088aqds board init code to support DM_I2C. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This commit is contained in:
Chuanhua Han
Prabhakar Kushwaha
parent
96d3fb4146
commit
c8b2e364b6
2 changed files with 101 additions and 46 deletions
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@ -81,11 +81,16 @@ struct ls1088a_qds_mdio {
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struct mii_dev *realbus;
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};
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struct reg_pair {
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uint addr;
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u8 *val;
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};
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static void sgmii_configure_repeater(int dpmac)
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{
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struct mii_dev *bus;
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uint8_t a = 0xf;
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int i, j, ret;
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int i, j, k, ret;
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unsigned short value;
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const char *dev = "LS1088A_QDS_MDIO2";
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int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
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@ -97,8 +102,28 @@ static void sgmii_configure_repeater(int dpmac)
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uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
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uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
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u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
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struct reg_pair reg_pair[10] = {
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{6, ®_val[0]}, {4, ®_val[1]},
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{8, ®_val[2]}, {0xf, NULL},
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{0x11, NULL}, {0x16, NULL},
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{0x18, NULL}, {0x23, ®_val[3]},
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{0x2d, ®_val[4]}, {4, ®_val[5]},
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};
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#ifdef CONFIG_DM_I2C
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struct udevice *udev;
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#endif
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/* Set I2c to Slot 1 */
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i2c_write(0x77, 0, 0, &a, 1);
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(0x77, 0, 0, &a, 1);
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#else
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ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
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if (!ret)
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ret = dm_i2c_write(udev, 0, &a, 1);
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#endif
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if (ret)
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goto error;
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switch (dpmac) {
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case 1:
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@ -144,31 +169,34 @@ static void sgmii_configure_repeater(int dpmac)
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return;
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}
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#ifdef CONFIG_DM_I2C
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i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
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#endif
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for (i = 0; i < 4; i++) {
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for (j = 0; j < 4; j++) {
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a = 0x18;
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i2c_write(i2c_phy_addr, 6, 1, &a, 1);
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a = 0x38;
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i2c_write(i2c_phy_addr, 4, 1, &a, 1);
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a = 0x4;
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i2c_write(i2c_phy_addr, 8, 1, &a, 1);
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reg_pair[3].val = &ch_a_eq[i];
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reg_pair[4].val = &ch_a_ctl2[j];
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reg_pair[5].val = &ch_b_eq[i];
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reg_pair[6].val = &ch_b_ctl2[j];
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for (k = 0; k < 10; k++) {
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(i2c_phy_addr,
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reg_pair[k].addr,
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1, reg_pair[k].val, 1);
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#else
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ret = i2c_get_chip_for_busnum(0,
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i2c_phy_addr,
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1, &udev);
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if (!ret)
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ret = dm_i2c_write(udev,
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reg_pair[k].addr,
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reg_pair[k].val, 1);
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#endif
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if (ret)
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goto error;
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}
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i2c_write(i2c_phy_addr, 0xf, 1,
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&ch_a_eq[i], 1);
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i2c_write(i2c_phy_addr, 0x11, 1,
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&ch_a_ctl2[j], 1);
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i2c_write(i2c_phy_addr, 0x16, 1,
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&ch_b_eq[i], 1);
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i2c_write(i2c_phy_addr, 0x18, 1,
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&ch_b_ctl2[j], 1);
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a = 0x14;
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i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
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a = 0xb5;
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i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
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a = 0x20;
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i2c_write(i2c_phy_addr, 4, 1, &a, 1);
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mdelay(100);
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ret = miiphy_read(dev, phy_addr, 0x11, &value);
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if (ret > 0)
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@ -203,7 +231,7 @@ error:
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static void qsgmii_configure_repeater(int dpmac)
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{
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uint8_t a = 0xf;
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int i, j;
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int i, j, k;
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int i2c_phy_addr = 0;
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int phy_addr = 0;
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int i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b};
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@ -213,12 +241,32 @@ static void qsgmii_configure_repeater(int dpmac)
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uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
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uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
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u8 reg_val[6] = {0x18, 0x38, 0x4, 0x14, 0xb5, 0x20};
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struct reg_pair reg_pair[10] = {
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{6, ®_val[0]}, {4, ®_val[1]},
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{8, ®_val[2]}, {0xf, NULL},
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{0x11, NULL}, {0x16, NULL},
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{0x18, NULL}, {0x23, ®_val[3]},
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{0x2d, ®_val[4]}, {4, ®_val[5]},
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};
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const char *dev = mdio_names[EMI1_SLOT1];
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int ret = 0;
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unsigned short value;
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#ifdef CONFIG_DM_I2C
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struct udevice *udev;
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#endif
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/* Set I2c to Slot 1 */
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i2c_write(0x77, 0, 0, &a, 1);
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(0x77, 0, 0, &a, 1);
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#else
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ret = i2c_get_chip_for_busnum(0, 0x77, 1, &udev);
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if (!ret)
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ret = dm_i2c_write(udev, 0, &a, 1);
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#endif
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if (ret)
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goto error;
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switch (dpmac) {
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case 7:
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@ -252,28 +300,35 @@ static void qsgmii_configure_repeater(int dpmac)
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return;
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}
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#ifdef CONFIG_DM_I2C
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i2c_get_chip_for_busnum(0, i2c_phy_addr, 1, &udev);
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#endif
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for (i = 0; i < 4; i++) {
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for (j = 0; j < 4; j++) {
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a = 0x18;
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i2c_write(i2c_phy_addr, 6, 1, &a, 1);
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a = 0x38;
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i2c_write(i2c_phy_addr, 4, 1, &a, 1);
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a = 0x4;
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i2c_write(i2c_phy_addr, 8, 1, &a, 1);
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reg_pair[3].val = &ch_a_eq[i];
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reg_pair[4].val = &ch_a_ctl2[j];
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reg_pair[5].val = &ch_b_eq[i];
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reg_pair[6].val = &ch_b_ctl2[j];
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i2c_write(i2c_phy_addr, 0xf, 1, &ch_a_eq[i], 1);
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i2c_write(i2c_phy_addr, 0x11, 1, &ch_a_ctl2[j], 1);
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for (k = 0; k < 10; k++) {
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#ifndef CONFIG_DM_I2C
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ret = i2c_write(i2c_phy_addr,
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reg_pair[k].addr,
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1, reg_pair[k].val, 1);
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#else
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ret = i2c_get_chip_for_busnum(0,
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i2c_addr[dpmac],
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1, &udev);
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if (!ret)
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ret = dm_i2c_write(udev,
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reg_pair[k].addr,
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reg_pair[k].val, 1);
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#endif
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if (ret)
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goto error;
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}
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i2c_write(i2c_phy_addr, 0x16, 1, &ch_b_eq[i], 1);
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i2c_write(i2c_phy_addr, 0x18, 1, &ch_b_ctl2[j], 1);
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a = 0x14;
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i2c_write(i2c_phy_addr, 0x23, 1, &a, 1);
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a = 0xb5;
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i2c_write(i2c_phy_addr, 0x2d, 1, &a, 1);
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a = 0x20;
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i2c_write(i2c_phy_addr, 4, 1, &a, 1);
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mdelay(100);
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ret = miiphy_read(dev, phy_addr, 0x11, &value);
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if (ret > 0)
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goto error;
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@ -46,7 +46,9 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_DDR_CLK_FREQ 100000000
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#else
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#define CONFIG_QIXIS_I2C_ACCESS
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#ifndef CONFIG_DM_I2C
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#define CONFIG_SYS_I2C_EARLY_INIT
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#endif
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#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
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#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
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#endif
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@ -357,9 +359,7 @@ unsigned long get_board_ddr_clk(void);
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* RTC configuration
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*/
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#define RTC
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#define CONFIG_RTC_PCF8563 1
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
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#define CONFIG_CMD_DATE
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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