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powerpc/boot: Change the macro of Boot from SRIO and PCIE master module

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Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable
the master module of Boot from SRIO and PCIE on a platform. But this
is not a silicon feature, it's just a specific booting mode based on
the SRIO and PCIE interfaces. So it's inappropriate to put the macro
into the file arch/powerpc/include/asm/config_mpc85xx.h.

Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to
"CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from
arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros
in configuration header file of each board which can support the
master module of Boot from SRIO and PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
This commit is contained in:
Liu Gang 2013-05-07 16:30:46 +08:00 committed by Andy Fleming
parent 5a516748a8
commit c8b281524b
9 changed files with 13 additions and 13 deletions
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3
README
View file

@ -3975,6 +3975,9 @@ Low Level (hardware related) configuration options:
- CONFIG_SRIO2: - CONFIG_SRIO2:
Board has SRIO 2 port available Board has SRIO 2 port available
- CONFIG_SRIO_PCIE_BOOT_MASTER
Board can support master function for Boot from SRIO and PCIE
- CONFIG_SYS_SRIOn_MEM_VIRT: - CONFIG_SYS_SRIOn_MEM_VIRT:
Virtual Address of SRIO port 'n' memory region Virtual Address of SRIO port 'n' memory region

2
arch/powerpc/cpu/mpc85xx/cpu_init.c
View file

@ -564,7 +564,7 @@ skip_l2:
#ifdef CONFIG_SYS_SRIO #ifdef CONFIG_SYS_SRIO
srio_init(); srio_init();
#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
char *s = getenv("bootmaster"); char *s = getenv("bootmaster");
if (s) { if (s) {
if (!strcmp(s, "SRIO1")) { if (!strcmp(s, "SRIO1")) {

4
arch/powerpc/cpu/mpc8xxx/srio.c
View file

@ -24,7 +24,7 @@
#include <asm/fsl_srio.h> #include <asm/fsl_srio.h>
#include <asm/errno.h> #include <asm/errno.h>
#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
#define SRIO_PORT_ACCEPT_ALL 0x10000001 #define SRIO_PORT_ACCEPT_ALL 0x10000001
#define SRIO_IB_ATMU_AR 0x80f55000 #define SRIO_IB_ATMU_AR 0x80f55000
#define SRIO_OB_ATMU_AR_MAINT 0x80077000 #define SRIO_OB_ATMU_AR_MAINT 0x80077000
@ -299,7 +299,7 @@ void srio_init(void)
} }
} }
#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
void srio_boot_master(int port) void srio_boot_master(int port)
{ {
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;

4
arch/powerpc/include/asm/config_mpc85xx.h
View file

@ -337,7 +337,6 @@
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@ -371,7 +370,6 @@
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@ -413,7 +411,6 @@
#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 #define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999 #define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
@ -449,7 +446,6 @@
#define CONFIG_SYS_FSL_ERRATUM_USB14 #define CONFIG_SYS_FSL_ERRATUM_USB14
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003
#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5

6
drivers/pci/fsl_pci_init.c
View file

@ -211,7 +211,7 @@ static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
return 1; return 1;
} }
#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
static void fsl_pcie_boot_master(pit_t *pi) static void fsl_pcie_boot_master(pit_t *pi)
{ {
/* configure inbound window for slave's u-boot image */ /* configure inbound window for slave's u-boot image */
@ -388,7 +388,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
/* see if we are a PCIe or PCI controller */ /* see if we are a PCIe or PCI controller */
pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap); pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
/* boot from PCIE --master */ /* boot from PCIE --master */
char *s = getenv("bootmaster"); char *s = getenv("bootmaster");
char pcie[6]; char pcie[6];
@ -624,7 +624,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
if (fsl_is_pci_agent(hose)) { if (fsl_is_pci_agent(hose)) {
fsl_pci_config_unlock(hose); fsl_pci_config_unlock(hose);
hose->last_busno = hose->first_busno; hose->last_busno = hose->first_busno;
#ifdef CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
} else { } else {
/* boot from PCIE --master releases slave's core 0 */ /* boot from PCIE --master releases slave's core 0 */
char *s = getenv("bootmaster"); char *s = getenv("bootmaster");

1
include/configs/P2041RDB.h
View file

@ -77,6 +77,7 @@
#define CONFIG_SYS_SRIO #define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */ #define CONFIG_SRIO2 /* SRIO port 2 */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_SYS_DPAA_RMAN /* RMan */ #define CONFIG_SYS_DPAA_RMAN /* RMan */
#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_FSL_LAW /* Use common FSL init code */

2
include/configs/P3041DS.h
View file

@ -40,7 +40,7 @@
#define CONFIG_SYS_SRIO #define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */ #define CONFIG_SRIO2 /* SRIO port 2 */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#include "corenet_ds.h" #include "corenet_ds.h"

2
include/configs/P4080DS.h
View file

@ -36,7 +36,7 @@
#define CONFIG_SYS_SRIO #define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */ #define CONFIG_SRIO2 /* SRIO port 2 */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */
#include "corenet_ds.h" #include "corenet_ds.h"

2
include/configs/P5020DS.h
View file

@ -41,7 +41,7 @@
#define CONFIG_SYS_SRIO #define CONFIG_SYS_SRIO
#define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO1 /* SRIO port 1 */
#define CONFIG_SRIO2 /* SRIO port 2 */ #define CONFIG_SRIO2 /* SRIO port 2 */
#define CONFIG_SRIO_PCIE_BOOT_MASTER
#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
#include "corenet_ds.h" #include "corenet_ds.h"