mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-01 08:59:33 +00:00
Add a common get_ram_size() function and modify the the
board-specific files to invoke that common implementation.
This commit is contained in:
parent
b299e41a0d
commit
c83bf6a2d0
54 changed files with 1848 additions and 3374 deletions
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@ -1,3 +1,10 @@
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======================================================================
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Changes since U-Boot 1.0.1:
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======================================================================
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* Add a common get_ram_size() function and modify the the
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board-specific files to invoke that common implementation.
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======================================================================
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======================================================================
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Changes for U-Boot 1.0.1:
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Changes for U-Boot 1.0.1:
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======================================================================
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======================================================================
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@ -53,8 +53,7 @@ static long int dram_size (long int, long int *, long int);
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#define _NOT_USED_ 0xFFFFFFFF
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#define _NOT_USED_ 0xFFFFFFFF
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const uint init_sdram_table[] =
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const uint init_sdram_table[] = {
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{
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/*
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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*/
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@ -90,8 +89,7 @@ const uint init_sdram_table[] =
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0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
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0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
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};
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};
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const uint sdram_table[] =
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const uint sdram_table[] = {
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{
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/*
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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*/
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@ -147,8 +145,7 @@ const uint sdram_table[] =
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/*
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/*
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* Very early board init code (fpga boot, etc.)
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* Very early board init code (fpga boot, etc.)
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*/
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*/
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int
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int board_pre_init (void)
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board_pre_init (void)
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{
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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@ -170,8 +167,7 @@ board_pre_init (void)
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* Return 1 if no second DRAM bank, otherwise returns 0
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* Return 1 if no second DRAM bank, otherwise returns 0
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*/
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*/
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int
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int checkboard (void)
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checkboard (void)
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{
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{
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unsigned char *s = getenv ("serial#");
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unsigned char *s = getenv ("serial#");
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@ -183,8 +179,7 @@ checkboard (void)
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/* ------------------------------------------------------------------------- */
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/* ------------------------------------------------------------------------- */
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long int
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long int initdram (int board_type)
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initdram (int board_type)
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{
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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@ -258,8 +253,7 @@ initdram (int board_type)
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* try 8 column mode
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* try 8 column mode
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*/
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*/
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size8 = dram_size (CFG_MAMR_8COL,
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size8 = dram_size (CFG_MAMR_8COL,
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(ulong *) SDRAM_BASE1_PRELIM,
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(ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
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SDRAM_MAX_SIZE);
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udelay (1000);
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udelay (1000);
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@ -267,16 +261,13 @@ initdram (int board_type)
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* try 9 column mode
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* try 9 column mode
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*/
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*/
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size9 = dram_size (CFG_MAMR_9COL,
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size9 = dram_size (CFG_MAMR_9COL,
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(ulong *) SDRAM_BASE1_PRELIM,
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(ulong *) SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
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SDRAM_MAX_SIZE);
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if ( size8 < size9 ) /* leave configuration at 9 columns */
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if (size8 < size9) { /* leave configuration at 9 columns */
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{
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size_b0 = size9;
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size_b0 = size9;
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/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
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/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
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}
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} else { /* back to 8 columns */
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else /* back to 8 columns */
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{
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size_b0 = size8;
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size_b0 = size8;
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memctl->memc_mamr = CFG_MAMR_8COL;
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memctl->memc_mamr = CFG_MAMR_8COL;
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udelay (500);
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udelay (500);
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@ -289,8 +280,7 @@ initdram (int board_type)
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* Adjust refresh rate depending on SDRAM type, both banks
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* Adjust refresh rate depending on SDRAM type, both banks
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* For types > 128 MBit leave it at the current (fast) rate
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* For types > 128 MBit leave it at the current (fast) rate
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*/
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*/
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if ( size_b0 < 0x02000000 )
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if (size_b0 < 0x02000000) {
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{
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/* reduce to 15.6 us (62.4 us / quad) */
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/* reduce to 15.6 us (62.4 us / quad) */
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memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
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memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
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udelay (1000);
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udelay (1000);
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@ -327,54 +317,14 @@ initdram (int board_type)
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*/
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*/
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static long int
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static long int
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dram_size (long int mamr_value,
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dram_size (long int mamr_value, long int *base, long int maxsize)
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long int *base,
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long int maxsize)
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{
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile long int *addr;
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ulong cnt, val;
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ulong save[32]; /* to make test non-destructive */
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unsigned char i = 0;
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memctl->memc_mamr = mamr_value;
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memctl->memc_mamr = mamr_value;
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for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1)
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return (get_ram_size (base, maxsize));
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{
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addr = base + cnt; /* pointer arith! */
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save[i++] = *addr;
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*addr = ~cnt;
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}
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/* write 0 to base address */
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addr = base;
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save[i] = *addr;
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*addr = 0;
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/* check at base address */
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if ( (val = *addr) != 0 )
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{
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*addr = save[i];
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return (0);
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}
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for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1)
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{
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addr = base + cnt; /* pointer arith! */
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val = *addr;
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*addr = save[--i];
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if ( val != (~cnt) )
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{
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return (cnt * sizeof(long));
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}
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}
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return (maxsize);
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}
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}
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/* ------------------------------------------------------------------------- */
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/* ------------------------------------------------------------------------- */
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@ -384,8 +334,7 @@ dram_size (long int mamr_value,
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#define CFG_LBKs (CFG_PA2 | CFG_PA1)
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#define CFG_LBKs (CFG_PA2 | CFG_PA1)
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void
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void reset_phy (void)
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reset_phy (void)
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{
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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@ -220,42 +220,10 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
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{
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile long int *addr;
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ulong cnt, val;
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ulong save[32]; /* to make test non-destructive */
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unsigned char i = 0;
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memctl->memc_mamr = mamr_value;
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memctl->memc_mamr = mamr_value;
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for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
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return (get_ram_size(base, maxsize));
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addr = base + cnt; /* pointer arith! */
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save[i++] = *addr;
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*addr = ~cnt;
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}
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/* write 0 to base address */
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addr = base;
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save[i] = *addr;
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*addr = 0;
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/* check at base address */
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if ((val = *addr) != 0) {
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*addr = save[i];
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return (0);
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}
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for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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val = *addr;
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*addr = save[--i];
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if (val != (~cnt)) {
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return (cnt * sizeof (long));
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}
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}
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return (maxsize);
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}
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}
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/*-----------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------
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* aschex_to_byte --
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* aschex_to_byte --
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@ -40,8 +40,7 @@ static long int dram_size (long int, long int *, long int);
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#define _NOT_USED_ 0xFFFFCC25
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#define _NOT_USED_ 0xFFFFCC25
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const uint sdram_table[] =
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const uint sdram_table[] = {
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{
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/*
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/*
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* Single Read. (Offset 00h in UPMA RAM)
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* Single Read. (Offset 00h in UPMA RAM)
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*/
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*/
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@ -109,7 +108,8 @@ long int initdram (int board_type)
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size10;
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long int size10;
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upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/* Refresh clock prescalar */
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/* Refresh clock prescalar */
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memctl->memc_mptpr = CFG_MPTPR;
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memctl->memc_mptpr = CFG_MPTPR;
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* try 10 column mode
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* try 10 column mode
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*/
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*/
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size10 = dram_size (CFG_MAMR_10COL, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE) ;
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size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE_PRELIM,
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SDRAM_MAX_SIZE);
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return (size10);
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return (size10);
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}
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}
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* - short between data lines
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* - short between data lines
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*/
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*/
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static long int dram_size (long int mamr_value, long int *base, long int maxsize)
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static long int dram_size (long int mamr_value, long int *base,
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long int maxsize)
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{
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile long int *addr;
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ulong cnt, val;
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ulong save[32]; /* to make test non-destructive */
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unsigned char i = 0;
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memctl->memc_mamr = mamr_value;
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memctl->memc_mamr = mamr_value;
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for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
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return (get_ram_size (base, maxsize));
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addr = base + cnt; /* pointer arith! */
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save[i++] = *addr;
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*addr = ~cnt;
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}
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/* write 0 to base address */
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addr = base;
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save[i] = *addr;
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*addr = 0;
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/* check at base address */
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if ((val = *addr) != 0) {
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*addr = save[i];
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return (0);
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}
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for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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val = *addr;
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*addr = save[--i];
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if (val != (~cnt)) {
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return (cnt * sizeof(long));
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}
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}
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return (maxsize);
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}
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}
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@ -229,53 +229,8 @@ static long int dram_size (long int mamr_value, long int *base,
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{
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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volatile long int *addr;
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ulong cnt, val, size;
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ulong save[32]; /* to make test non-destructive */
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unsigned char i = 0;
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memctl->memc_mamr = mamr_value;
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memctl->memc_mamr = mamr_value;
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for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
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return (get_ram_size(base, maxsize));
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addr = base + cnt; /* pointer arith! */
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save[i++] = *addr;
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*addr = ~cnt;
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}
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/* write 0 to base address */
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addr = base;
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save[i] = *addr;
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*addr = 0;
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/* check at base address */
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if ((val = *addr) != 0) {
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/* Restore the original data before leaving the function.
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*/
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*addr = save[i];
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for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
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addr = (volatile ulong *) base + cnt;
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*addr = save[--i];
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}
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return (0);
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}
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for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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val = *addr;
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*addr = save[--i];
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if (val != (~cnt)) {
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size = cnt * sizeof (long);
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/* Restore the original data before returning
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*/
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for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
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addr = (volatile ulong *) base + cnt;
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*addr = save[--i];
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}
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return (size);
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}
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}
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return (maxsize);
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}
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}
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@ -40,35 +40,16 @@ int checkboard (void)
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long int initdram (int board_type)
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long int initdram (int board_type)
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{
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{
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int i, cnt;
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long size;
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volatile uchar * base= CFG_SDRAM_BASE;
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long new_bank0_end;
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volatile ulong * addr;
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long mear1;
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ulong save[32];
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long emear1;
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ulong val, ret = 0;
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for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
|
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
|
||||||
addr = (volatile ulong *)base + cnt;
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *)base;
|
new_bank0_end = size - 1;
|
||||||
save[i] = *addr;
|
mear1 = mpc824x_mpc107_getreg(MEAR1);
|
||||||
*addr = 0;
|
emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
||||||
|
|
||||||
if (*addr != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *)base + cnt;
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
ulong new_bank0_end = cnt * sizeof(long) - 1;
|
|
||||||
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
|
|
||||||
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
|
||||||
mear1 = (mear1 & 0xFFFFFF00) |
|
mear1 = (mear1 & 0xFFFFFF00) |
|
||||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
||||||
emear1 = (emear1 & 0xFFFFFF00) |
|
emear1 = (emear1 & 0xFFFFFF00) |
|
||||||
|
@ -76,14 +57,7 @@ long int initdram (int board_type)
|
||||||
mpc824x_mpc107_setreg(MEAR1, mear1);
|
mpc824x_mpc107_setreg(MEAR1, mear1);
|
||||||
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
||||||
|
|
||||||
ret = cnt * sizeof(long);
|
return (size);
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = CFG_MAX_RAM_SIZE;
|
|
||||||
Done:
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -269,13 +269,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
|
||||||
ulong orx, volatile uchar * base)
|
ulong orx, volatile uchar * base)
|
||||||
{
|
{
|
||||||
volatile uchar c = 0xff;
|
volatile uchar c = 0xff;
|
||||||
ulong cnt, val, size;
|
|
||||||
volatile ulong *addr;
|
|
||||||
volatile uint *sdmr_ptr;
|
volatile uint *sdmr_ptr;
|
||||||
volatile uint *orx_ptr;
|
volatile uint *orx_ptr;
|
||||||
|
ulong maxsize, size;
|
||||||
int i;
|
int i;
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
ulong maxsize;
|
|
||||||
|
|
||||||
/* We must be able to test a location outsize the maximum legal size
|
/* We must be able to test a location outsize the maximum legal size
|
||||||
* to find out THAT we are outside; but this address still has to be
|
* to find out THAT we are outside; but this address still has to be
|
||||||
|
@ -325,55 +322,12 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
|
||||||
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
||||||
*base = c;
|
*base = c;
|
||||||
|
|
||||||
/*
|
size = get_ram_size((long *)base, maxsize);
|
||||||
* Check memory range for valid RAM. A simple memory test determines
|
|
||||||
* the actually available RAM size between addresses `base' and
|
|
||||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
|
||||||
* - short between address lines
|
|
||||||
* - short between data lines
|
|
||||||
*/
|
|
||||||
i = 0;
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt; /* pointer arith! */
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *) base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
/* Restore the original data before leaving the function.
|
|
||||||
*/
|
|
||||||
*addr = save[i];
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt;
|
|
||||||
*addr = save[--i];
|
|
||||||
}
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt; /* pointer arith! */
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
size = cnt * sizeof (long);
|
|
||||||
/* Restore the original data before returning
|
|
||||||
*/
|
|
||||||
for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt;
|
|
||||||
*addr = save[--i];
|
|
||||||
}
|
|
||||||
/* Write the actual size to ORx
|
|
||||||
*/
|
|
||||||
*orx_ptr = orx | ~(size - 1);
|
*orx_ptr = orx | ~(size - 1);
|
||||||
|
|
||||||
return (size);
|
return (size);
|
||||||
}
|
}
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
|
||||||
|
|
||||||
int misc_init_r(void)
|
int misc_init_r(void)
|
||||||
{
|
{
|
||||||
|
|
|
@ -227,53 +227,8 @@ static long int dram_size (long int mamr_value, long int *base,
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val, size;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size(base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
/* Restore the original data before leaving the function.
|
|
||||||
*/
|
|
||||||
*addr = save[i];
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt;
|
|
||||||
*addr = save[--i];
|
|
||||||
}
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
size = cnt * sizeof (long);
|
|
||||||
/* Restore the original data before returning
|
|
||||||
*/
|
|
||||||
for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt;
|
|
||||||
*addr = save[--i];
|
|
||||||
}
|
|
||||||
return (size);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -60,36 +60,16 @@ int checkboard(void)
|
||||||
|
|
||||||
long int initdram(int board_type)
|
long int initdram(int board_type)
|
||||||
{
|
{
|
||||||
int i, cnt;
|
long size;
|
||||||
volatile uchar * base = CFG_SDRAM_BASE;
|
long new_bank0_end;
|
||||||
volatile ulong * addr;
|
long mear1;
|
||||||
ulong save[32];
|
long emear1;
|
||||||
ulong val, ret = 0;
|
|
||||||
|
|
||||||
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
|
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
|
||||||
|
|
||||||
addr = (volatile ulong *)base + cnt;
|
new_bank0_end = size - 1;
|
||||||
save[i++] = *addr;
|
mear1 = mpc824x_mpc107_getreg(MEAR1);
|
||||||
*addr = ~cnt;
|
emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *)base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
if (*addr != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *)base + cnt;
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
ulong new_bank0_end = cnt * sizeof(long) - 1;
|
|
||||||
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
|
|
||||||
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
|
||||||
mear1 = (mear1 & 0xFFFFFF00) |
|
mear1 = (mear1 & 0xFFFFFF00) |
|
||||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
||||||
emear1 = (emear1 & 0xFFFFFF00) |
|
emear1 = (emear1 & 0xFFFFFF00) |
|
||||||
|
@ -97,14 +77,7 @@ long int initdram(int board_type)
|
||||||
mpc824x_mpc107_setreg(MEAR1, mear1);
|
mpc824x_mpc107_setreg(MEAR1, mear1);
|
||||||
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
||||||
|
|
||||||
ret = cnt * sizeof(long);
|
return (size);
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = CFG_MAX_RAM_SIZE;
|
|
||||||
Done:
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -213,13 +213,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
|
||||||
ulong orx, volatile uchar * base)
|
ulong orx, volatile uchar * base)
|
||||||
{
|
{
|
||||||
volatile uchar c = 0xff;
|
volatile uchar c = 0xff;
|
||||||
ulong cnt, val;
|
|
||||||
volatile ulong *addr;
|
|
||||||
volatile uint *sdmr_ptr;
|
volatile uint *sdmr_ptr;
|
||||||
volatile uint *orx_ptr;
|
volatile uint *orx_ptr;
|
||||||
|
ulong maxsize, size;
|
||||||
int i;
|
int i;
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
ulong maxsize;
|
|
||||||
|
|
||||||
/* We must be able to test a location outsize the maximum legal size
|
/* We must be able to test a location outsize the maximum legal size
|
||||||
* to find out THAT we are outside; but this address still has to be
|
* to find out THAT we are outside; but this address still has to be
|
||||||
|
@ -269,41 +266,11 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
|
||||||
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
||||||
*base = c;
|
*base = c;
|
||||||
|
|
||||||
/*
|
size = get_ram_size((long *)base, maxsize);
|
||||||
* Check memory range for valid RAM. A simple memory test determines
|
|
||||||
* the actually available RAM size between addresses `base' and
|
|
||||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
|
||||||
* - short between address lines
|
|
||||||
* - short between data lines
|
|
||||||
*/
|
|
||||||
i = 0;
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt; /* pointer arith! */
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *) base;
|
*orx_ptr = orx | ~(size - 1);
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
if ((val = *addr) != 0) {
|
return (size);
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt; /* pointer arith! */
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
/* Write the actual size to ORx
|
|
||||||
*/
|
|
||||||
*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
|
|
||||||
return (cnt * sizeof (long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
long int initdram (int board_type)
|
long int initdram (int board_type)
|
||||||
|
|
|
@ -47,35 +47,16 @@ int checkboard (void)
|
||||||
|
|
||||||
long int initdram(int board_type)
|
long int initdram(int board_type)
|
||||||
{
|
{
|
||||||
int i, cnt;
|
long size;
|
||||||
volatile uchar * base = CFG_SDRAM_BASE;
|
long new_bank0_end;
|
||||||
volatile ulong * addr;
|
long mear1;
|
||||||
ulong save[32];
|
long emear1;
|
||||||
ulong val, ret = 0;
|
|
||||||
|
|
||||||
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
|
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
|
||||||
addr = (volatile ulong *)base + cnt;
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *)base;
|
new_bank0_end = size - 1;
|
||||||
save[i] = *addr;
|
mear1 = mpc824x_mpc107_getreg(MEAR1);
|
||||||
*addr = 0;
|
emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
||||||
|
|
||||||
if (*addr != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *)base + cnt;
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
ulong new_bank0_end = cnt * sizeof(long) - 1;
|
|
||||||
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
|
|
||||||
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
|
||||||
mear1 = (mear1 & 0xFFFFFF00) |
|
mear1 = (mear1 & 0xFFFFFF00) |
|
||||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
||||||
emear1 = (emear1 & 0xFFFFFF00) |
|
emear1 = (emear1 & 0xFFFFFF00) |
|
||||||
|
@ -83,14 +64,7 @@ long int initdram(int board_type)
|
||||||
mpc824x_mpc107_setreg(MEAR1, mear1);
|
mpc824x_mpc107_setreg(MEAR1, mear1);
|
||||||
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
||||||
|
|
||||||
ret = cnt * sizeof(long);
|
return (size);
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = CFG_MAX_RAM_SIZE;
|
|
||||||
Done:
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -30,14 +30,9 @@
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
||||||
static long int dram_size ( long int *base, long int maxsize);
|
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
#define _NOT_USED_ 0xFFFFFFFF
|
#define _NOT_USED_ 0xFFFFFFFF
|
||||||
|
|
||||||
const uint sdram_table[] =
|
const uint sdram_table[] = {
|
||||||
{
|
|
||||||
/*
|
/*
|
||||||
* Single Read. (Offset 0 in UPMA RAM)
|
* Single Read. (Offset 0 in UPMA RAM)
|
||||||
*
|
*
|
||||||
|
@ -120,7 +115,8 @@ long int initdram (int board_type)
|
||||||
|
|
||||||
memctl->memc_mamr = 0x18003112; /*CFG_MAMR_8COL; *//* 0x18005112 TODO: explain here */
|
memctl->memc_mamr = 0x18003112; /*CFG_MAMR_8COL; *//* 0x18005112 TODO: explain here */
|
||||||
|
|
||||||
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
|
upmconfig (UPMA, (uint *) sdram_table,
|
||||||
|
sizeof (sdram_table) / sizeof (uint));
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Map cs 2 and 3 to the SDRAM banks 0 and 1 at
|
* Map cs 2 and 3 to the SDRAM banks 0 and 1 at
|
||||||
|
@ -137,17 +133,12 @@ long int initdram (int board_type)
|
||||||
|
|
||||||
/* perform SDRAM initializsation sequence */
|
/* perform SDRAM initializsation sequence */
|
||||||
memctl->memc_mar = 0x00000088;
|
memctl->memc_mar = 0x00000088;
|
||||||
|
|
||||||
memctl->memc_mcr = 0x80004830; /* SDRAM bank 0 execute 8 refresh */
|
memctl->memc_mcr = 0x80004830; /* SDRAM bank 0 execute 8 refresh */
|
||||||
|
|
||||||
memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
|
memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
|
||||||
|
|
||||||
|
|
||||||
memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */
|
memctl->memc_mcr = 0x80006830; /* SDRAM bank 1 execute 8 refresh */
|
||||||
|
|
||||||
memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
|
memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
|
||||||
|
|
||||||
|
|
||||||
memctl->memc_mamr = CFG_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */
|
memctl->memc_mamr = CFG_MAMR_8COL; /* 0x18803112 start refresh timer TODO: explain here */
|
||||||
|
|
||||||
/* printf ("banks 0 and 1 are programed\n"); */
|
/* printf ("banks 0 and 1 are programed\n"); */
|
||||||
|
@ -156,23 +147,17 @@ long int initdram (int board_type)
|
||||||
* Check Bank 0 Memory Size for re-configuration
|
* Check Bank 0 Memory Size for re-configuration
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
|
size_b0 = get_ram_size ((ulong *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
|
||||||
size_b0 = dram_size ((ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
|
size_b1 = get_ram_size ((ulong *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
|
||||||
|
|
||||||
size_b1 = dram_size ((ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
|
|
||||||
|
|
||||||
|
|
||||||
printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1);
|
printf ("\nbank 0 size %lu\nbank 1 size %lu\n", size_b0, size_b1);
|
||||||
|
|
||||||
|
|
||||||
/* printf ("bank 1 size %u\n",size_b1); */
|
/* printf ("bank 1 size %u\n",size_b1); */
|
||||||
|
|
||||||
if (size_b1 == 0) {
|
if (size_b1 == 0) {
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Adjust refresh rate if bank 0 isn't stuffed
|
* Adjust refresh rate if bank 0 isn't stuffed
|
||||||
*/
|
*/
|
||||||
|
|
||||||
memctl->memc_mptpr = 0x0400; /* divide by 64 */
|
memctl->memc_mptpr = 0x0400; /* divide by 64 */
|
||||||
memctl->memc_br3 &= 0x0FFFFFFFE;
|
memctl->memc_br3 &= 0x0FFFFFFFE;
|
||||||
|
|
||||||
|
@ -180,11 +165,7 @@ long int initdram (int board_type)
|
||||||
* Adjust OR2 for size of bank 0
|
* Adjust OR2 for size of bank 0
|
||||||
*/
|
*/
|
||||||
memctl->memc_or2 |= 7 * size_b0;
|
memctl->memc_or2 |= 7 * size_b0;
|
||||||
|
} else {
|
||||||
}
|
|
||||||
|
|
||||||
else {
|
|
||||||
|
|
||||||
if (size_b0 < size_b1) {
|
if (size_b0 < size_b1) {
|
||||||
memctl->memc_br2 &= 0x00007FFE;
|
memctl->memc_br2 &= 0x00007FFE;
|
||||||
memctl->memc_br3 &= 0x00007FFF;
|
memctl->memc_br3 &= 0x00007FFF;
|
||||||
|
@ -198,15 +179,10 @@ long int initdram (int board_type)
|
||||||
* Adjust OR2 for size of bank 0
|
* Adjust OR2 for size of bank 0
|
||||||
*/
|
*/
|
||||||
memctl->memc_or2 |= 15 * size_b0;
|
memctl->memc_or2 |= 15 * size_b0;
|
||||||
|
|
||||||
memctl->memc_br2 += (size_b1 + 1);
|
memctl->memc_br2 += (size_b1 + 1);
|
||||||
|
} else {
|
||||||
}
|
|
||||||
else {
|
|
||||||
|
|
||||||
memctl->memc_br3 &= 0x00007FFE;
|
memctl->memc_br3 &= 0x00007FFE;
|
||||||
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Adjust OR2 for size of bank 0
|
* Adjust OR2 for size of bank 0
|
||||||
*/
|
*/
|
||||||
|
@ -216,14 +192,10 @@ long int initdram (int board_type)
|
||||||
* Adjust OR3 for size of bank 1
|
* Adjust OR3 for size of bank 1
|
||||||
*/
|
*/
|
||||||
memctl->memc_or3 |= 15 * size_b1;
|
memctl->memc_or3 |= 15 * size_b1;
|
||||||
|
|
||||||
memctl->memc_br3 += (size_b0 + 1);
|
memctl->memc_br3 += (size_b0 + 1);
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
/* before leaving set all unused i/o pins to outputs */
|
/* before leaving set all unused i/o pins to outputs */
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -247,7 +219,6 @@ long int initdram (int board_type)
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
|
|
||||||
|
|
||||||
immap->im_ioport.iop_papar &= ~0x05C3; /* set pins as io */
|
immap->im_ioport.iop_papar &= ~0x05C3; /* set pins as io */
|
||||||
immap->im_ioport.iop_padir |= 0x05C3; /* set pins as output */
|
immap->im_ioport.iop_padir |= 0x05C3; /* set pins as output */
|
||||||
immap->im_ioport.iop_paodr &= 0x0008; /* config pins 9 & 14 as normal outputs */
|
immap->im_ioport.iop_paodr &= 0x0008; /* config pins 9 & 14 as normal outputs */
|
||||||
|
@ -268,49 +239,5 @@ long int initdram (int board_type)
|
||||||
immap->im_ioport.iop_pddir |= 0x07FF; /* set bits 5 - 15 as outputs */
|
immap->im_ioport.iop_pddir |= 0x07FF; /* set bits 5 - 15 as outputs */
|
||||||
immap->im_ioport.iop_pddat = 0x0055; /* set alternating pattern on test port */
|
immap->im_ioport.iop_pddat = 0x0055; /* set alternating pattern on test port */
|
||||||
|
|
||||||
|
|
||||||
return (size_b0 + size_b1);
|
return (size_b0 + size_b1);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Check memory range for valid RAM. A simple memory test determines
|
|
||||||
* the actually available RAM size between addresses `base' and
|
|
||||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
|
||||||
* - short between address lines
|
|
||||||
* - short between data lines
|
|
||||||
*/
|
|
||||||
|
|
||||||
static long int dram_size ( long int *base, long int maxsize)
|
|
||||||
{
|
|
||||||
|
|
||||||
volatile long int *addr;
|
|
||||||
long int cnt, val;
|
|
||||||
|
|
||||||
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; ; cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof(long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* NOTREACHED */
|
|
||||||
}
|
|
||||||
|
|
|
@ -52,50 +52,28 @@ int checkflash (void)
|
||||||
|
|
||||||
long int initdram (int board_type)
|
long int initdram (int board_type)
|
||||||
{
|
{
|
||||||
int i, cnt;
|
long size;
|
||||||
volatile uchar * base= CFG_SDRAM_BASE;
|
#if 0
|
||||||
volatile ulong * addr;
|
long new_bank0_end;
|
||||||
ulong save[32];
|
long mear1;
|
||||||
ulong val, ret = 0;
|
long emear1;
|
||||||
|
#endif
|
||||||
|
|
||||||
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
|
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
|
||||||
addr = (volatile ulong *)base + cnt;
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *)base;
|
#if 0
|
||||||
save[i] = *addr;
|
new_bank0_end = size - 1;
|
||||||
*addr = 0;
|
mear1 = mpc824x_mpc107_getreg(MEAR1);
|
||||||
|
emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
||||||
if (*addr != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *)base + cnt;
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
/* ulong new_bank0_end = cnt * sizeof(long) - 1;
|
|
||||||
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
|
|
||||||
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
|
||||||
mear1 = (mear1 & 0xFFFFFF00) |
|
mear1 = (mear1 & 0xFFFFFF00) |
|
||||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
||||||
emear1 = (emear1 & 0xFFFFFF00) |
|
emear1 = (emear1 & 0xFFFFFF00) |
|
||||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
|
((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
|
||||||
mpc824x_mpc107_setreg(MEAR1, mear1);
|
mpc824x_mpc107_setreg(MEAR1, mear1);
|
||||||
mpc824x_mpc107_setreg(EMEAR1, emear1);*/
|
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
||||||
|
#endif
|
||||||
|
|
||||||
ret = cnt * sizeof(long);
|
return (size);
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = CFG_MAX_RAM_SIZE;
|
|
||||||
Done:
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -320,55 +320,10 @@ static long int dram_size (long int mamr_value, long int *base,
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val, size;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size(base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
/* Restore the original data before leaving the function.
|
|
||||||
*/
|
|
||||||
*addr = save[i];
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt;
|
|
||||||
*addr = save[--i];
|
|
||||||
}
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
size = cnt * sizeof (long);
|
|
||||||
/* Restore the original data before returning
|
|
||||||
*/
|
|
||||||
for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt;
|
|
||||||
*addr = save[--i];
|
|
||||||
}
|
|
||||||
return (size);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
|
@ -186,45 +186,6 @@ static const uint edo_70ns[] =
|
||||||
#error dram not correctly defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
|
#error dram not correctly defined - use CONFIG_DRAM_25MHZ or CONFIG_DRAM_50MHZ
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
|
||||||
static long int dram_size (long int *base, long int maxsize)
|
|
||||||
{
|
|
||||||
volatile long int *addr=base;
|
|
||||||
ulong cnt, val;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof (long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
|
static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
|
||||||
{
|
{
|
||||||
|
@ -306,10 +267,10 @@ static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
|
||||||
/* if no dimm is inserted, noMbytes is still detected as 8m, so
|
/* if no dimm is inserted, noMbytes is still detected as 8m, so
|
||||||
* sanity check top and bottom of memory */
|
* sanity check top and bottom of memory */
|
||||||
|
|
||||||
/* check bytes / 2 because dram_size tests at base+bytes, which
|
/* check bytes / 2 because get_ram_size tests at base+bytes, which
|
||||||
* is not mapped */
|
* is not mapped */
|
||||||
if (noMbytes == 8)
|
if (noMbytes == 8)
|
||||||
if (dram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
|
if (get_ram_size ((long *) base, noMbytes << 19) != noMbytes << 19) {
|
||||||
*((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */
|
*((uint *) BCSR1) |= BCSR1_DRAM_EN; /* disable dram */
|
||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
|
@ -39,8 +39,7 @@ static long int dram_size (long int, long int *, long int);
|
||||||
|
|
||||||
#define _NOT_USED_ 0xFFFFFFFF
|
#define _NOT_USED_ 0xFFFFFFFF
|
||||||
|
|
||||||
const uint sdram_table[] =
|
const uint sdram_table[] = {
|
||||||
{
|
|
||||||
/*
|
/*
|
||||||
* Single Read. (Offset 0 in UPMB RAM)
|
* Single Read. (Offset 0 in UPMB RAM)
|
||||||
*/
|
*/
|
||||||
|
@ -108,9 +107,12 @@ static void PrintState(void)
|
||||||
volatile immap_t *im = (immap_t *) CFG_IMMR;
|
volatile immap_t *im = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &im->im_memctl;
|
volatile memctl8xx_t *memctl = &im->im_memctl;
|
||||||
|
|
||||||
printf("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0, memctl->memc_or0);
|
printf ("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0,
|
||||||
printf("\n1 - SDRAM: B=%08x O=%08x", memctl->memc_br1, memctl->memc_or1);
|
memctl->memc_or0);
|
||||||
printf("\n2 - SDRAM: B=%08x O=%08x", memctl->memc_br2, memctl->memc_or2);
|
printf ("\n1 - SDRAM: B=%08x O=%08x", memctl->memc_br1,
|
||||||
|
memctl->memc_or1);
|
||||||
|
printf ("\n2 - SDRAM: B=%08x O=%08x", memctl->memc_br2,
|
||||||
|
memctl->memc_or2);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -141,7 +143,8 @@ long int initdram (int board_type)
|
||||||
|
|
||||||
memctl->memc_mbmr = CFG_MBMR_8COL;
|
memctl->memc_mbmr = CFG_MBMR_8COL;
|
||||||
|
|
||||||
upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
|
upmconfig (UPMB, (uint *) sdram_table,
|
||||||
|
sizeof (sdram_table) / sizeof (uint));
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Map controller banks 1 and 2 to the SDRAM banks 1 and 2 at
|
* Map controller banks 1 and 2 to the SDRAM banks 1 and 2 at
|
||||||
|
@ -150,10 +153,12 @@ long int initdram (int board_type)
|
||||||
*/
|
*/
|
||||||
|
|
||||||
memctl->memc_or1 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
|
memctl->memc_or1 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
|
||||||
memctl->memc_br1 = ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
|
memctl->memc_br1 =
|
||||||
|
((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
|
||||||
|
|
||||||
memctl->memc_or2 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
|
memctl->memc_or2 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
|
||||||
memctl->memc_br2 = ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
|
memctl->memc_br2 =
|
||||||
|
((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
|
||||||
|
|
||||||
/* perform SDRAM initialization sequence */
|
/* perform SDRAM initialization sequence */
|
||||||
memctl->memc_mar = 0x00000088;
|
memctl->memc_mar = 0x00000088;
|
||||||
|
@ -182,12 +187,15 @@ long int initdram (int board_type)
|
||||||
PrintState ();
|
PrintState ();
|
||||||
#endif
|
#endif
|
||||||
/* printf ("\nChecking bank1..."); */
|
/* printf ("\nChecking bank1..."); */
|
||||||
size8 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
|
size8 = dram_size (CFG_MBMR_8COL, (ulong *) SDRAM_BASE1_PRELIM,
|
||||||
|
SDRAM_MAX_SIZE);
|
||||||
|
|
||||||
size_b0 = size8;
|
size_b0 = size8;
|
||||||
|
|
||||||
/* printf ("\nChecking bank2..."); */
|
/* printf ("\nChecking bank2..."); */
|
||||||
size_b1 = dram_size (memctl->memc_mbmr, (ulong *)SDRAM_BASE2_PRELIM,SDRAM_MAX_SIZE);
|
size_b1 =
|
||||||
|
dram_size (memctl->memc_mbmr, (ulong *) SDRAM_BASE2_PRELIM,
|
||||||
|
SDRAM_MAX_SIZE);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Final mapping: map bigger bank first
|
* Final mapping: map bigger bank first
|
||||||
|
@ -196,17 +204,16 @@ long int initdram (int board_type)
|
||||||
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
|
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
|
||||||
memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
|
memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
|
||||||
|
|
||||||
if (size_b1 > 0)
|
if (size_b1 > 0) {
|
||||||
{
|
|
||||||
/*
|
/*
|
||||||
* Position Bank 1 immediately above Bank 0
|
* Position Bank 1 immediately above Bank 0
|
||||||
*/
|
*/
|
||||||
memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
|
memctl->memc_or2 =
|
||||||
memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) +
|
((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
|
||||||
|
memctl->memc_br2 =
|
||||||
|
((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) +
|
||||||
(size_b0 & BR_BA_MSK);
|
(size_b0 & BR_BA_MSK);
|
||||||
}
|
} else {
|
||||||
else
|
|
||||||
{
|
|
||||||
/*
|
/*
|
||||||
* No bank 1
|
* No bank 1
|
||||||
*
|
*
|
||||||
|
@ -218,8 +225,7 @@ long int initdram (int board_type)
|
||||||
}
|
}
|
||||||
|
|
||||||
/* If no memory detected, disable SDRAM */
|
/* If no memory detected, disable SDRAM */
|
||||||
if ((size_b0 + size_b1) == 0)
|
if ((size_b0 + size_b1) == 0) {
|
||||||
{
|
|
||||||
printf ("disabling SDRAM!\n");
|
printf ("disabling SDRAM!\n");
|
||||||
/* Disable SDRAM - PA7 = 1 */
|
/* Disable SDRAM - PA7 = 1 */
|
||||||
im->im_ioport.iop_padat &= ~CFG_PA7; /* value of PA7 */
|
im->im_ioport.iop_padat &= ~CFG_PA7; /* value of PA7 */
|
||||||
|
@ -243,40 +249,22 @@ long int initdram (int board_type)
|
||||||
* - short between data lines
|
* - short between data lines
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static long int dram_size (long int mbmr_value, long int *base, long int maxsize)
|
static long int dram_size (long int mbmr_value, long int *base,
|
||||||
|
long int maxsize)
|
||||||
{
|
{
|
||||||
volatile long int *addr;
|
long size;
|
||||||
long int cnt, val;
|
|
||||||
|
|
||||||
/*memctl->memc_mbmr = mbmr_value; */
|
/*memctl->memc_mbmr = mbmr_value; */
|
||||||
|
|
||||||
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
|
size = get_ram_size (base, maxsize);
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
*addr = ~cnt;
|
if (size) {
|
||||||
}
|
/* printf("(%08lx)", size); */
|
||||||
|
} else {
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
printf ("(0)");
|
printf ("(0)");
|
||||||
return (0);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
for (cnt = 1; ; cnt <<= 1) {
|
return (size);
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
/* printf("(%08lx)", cnt*sizeof(long)); */
|
|
||||||
return (cnt * sizeof(long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* NOTREACHED */
|
|
||||||
return (0);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
|
#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
|
||||||
|
@ -314,8 +302,7 @@ int pcmcia_init(void)
|
||||||
slota = (pcmp->pcmc_pipr & 0x18000000) == 0;
|
slota = (pcmp->pcmc_pipr & 0x18000000) == 0;
|
||||||
slotb = (pcmp->pcmc_pipr & 0x00001800) == 0;
|
slotb = (pcmp->pcmc_pipr & 0x00001800) == 0;
|
||||||
|
|
||||||
if (!(slota || slotb))
|
if (!(slota || slotb)) {
|
||||||
{
|
|
||||||
printf ("No card present\n");
|
printf ("No card present\n");
|
||||||
#ifdef PCMCIA_SLOT_A
|
#ifdef PCMCIA_SLOT_A
|
||||||
pcmp->pcmc_pgcra = 0;
|
pcmp->pcmc_pgcra = 0;
|
||||||
|
@ -324,14 +311,12 @@ int pcmcia_init(void)
|
||||||
pcmp->pcmc_pgcrb = 0;
|
pcmp->pcmc_pgcrb = 0;
|
||||||
#endif
|
#endif
|
||||||
return -1;
|
return -1;
|
||||||
}
|
} else
|
||||||
else
|
|
||||||
printf ("Unknown card (");
|
printf ("Unknown card (");
|
||||||
|
|
||||||
v = 0;
|
v = 0;
|
||||||
|
|
||||||
switch( (pcmp->pcmc_pipr >> 14) & 3 )
|
switch ((pcmp->pcmc_pipr >> 14) & 3) {
|
||||||
{
|
|
||||||
case 0x00:
|
case 0x00:
|
||||||
printf ("5V");
|
printf ("5V");
|
||||||
v = 5;
|
v = 5;
|
||||||
|
|
|
@ -225,42 +225,10 @@ static long int dram_size (long int mamr_value, long int *base,
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size(base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof (long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
|
@ -26,44 +26,6 @@
|
||||||
#include <pci.h>
|
#include <pci.h>
|
||||||
|
|
||||||
#ifndef CFG_RAMBOOT
|
#ifndef CFG_RAMBOOT
|
||||||
static long int dram_size(long int *base, long int maxsize)
|
|
||||||
{
|
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof (long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void sdram_start (int hi_addr)
|
static void sdram_start (int hi_addr)
|
||||||
{
|
{
|
||||||
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
|
long hi_addr_bit = hi_addr ? 0x01000000 : 0;
|
||||||
|
@ -148,9 +110,9 @@ long int initdram (int board_type)
|
||||||
*(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
|
*(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000;
|
||||||
#endif
|
#endif
|
||||||
sdram_start(0);
|
sdram_start(0);
|
||||||
test1 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
|
test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
|
||||||
sdram_start(1);
|
sdram_start(1);
|
||||||
test2 = dram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
|
test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
|
||||||
if (test1 > test2) {
|
if (test1 > test2) {
|
||||||
sdram_start(0);
|
sdram_start(0);
|
||||||
dramsize = test1;
|
dramsize = test1;
|
||||||
|
@ -163,9 +125,9 @@ long int initdram (int board_type)
|
||||||
#ifdef CONFIG_MPC5200_DDR
|
#ifdef CONFIG_MPC5200_DDR
|
||||||
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
|
*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
|
||||||
sdram_start(0);
|
sdram_start(0);
|
||||||
test1 = dram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
|
test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
|
||||||
sdram_start(1);
|
sdram_start(1);
|
||||||
test2 = dram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
|
test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
|
||||||
if (test1 > test2) {
|
if (test1 > test2) {
|
||||||
sdram_start(0);
|
sdram_start(0);
|
||||||
dramsize2 = test1;
|
dramsize2 = test1;
|
||||||
|
|
|
@ -208,39 +208,8 @@ static long int dram_size (long int mamr_value, long int *base,
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size(base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof (long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -47,52 +47,6 @@ static ulong max_sdram_size(void)
|
||||||
return size;
|
return size;
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
|
||||||
* Check memory range for valid RAM. A simple memory test determines
|
|
||||||
* the actually available RAM size between addresses `base' and
|
|
||||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
|
||||||
* - short between address lines
|
|
||||||
* - short between data lines
|
|
||||||
*/
|
|
||||||
|
|
||||||
static long int dram_size(long int *base, long int maxsize)
|
|
||||||
{
|
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof (long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
|
||||||
|
|
||||||
long int initdram(int board_type)
|
long int initdram(int board_type)
|
||||||
{
|
{
|
||||||
int rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0;
|
int rows, cols, best_val = *INCA_IP_SDRAM_MC_CFGPB0;
|
||||||
|
@ -114,7 +68,7 @@ long int initdram(int board_type)
|
||||||
{
|
{
|
||||||
*INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) |
|
*INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) |
|
||||||
(rows << 4) | cols;
|
(rows << 4) | cols;
|
||||||
size = dram_size((ulong *)CFG_SDRAM_BASE,
|
size = get_ram_size((ulong *)CFG_SDRAM_BASE,
|
||||||
max_sdram_size());
|
max_sdram_size());
|
||||||
|
|
||||||
if (size > max_size)
|
if (size > max_size)
|
||||||
|
|
|
@ -253,42 +253,10 @@ static long int dram_size (long int mamr_value, long int *base,
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size(base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof (long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
|
@ -198,9 +198,8 @@ long int initdram (int board_type)
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8260_t *memctl = &immap->im_memctl;
|
volatile memctl8260_t *memctl = &immap->im_memctl;
|
||||||
volatile uchar *base;
|
volatile uchar *base;
|
||||||
volatile ulong *addr, cnt, val;
|
ulong maxsize;
|
||||||
ulong save[32]; /* to make test non-destructive */
|
int i;
|
||||||
int i, maxsize;
|
|
||||||
|
|
||||||
memctl->memc_psrt = CFG_PSRT;
|
memctl->memc_psrt = CFG_PSRT;
|
||||||
memctl->memc_mptpr = CFG_MPTPR;
|
memctl->memc_mptpr = CFG_MPTPR;
|
||||||
|
@ -237,43 +236,10 @@ long int initdram (int board_type)
|
||||||
*/
|
*/
|
||||||
maxsize = (1 + (~memctl->memc_or1 | 0x7fff)) / 2;
|
maxsize = (1 + (~memctl->memc_or1 | 0x7fff)) / 2;
|
||||||
|
|
||||||
/*
|
maxsize = get_ram_size((long *)base, maxsize);
|
||||||
* Check memory range for valid RAM. A simple memory test determines
|
|
||||||
* the actually available RAM size between addresses `base' and
|
|
||||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
|
||||||
* - short between address lines
|
|
||||||
* - short between data lines
|
|
||||||
*/
|
|
||||||
i = 0;
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt; /* pointer arith! */
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *) base;
|
memctl->memc_or1 |= ~(maxsize - 1);
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt; /* pointer arith! */
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
/* Write the actual size to ORx
|
|
||||||
*/
|
|
||||||
memctl->memc_or1 |= ~(cnt * sizeof (long) - 1);
|
|
||||||
maxsize = cnt * sizeof (long) / 2;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
maxsize *= 2;
|
|
||||||
if (maxsize != hwc_main_sdram_size ())
|
if (maxsize != hwc_main_sdram_size ())
|
||||||
printf ("Oops: memory test has not found all memory!\n");
|
printf ("Oops: memory test has not found all memory!\n");
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -41,8 +41,7 @@ static long int dram_size (long int, long int *, long int);
|
||||||
/*
|
/*
|
||||||
* 50 MHz SHARC access using UPM A
|
* 50 MHz SHARC access using UPM A
|
||||||
*/
|
*/
|
||||||
const uint sharc_table[] =
|
const uint sharc_table[] = {
|
||||||
{
|
|
||||||
/*
|
/*
|
||||||
* Single Read. (Offset 0 in UPM RAM)
|
* Single Read. (Offset 0 in UPM RAM)
|
||||||
*/
|
*/
|
||||||
|
@ -89,8 +88,7 @@ const uint sharc_table[] =
|
||||||
/*
|
/*
|
||||||
* 50 MHz SDRAM access using UPM B
|
* 50 MHz SDRAM access using UPM B
|
||||||
*/
|
*/
|
||||||
const uint sdram_table[] =
|
const uint sdram_table[] = {
|
||||||
{
|
|
||||||
/*
|
/*
|
||||||
* Single Read. (Offset 0 in UPM RAM)
|
* Single Read. (Offset 0 in UPM RAM)
|
||||||
*/
|
*/
|
||||||
|
@ -161,8 +159,7 @@ int checkboard (void)
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
||||||
long int
|
long int initdram (int board_type)
|
||||||
initdram (int board_type)
|
|
||||||
{
|
{
|
||||||
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immr->im_memctl;
|
volatile memctl8xx_t *memctl = &immr->im_memctl;
|
||||||
|
@ -190,7 +187,8 @@ initdram (int board_type)
|
||||||
/*
|
/*
|
||||||
* Configure UPMA for SHARC
|
* Configure UPMA for SHARC
|
||||||
*/
|
*/
|
||||||
upmconfig(UPMA, (uint *)sharc_table, sizeof(sharc_table)/sizeof(uint));
|
upmconfig (UPMA, (uint *) sharc_table,
|
||||||
|
sizeof (sharc_table) / sizeof (uint));
|
||||||
|
|
||||||
#if defined(CONFIG_IVML24)
|
#if defined(CONFIG_IVML24)
|
||||||
/*
|
/*
|
||||||
|
@ -211,7 +209,8 @@ initdram (int board_type)
|
||||||
/*
|
/*
|
||||||
* Configure UPMB for SDRAM
|
* Configure UPMB for SDRAM
|
||||||
*/
|
*/
|
||||||
upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
|
upmconfig (UPMB, (uint *) sdram_table,
|
||||||
|
sizeof (sdram_table) / sizeof (uint));
|
||||||
|
|
||||||
memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
|
memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
|
||||||
|
|
||||||
|
@ -251,7 +250,9 @@ initdram (int board_type)
|
||||||
/*
|
/*
|
||||||
* Check Bank 0 Memory Size for re-configuration
|
* Check Bank 0 Memory Size for re-configuration
|
||||||
*/
|
*/
|
||||||
size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
|
size_b0 =
|
||||||
|
dram_size (CFG_MBMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
|
||||||
|
SDRAM_MAX_SIZE);
|
||||||
|
|
||||||
memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
|
memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
|
||||||
|
|
||||||
|
@ -268,46 +269,15 @@ initdram (int board_type)
|
||||||
* - short between data lines
|
* - short between data lines
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
|
static long int dram_size (long int mamr_value, long int *base,
|
||||||
|
long int maxsize)
|
||||||
{
|
{
|
||||||
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immr->im_memctl;
|
volatile memctl8xx_t *memctl = &immr->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
memctl->memc_mbmr = mamr_value;
|
memctl->memc_mbmr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size (base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof(long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
|
@ -230,42 +230,10 @@ static long int dram_size (long int mamr_value, long int *base,
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
return(get_ram_size(base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof (long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
|
@ -39,8 +39,7 @@ static long int dram_size (long int, long int *, long int);
|
||||||
|
|
||||||
#define _NOT_USED_ 0xFFFFFFFF
|
#define _NOT_USED_ 0xFFFFFFFF
|
||||||
|
|
||||||
const uint sdram_table[] =
|
const uint sdram_table[] = {
|
||||||
{
|
|
||||||
/*
|
/*
|
||||||
* Single Read. (Offset 0 in UPMA RAM)
|
* Single Read. (Offset 0 in UPMA RAM)
|
||||||
*/
|
*/
|
||||||
|
@ -120,7 +119,8 @@ long int initdram (int board_type)
|
||||||
/*
|
/*
|
||||||
* Configure UPMA for SDRAM
|
* Configure UPMA for SDRAM
|
||||||
*/
|
*/
|
||||||
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
|
upmconfig (UPMA, (uint *) sdram_table,
|
||||||
|
sizeof (sdram_table) / sizeof (uint));
|
||||||
|
|
||||||
memctl->memc_mptpr = CFG_MPTPR_1BK_8K /* XXX CFG_MPTPR XXX */ ;
|
memctl->memc_mptpr = CFG_MPTPR_1BK_8K /* XXX CFG_MPTPR XXX */ ;
|
||||||
|
|
||||||
|
@ -138,16 +138,20 @@ long int initdram (int board_type)
|
||||||
|
|
||||||
/* mode initialization (offset 5) */
|
/* mode initialization (offset 5) */
|
||||||
udelay (200); /* 0x80006105 */
|
udelay (200); /* 0x80006105 */
|
||||||
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x05);
|
memctl->memc_mcr =
|
||||||
|
MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);
|
||||||
|
|
||||||
/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
|
/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
|
||||||
udelay (1); /* 0x80006130 */
|
udelay (1); /* 0x80006130 */
|
||||||
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
|
memctl->memc_mcr =
|
||||||
|
MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
|
||||||
udelay (1); /* 0x80006130 */
|
udelay (1); /* 0x80006130 */
|
||||||
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x30);
|
memctl->memc_mcr =
|
||||||
|
MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
|
||||||
|
|
||||||
udelay (1); /* 0x80006106 */
|
udelay (1); /* 0x80006106 */
|
||||||
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x06);
|
memctl->memc_mcr =
|
||||||
|
MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
|
||||||
|
|
||||||
memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */
|
memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */
|
||||||
|
|
||||||
|
@ -155,7 +159,7 @@ long int initdram (int board_type)
|
||||||
|
|
||||||
/* Need at least 10 DRAM accesses to stabilize */
|
/* Need at least 10 DRAM accesses to stabilize */
|
||||||
for (i = 0; i < 10; ++i) {
|
for (i = 0; i < 10; ++i) {
|
||||||
volatile unsigned long *addr = \
|
volatile unsigned long *addr =
|
||||||
(volatile unsigned long *) SDRAM_BASE3_PRELIM;
|
(volatile unsigned long *) SDRAM_BASE3_PRELIM;
|
||||||
unsigned long val;
|
unsigned long val;
|
||||||
|
|
||||||
|
@ -167,8 +171,7 @@ long int initdram (int board_type)
|
||||||
* Check Bank 0 Memory Size for re-configuration
|
* Check Bank 0 Memory Size for re-configuration
|
||||||
*/
|
*/
|
||||||
size_b0 = dram_size (CFG_MAMR_8COL,
|
size_b0 = dram_size (CFG_MAMR_8COL,
|
||||||
(ulong *)SDRAM_BASE3_PRELIM,
|
(ulong *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
|
||||||
SDRAM_MAX_SIZE);
|
|
||||||
|
|
||||||
memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
|
memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
|
||||||
|
|
||||||
|
@ -193,44 +196,13 @@ long int initdram (int board_type)
|
||||||
* - short between data lines
|
* - short between data lines
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
|
static long int dram_size (long int mamr_value, long int *base,
|
||||||
|
long int maxsize)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size (base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof(long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -326,42 +326,10 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
|
||||||
{
|
{
|
||||||
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immr->im_memctl;
|
volatile memctl8xx_t *memctl = &immr->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size(base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof (long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
|
@ -47,35 +47,16 @@ int checkflash (void)
|
||||||
|
|
||||||
long int initdram (int board_type)
|
long int initdram (int board_type)
|
||||||
{
|
{
|
||||||
int i, cnt;
|
long size;
|
||||||
volatile uchar * base= CFG_SDRAM_BASE;
|
long new_bank0_end;
|
||||||
volatile ulong * addr;
|
long mear1;
|
||||||
ulong save[32];
|
long emear1;
|
||||||
ulong val, ret = 0;
|
|
||||||
|
|
||||||
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
|
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
|
||||||
addr = (volatile ulong *)base + cnt;
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *)base;
|
new_bank0_end = size - 1;
|
||||||
save[i] = *addr;
|
mear1 = mpc824x_mpc107_getreg(MEAR1);
|
||||||
*addr = 0;
|
emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
||||||
|
|
||||||
if (*addr != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *)base + cnt;
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
ulong new_bank0_end = cnt * sizeof(long) - 1;
|
|
||||||
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
|
|
||||||
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
|
||||||
mear1 = (mear1 & 0xFFFFFF00) |
|
mear1 = (mear1 & 0xFFFFFF00) |
|
||||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
||||||
emear1 = (emear1 & 0xFFFFFF00) |
|
emear1 = (emear1 & 0xFFFFFF00) |
|
||||||
|
@ -83,14 +64,7 @@ long int initdram (int board_type)
|
||||||
mpc824x_mpc107_setreg(MEAR1, mear1);
|
mpc824x_mpc107_setreg(MEAR1, mear1);
|
||||||
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
||||||
|
|
||||||
ret = cnt * sizeof(long);
|
return (size);
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = CFG_MAX_RAM_SIZE;
|
|
||||||
Done:
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -77,53 +77,24 @@ int checkboard (void)
|
||||||
|
|
||||||
long int initdram (int board_type)
|
long int initdram (int board_type)
|
||||||
{
|
{
|
||||||
int i, cnt;
|
long size;
|
||||||
volatile uchar *base = CFG_SDRAM_BASE;
|
long new_bank0_end;
|
||||||
volatile ulong *addr;
|
long mear1;
|
||||||
ulong save[32];
|
long emear1;
|
||||||
ulong val, ret = 0;
|
|
||||||
|
|
||||||
for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
|
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
|
||||||
cnt >>= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt;
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *) base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
if (*addr != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt;
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
ulong new_bank0_end = cnt * sizeof (long) - 1;
|
|
||||||
ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
|
|
||||||
ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
|
|
||||||
|
|
||||||
|
new_bank0_end = size - 1;
|
||||||
|
mear1 = mpc824x_mpc107_getreg(MEAR1);
|
||||||
|
emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
||||||
mear1 = (mear1 & 0xFFFFFF00) |
|
mear1 = (mear1 & 0xFFFFFF00) |
|
||||||
((new_bank0_end & MICR_ADDR_MASK) >>
|
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
||||||
MICR_ADDR_SHIFT);
|
|
||||||
emear1 = (emear1 & 0xFFFFFF00) |
|
emear1 = (emear1 & 0xFFFFFF00) |
|
||||||
((new_bank0_end & MICR_ADDR_MASK) >>
|
((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
|
||||||
MICR_EADDR_SHIFT);
|
|
||||||
mpc824x_mpc107_setreg(MEAR1, mear1);
|
mpc824x_mpc107_setreg(MEAR1, mear1);
|
||||||
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
||||||
ret = cnt * sizeof (long);
|
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = CFG_MAX_RAM_SIZE;
|
return (size);
|
||||||
Done:
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
|
@ -337,37 +337,10 @@ static long int dram_size (long int mamr_value, long int *base,
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
long int cnt, val;
|
|
||||||
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size(base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1;; cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof (long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* NOTREACHED */
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -36,16 +36,12 @@ static long int dram_size (long int, long int *, long int);
|
||||||
|
|
||||||
#define _NOT_USED_ 0xFFFFFFFF
|
#define _NOT_USED_ 0xFFFFFFFF
|
||||||
|
|
||||||
const uint sdram_table[] =
|
const uint sdram_table[] = {
|
||||||
{
|
|
||||||
#if (MPC8XX_SPEED <= 50000000L)
|
#if (MPC8XX_SPEED <= 50000000L)
|
||||||
/*
|
/*
|
||||||
* Single Read. (Offset 0 in UPMA RAM)
|
* Single Read. (Offset 0 in UPMA RAM)
|
||||||
*/
|
*/
|
||||||
0x0F07EC04,
|
0x0F07EC04, 0x01BBD804, 0x1FF7F440, 0xFFFFFC07,
|
||||||
0x01BBD804,
|
|
||||||
0x1FF7F440,
|
|
||||||
0xFFFFFC07,
|
|
||||||
0xFFFFFFFF,
|
0xFFFFFFFF,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -56,95 +52,47 @@ const uint sdram_table[] =
|
||||||
* sequence, which is executed by a RUN command.
|
* sequence, which is executed by a RUN command.
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
0x1FE7F434,
|
0x1FE7F434, 0xEFABE834, 0x1FA7D435,
|
||||||
0xEFABE834,
|
|
||||||
0x1FA7D435,
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Burst Read. (Offset 8 in UPMA RAM)
|
* Burst Read. (Offset 8 in UPMA RAM)
|
||||||
*/
|
*/
|
||||||
0x0F07EC04,
|
0x0F07EC04, 0x10EFDC04, 0xF0AFFC00, 0xF0AFFC00,
|
||||||
0x10EFDC04,
|
0xF1AFFC00, 0xFFAFFC40, 0xFFAFFC07, 0xFFFFFFFF,
|
||||||
0xF0AFFC00,
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||||
0xF0AFFC00,
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||||
0xF1AFFC00,
|
|
||||||
0xFFAFFC40,
|
|
||||||
0xFFAFFC07,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Single Write. (Offset 18 in UPMA RAM)
|
* Single Write. (Offset 18 in UPMA RAM)
|
||||||
*/
|
*/
|
||||||
0x0E07E804,
|
0x0E07E804, 0x01BBD000, 0x1FF7F447, 0xFFFFFFFF,
|
||||||
0x01BBD000,
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||||
0x1FF7F447,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Burst Write. (Offset 20 in UPMA RAM)
|
* Burst Write. (Offset 20 in UPMA RAM)
|
||||||
*/
|
*/
|
||||||
0x0E07E800,
|
0x0E07E800, 0x10EFD400, 0xF0AFFC00, 0xF0AFFC00,
|
||||||
0x10EFD400,
|
0xF1AFFC47, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||||
0xF0AFFC00,
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||||
0xF0AFFC00,
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||||
0xF1AFFC47,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Refresh (Offset 30 in UPMA RAM)
|
* Refresh (Offset 30 in UPMA RAM)
|
||||||
*/
|
*/
|
||||||
0x1FF7DC84,
|
0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC84, 0xFFFFFC07,
|
||||||
0xFFFFFC04,
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||||
0xFFFFFC84,
|
0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
|
||||||
0xFFFFFC07,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Exception. (Offset 3c in UPMA RAM)
|
* Exception. (Offset 3c in UPMA RAM)
|
||||||
*/
|
*/
|
||||||
0x7FFFFC07,
|
0x7FFFFC07, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF,
|
|
||||||
0xFFFFFFFF
|
|
||||||
|
|
||||||
#else
|
#else
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Single Read. (Offset 0 in UPMA RAM)
|
* Single Read. (Offset 0 in UPMA RAM)
|
||||||
*/
|
*/
|
||||||
0x1F07FC04,
|
0x1F07FC04, 0xEEAFEC04, 0x11AFDC04, 0xEFBBF800,
|
||||||
0xEEAFEC04,
|
|
||||||
0x11AFDC04,
|
|
||||||
0xEFBBF800,
|
|
||||||
0x1FF7F447,
|
0x1FF7F447,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -155,55 +103,35 @@ const uint sdram_table[] =
|
||||||
* sequence, which is executed by a RUN command.
|
* sequence, which is executed by a RUN command.
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
0x1FF7F434,
|
0x1FF7F434, 0xEFEBE834, 0x1FB7D435,
|
||||||
0xEFEBE834,
|
|
||||||
0x1FB7D435,
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Burst Read. (Offset 8 in UPMA RAM)
|
* Burst Read. (Offset 8 in UPMA RAM)
|
||||||
*/
|
*/
|
||||||
0x1F07FC04,
|
0x1F07FC04, 0xEEAFEC04, 0x10AFDC04, 0xF0AFFC00,
|
||||||
0xEEAFEC04,
|
0xF0AFFC00, 0xF1AFFC00, 0xEFBBF800, 0x1FF7F447,
|
||||||
0x10AFDC04,
|
|
||||||
0xF0AFFC00,
|
|
||||||
0xF0AFFC00,
|
|
||||||
0xF1AFFC00,
|
|
||||||
0xEFBBF800,
|
|
||||||
0x1FF7F447,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Single Write. (Offset 18 in UPMA RAM)
|
* Single Write. (Offset 18 in UPMA RAM)
|
||||||
*/
|
*/
|
||||||
0x1F07FC04,
|
0x1F07FC04, 0xEEAFE800, 0x01BBD004, 0x1FF7F447,
|
||||||
0xEEAFE800,
|
|
||||||
0x01BBD004,
|
|
||||||
0x1FF7F447,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Burst Write. (Offset 20 in UPMA RAM)
|
* Burst Write. (Offset 20 in UPMA RAM)
|
||||||
*/
|
*/
|
||||||
0x1F07FC04,
|
0x1F07FC04, 0xEEAFE800, 0x10AFD400, 0xF0AFFC00,
|
||||||
0xEEAFE800,
|
0xF0AFFC00, 0xE1BBF804, 0x1FF7F447, _NOT_USED_,
|
||||||
0x10AFD400,
|
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
0xF0AFFC00,
|
|
||||||
0xF0AFFC00,
|
|
||||||
0xE1BBF804,
|
|
||||||
0x1FF7F447,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Refresh (Offset 30 in UPMA RAM)
|
* Refresh (Offset 30 in UPMA RAM)
|
||||||
*/
|
*/
|
||||||
0x1FF7DC84,
|
0x1FF7DC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
|
||||||
0xFFFFFC04,
|
0xFFFFFC84, 0xFFFFFC07,
|
||||||
0xFFFFFC04,
|
|
||||||
0xFFFFFC04,
|
|
||||||
0xFFFFFC84,
|
|
||||||
0xFFFFFC07,
|
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
_NOT_USED_, _NOT_USED_, _NOT_USED_,
|
||||||
|
|
||||||
|
@ -237,7 +165,8 @@ long int initdram (int board_type)
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
long int size_b0, size_b1, size8, size9;
|
long int size_b0, size_b1, size8, size9;
|
||||||
|
|
||||||
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
|
upmconfig (UPMA, (uint *) sdram_table,
|
||||||
|
sizeof (sdram_table) / sizeof (uint));
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Up to 2 Banks of 64Mbit x 2 devices
|
* Up to 2 Banks of 64Mbit x 2 devices
|
||||||
|
@ -292,14 +221,16 @@ long int initdram (int board_type)
|
||||||
*
|
*
|
||||||
* try 8 column mode
|
* try 8 column mode
|
||||||
*/
|
*/
|
||||||
size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
|
size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE1_PRELIM,
|
||||||
|
SDRAM_MAX_SIZE);
|
||||||
|
|
||||||
udelay (1000);
|
udelay (1000);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* try 9 column mode
|
* try 9 column mode
|
||||||
*/
|
*/
|
||||||
size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
|
size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE1_PRELIM,
|
||||||
|
SDRAM_MAX_SIZE);
|
||||||
|
|
||||||
if (size8 < size9) { /* leave configuration at 9 columns */
|
if (size8 < size9) { /* leave configuration at 9 columns */
|
||||||
size_b0 = size9;
|
size_b0 = size9;
|
||||||
|
@ -338,18 +269,25 @@ long int initdram (int board_type)
|
||||||
*/
|
*/
|
||||||
if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
|
if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
|
||||||
|
|
||||||
memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
|
memctl->memc_or2 =
|
||||||
memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
|
((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
|
||||||
|
memctl->memc_br2 =
|
||||||
|
(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
|
||||||
|
|
||||||
if (size_b0 > 0) {
|
if (size_b0 > 0) {
|
||||||
/*
|
/*
|
||||||
* Position Bank 0 immediately above Bank 1
|
* Position Bank 0 immediately above Bank 1
|
||||||
*/
|
*/
|
||||||
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
|
memctl->memc_or1 =
|
||||||
memctl->memc_br1 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
|
((-size_b0) & 0xFFFF0000) |
|
||||||
|
CFG_OR_TIMING_SDRAM;
|
||||||
|
memctl->memc_br1 =
|
||||||
|
((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
|
||||||
|
BR_V)
|
||||||
+ size_b1;
|
+ size_b1;
|
||||||
} else {
|
} else {
|
||||||
unsigned long reg;
|
unsigned long reg;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* No bank 0
|
* No bank 0
|
||||||
*
|
*
|
||||||
|
@ -365,18 +303,25 @@ long int initdram (int board_type)
|
||||||
|
|
||||||
} else { /* SDRAM Bank 0 is bigger - map first */
|
} else { /* SDRAM Bank 0 is bigger - map first */
|
||||||
|
|
||||||
memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
|
memctl->memc_or1 =
|
||||||
memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
|
((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
|
||||||
|
memctl->memc_br1 =
|
||||||
|
(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
|
||||||
|
|
||||||
if (size_b1 > 0) {
|
if (size_b1 > 0) {
|
||||||
/*
|
/*
|
||||||
* Position Bank 1 immediately above Bank 0
|
* Position Bank 1 immediately above Bank 0
|
||||||
*/
|
*/
|
||||||
memctl->memc_or2 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
|
memctl->memc_or2 =
|
||||||
memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
|
((-size_b1) & 0xFFFF0000) |
|
||||||
|
CFG_OR_TIMING_SDRAM;
|
||||||
|
memctl->memc_br2 =
|
||||||
|
((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
|
||||||
|
BR_V)
|
||||||
+ size_b0;
|
+ size_b0;
|
||||||
} else {
|
} else {
|
||||||
unsigned long reg;
|
unsigned long reg;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* No bank 1
|
* No bank 1
|
||||||
*
|
*
|
||||||
|
@ -406,40 +351,15 @@ long int initdram (int board_type)
|
||||||
* - short between data lines
|
* - short between data lines
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
|
static long int dram_size (long int mamr_value, long int *base,
|
||||||
|
long int maxsize)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
long int cnt, val;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size (base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; ; cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof(long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* NOTREACHED */
|
|
||||||
}
|
}
|
||||||
|
|
||||||
u_long *my_sernum;
|
u_long *my_sernum;
|
||||||
|
@ -459,8 +379,8 @@ int misc_init_r (void)
|
||||||
sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]);
|
sprintf (tmp, "%08lx%08lx", my_sernum[0], my_sernum[1]);
|
||||||
setenv ("serial#", tmp);
|
setenv ("serial#", tmp);
|
||||||
|
|
||||||
sprintf(tmp,"%02x:%02x:%02x:%02x:%02x:%02x"
|
sprintf (tmp, "%02x:%02x:%02x:%02x:%02x:%02x", e[0], e[1], e[2], e[3],
|
||||||
,e[0],e[1],e[2],e[3],e[4],e[5]);
|
e[4], e[5]);
|
||||||
setenv ("ethaddr", tmp);
|
setenv ("ethaddr", tmp);
|
||||||
return (0);
|
return (0);
|
||||||
}
|
}
|
||||||
|
|
|
@ -35,35 +35,16 @@ int checkboard (void)
|
||||||
long int initdram (int board_type)
|
long int initdram (int board_type)
|
||||||
{
|
{
|
||||||
#ifndef CFG_RAMBOOT
|
#ifndef CFG_RAMBOOT
|
||||||
int i, cnt;
|
long size;
|
||||||
volatile uchar * base= CFG_SDRAM_BASE;
|
long new_bank0_end;
|
||||||
volatile ulong * addr;
|
long mear1;
|
||||||
ulong save[32];
|
long emear1;
|
||||||
ulong val, ret = 0;
|
|
||||||
|
|
||||||
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
|
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
|
||||||
addr = (volatile ulong *)base + cnt;
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *)base;
|
new_bank0_end = size - 1;
|
||||||
save[i] = *addr;
|
mear1 = mpc824x_mpc107_getreg(MEAR1);
|
||||||
*addr = 0;
|
emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
||||||
|
|
||||||
if (*addr != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *)base + cnt;
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
ulong new_bank0_end = cnt * sizeof(long) - 1;
|
|
||||||
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
|
|
||||||
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
|
||||||
mear1 = (mear1 & 0xFFFFFF00) |
|
mear1 = (mear1 & 0xFFFFFF00) |
|
||||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
||||||
emear1 = (emear1 & 0xFFFFFF00) |
|
emear1 = (emear1 & 0xFFFFFF00) |
|
||||||
|
@ -71,14 +52,7 @@ long int initdram (int board_type)
|
||||||
mpc824x_mpc107_setreg(MEAR1, mear1);
|
mpc824x_mpc107_setreg(MEAR1, mear1);
|
||||||
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
||||||
|
|
||||||
ret = cnt * sizeof(long);
|
return (size);
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = CFG_MAX_RAM_SIZE;
|
|
||||||
Done:
|
|
||||||
return ret;
|
|
||||||
#else
|
#else
|
||||||
/* if U-Boot starts from RAM, then suppose we have 16Mb of RAM */
|
/* if U-Boot starts from RAM, then suppose we have 16Mb of RAM */
|
||||||
return (16 << 20);
|
return (16 << 20);
|
||||||
|
|
|
@ -221,13 +221,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
|
||||||
ulong orx, volatile uchar * base)
|
ulong orx, volatile uchar * base)
|
||||||
{
|
{
|
||||||
volatile uchar c = 0xff;
|
volatile uchar c = 0xff;
|
||||||
volatile ulong cnt, val;
|
|
||||||
volatile ulong *addr;
|
|
||||||
volatile uint *sdmr_ptr;
|
volatile uint *sdmr_ptr;
|
||||||
volatile uint *orx_ptr;
|
volatile uint *orx_ptr;
|
||||||
|
ulong maxsize, size;
|
||||||
int i;
|
int i;
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
ulong maxsize;
|
|
||||||
|
|
||||||
/* We must be able to test a location outsize the maximum legal size
|
/* We must be able to test a location outsize the maximum legal size
|
||||||
* to find out THAT we are outside; but this address still has to be
|
* to find out THAT we are outside; but this address still has to be
|
||||||
|
@ -274,41 +271,11 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
|
||||||
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
||||||
*base = c;
|
*base = c;
|
||||||
|
|
||||||
/*
|
size = get_ram_size((long *)base, maxsize);
|
||||||
* Check memory range for valid RAM. A simple memory test determines
|
|
||||||
* the actually available RAM size between addresses `base' and
|
|
||||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
|
||||||
* - short between address lines
|
|
||||||
* - short between data lines
|
|
||||||
*/
|
|
||||||
i = 0;
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt; /* pointer arith! */
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *) base;
|
*orx_ptr = orx | ~(size - 1);
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
if ((val = *addr) != 0) {
|
return (size);
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt; /* pointer arith! */
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
/* Write the actual size to ORx
|
|
||||||
*/
|
|
||||||
*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
|
|
||||||
return (cnt * sizeof (long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -76,39 +76,18 @@ int checkboard (void)
|
||||||
|
|
||||||
long int initdram (int board_type)
|
long int initdram (int board_type)
|
||||||
{
|
{
|
||||||
int i, cnt;
|
long size;
|
||||||
volatile uchar *base = CFG_SDRAM_BASE;
|
long new_bank0_end;
|
||||||
volatile ulong *addr;
|
long mear1;
|
||||||
ulong save[32];
|
long emear1;
|
||||||
ulong val, ret = 0;
|
|
||||||
|
|
||||||
show_startup_phase (2);
|
show_startup_phase (2);
|
||||||
|
|
||||||
for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
|
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
|
||||||
cnt >>= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt;
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *) base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
if (*addr != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt;
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
ulong new_bank0_end = cnt * sizeof (long) - 1;
|
|
||||||
ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
|
|
||||||
ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
|
|
||||||
|
|
||||||
|
new_bank0_end = size - 1;
|
||||||
|
mear1 = mpc824x_mpc107_getreg (MEAR1);
|
||||||
|
emear1 = mpc824x_mpc107_getreg (EMEAR1);
|
||||||
mear1 = (mear1 & 0xFFFFFF00) |
|
mear1 = (mear1 & 0xFFFFFF00) |
|
||||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
||||||
emear1 = (emear1 & 0xFFFFFF00) |
|
emear1 = (emear1 & 0xFFFFFF00) |
|
||||||
|
@ -116,15 +95,7 @@ long int initdram (int board_type)
|
||||||
mpc824x_mpc107_setreg (MEAR1, mear1);
|
mpc824x_mpc107_setreg (MEAR1, mear1);
|
||||||
mpc824x_mpc107_setreg (EMEAR1, emear1);
|
mpc824x_mpc107_setreg (EMEAR1, emear1);
|
||||||
|
|
||||||
ret = cnt * sizeof (long);
|
return (size);
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = CFG_MAX_RAM_SIZE;
|
|
||||||
Done:
|
|
||||||
show_startup_phase (3);
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -258,41 +258,10 @@ static long int dram_size (long int mamr_value,
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size(base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof (long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
|
@ -148,7 +148,8 @@ long int initdram (int board_type)
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
long int size_b0, size8, size9;
|
long int size_b0, size8, size9;
|
||||||
|
|
||||||
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
|
upmconfig (UPMA, (uint *) sdram_table,
|
||||||
|
sizeof (sdram_table) / sizeof (uint));
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* 1 Bank of 64Mbit x 2 devices
|
* 1 Bank of 64Mbit x 2 devices
|
||||||
|
@ -192,13 +193,15 @@ long int initdram (int board_type)
|
||||||
*
|
*
|
||||||
* try 8 column mode
|
* try 8 column mode
|
||||||
*/
|
*/
|
||||||
size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE);
|
size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE4_PRELIM,
|
||||||
|
SDRAM_MAX_SIZE);
|
||||||
udelay (1000);
|
udelay (1000);
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* try 9 column mode
|
* try 9 column mode
|
||||||
*/
|
*/
|
||||||
size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE);
|
size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE4_PRELIM,
|
||||||
|
SDRAM_MAX_SIZE);
|
||||||
|
|
||||||
if (size8 < size9) { /* leave configuration at 9 columns */
|
if (size8 < size9) { /* leave configuration at 9 columns */
|
||||||
size_b0 = size9;
|
size_b0 = size9;
|
||||||
|
@ -242,41 +245,15 @@ long int initdram (int board_type)
|
||||||
* - short between data lines
|
* - short between data lines
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
|
static long int dram_size (long int mamr_value, long int *base,
|
||||||
|
long int maxsize)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
long int cnt, val;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize/sizeof(long)/2; cnt > 0; cnt >>= 1) {
|
return (get_ram_size (base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt < maxsize/sizeof(long) ; cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof(long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return cnt * sizeof(long);
|
|
||||||
/* NOTREACHED */
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void doc_init (void)
|
void doc_init (void)
|
||||||
|
@ -284,7 +261,8 @@ void doc_init(void)
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
|
|
||||||
upmconfig(UPMB, (uint *)static_table, sizeof(static_table)/sizeof(uint));
|
upmconfig (UPMB, (uint *) static_table,
|
||||||
|
sizeof (static_table) / sizeof (uint));
|
||||||
memctl->memc_mbmr = MAMR_DSA_1_CYCL;
|
memctl->memc_mbmr = MAMR_DSA_1_CYCL;
|
||||||
|
|
||||||
doc_probe (FLASH_BASE1_PRELIM);
|
doc_probe (FLASH_BASE1_PRELIM);
|
||||||
|
|
|
@ -155,53 +155,8 @@ static long int dram_size (long int mamr_value, long int *base,
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val, size;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size(base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
/* Restore the original data before leaving the function.
|
|
||||||
*/
|
|
||||||
*addr = save[i];
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt;
|
|
||||||
*addr = save[--i];
|
|
||||||
}
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
size = cnt * sizeof (long);
|
|
||||||
/* Restore the original data before returning
|
|
||||||
*/
|
|
||||||
for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt;
|
|
||||||
*addr = save[--i];
|
|
||||||
}
|
|
||||||
return (size);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -52,35 +52,16 @@ int checkflash (void)
|
||||||
|
|
||||||
long int initdram (int board_type)
|
long int initdram (int board_type)
|
||||||
{
|
{
|
||||||
int i, cnt;
|
long size;
|
||||||
volatile uchar * base= CFG_SDRAM_BASE;
|
long new_bank0_end;
|
||||||
volatile ulong * addr;
|
long mear1;
|
||||||
ulong save[32];
|
long emear1;
|
||||||
ulong val, ret = 0;
|
|
||||||
|
|
||||||
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
|
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
|
||||||
addr = (volatile ulong *)base + cnt;
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *)base;
|
new_bank0_end = size - 1;
|
||||||
save[i] = *addr;
|
mear1 = mpc824x_mpc107_getreg(MEAR1);
|
||||||
*addr = 0;
|
emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
||||||
|
|
||||||
if (*addr != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *)base + cnt;
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
ulong new_bank0_end = cnt * sizeof(long) - 1;
|
|
||||||
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
|
|
||||||
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
|
||||||
mear1 = (mear1 & 0xFFFFFF00) |
|
mear1 = (mear1 & 0xFFFFFF00) |
|
||||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
||||||
emear1 = (emear1 & 0xFFFFFF00) |
|
emear1 = (emear1 & 0xFFFFFF00) |
|
||||||
|
@ -88,14 +69,7 @@ long int initdram (int board_type)
|
||||||
mpc824x_mpc107_setreg(MEAR1, mear1);
|
mpc824x_mpc107_setreg(MEAR1, mear1);
|
||||||
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
||||||
|
|
||||||
ret = cnt * sizeof(long);
|
return (size);
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = CFG_MAX_RAM_SIZE;
|
|
||||||
Done:
|
|
||||||
return ret;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -333,42 +333,10 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size(base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof(long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
|
@ -41,8 +41,7 @@ static long int dram_size (long int, long int *, long int);
|
||||||
|
|
||||||
#define _NOT_USED_ 0xFFFFFFFF
|
#define _NOT_USED_ 0xFFFFFFFF
|
||||||
|
|
||||||
const uint sdram_table[] =
|
const uint sdram_table[] = {
|
||||||
{
|
|
||||||
/*
|
/*
|
||||||
* Single Read. (Offset 0 in UPMA RAM)
|
* Single Read. (Offset 0 in UPMA RAM)
|
||||||
*/
|
*/
|
||||||
|
@ -109,7 +108,8 @@ long int initdram (int board_type)
|
||||||
volatile fec_t *fecp = &immap->im_cpm.cp_fec;
|
volatile fec_t *fecp = &immap->im_cpm.cp_fec;
|
||||||
long int size;
|
long int size;
|
||||||
|
|
||||||
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
|
upmconfig (UPMA, (uint *) sdram_table,
|
||||||
|
sizeof (sdram_table) / sizeof (uint));
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Preliminary prescaler for refresh (depends on number of
|
* Preliminary prescaler for refresh (depends on number of
|
||||||
|
@ -155,7 +155,8 @@ long int initdram (int board_type)
|
||||||
* Check Bank 0 Memory Size for re-configuration
|
* Check Bank 0 Memory Size for re-configuration
|
||||||
*
|
*
|
||||||
*/
|
*/
|
||||||
size = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
|
size = dram_size (CFG_MAMR, (ulong *) SDRAM_BASE_PRELIM,
|
||||||
|
SDRAM_MAX_SIZE);
|
||||||
|
|
||||||
udelay (1000);
|
udelay (1000);
|
||||||
|
|
||||||
|
@ -191,46 +192,15 @@ long int initdram (int board_type)
|
||||||
* - short between data lines
|
* - short between data lines
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
|
static long int dram_size (long int mamr_value, long int *base,
|
||||||
|
long int maxsize)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size (base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof(long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
@ -308,10 +278,9 @@ void board_get_enetaddr (uchar *addr)
|
||||||
|
|
||||||
i2c_reg_read (0xa0, 0);
|
i2c_reg_read (0xa0, 0);
|
||||||
printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
|
printf ("seep = '-%c-%c-%c-%c-%c-%c-'\n",
|
||||||
i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0),
|
i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
|
||||||
i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0), i2c_reg_read(0xa0, 0) );
|
i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0),
|
||||||
|
i2c_reg_read (0xa0, 0), i2c_reg_read (0xa0, 0));
|
||||||
|
|
||||||
cpm->cp_rccr = rccrtmp;
|
cpm->cp_rccr = rccrtmp;
|
||||||
|
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -235,13 +235,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
|
||||||
ulong orx, volatile uchar * base)
|
ulong orx, volatile uchar * base)
|
||||||
{
|
{
|
||||||
volatile uchar c = 0xff;
|
volatile uchar c = 0xff;
|
||||||
ulong cnt, val;
|
|
||||||
volatile ulong *addr;
|
|
||||||
volatile uint *sdmr_ptr;
|
volatile uint *sdmr_ptr;
|
||||||
volatile uint *orx_ptr;
|
volatile uint *orx_ptr;
|
||||||
|
ulong maxsize, size;
|
||||||
int i;
|
int i;
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
ulong maxsize;
|
|
||||||
|
|
||||||
/* We must be able to test a location outsize the maximum legal size
|
/* We must be able to test a location outsize the maximum legal size
|
||||||
* to find out THAT we are outside; but this address still has to be
|
* to find out THAT we are outside; but this address still has to be
|
||||||
|
@ -291,41 +288,11 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
|
||||||
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
||||||
*base = c;
|
*base = c;
|
||||||
|
|
||||||
/*
|
size = get_ram_size((long *)base, maxsize);
|
||||||
* Check memory range for valid RAM. A simple memory test determines
|
|
||||||
* the actually available RAM size between addresses `base' and
|
|
||||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
|
||||||
* - short between address lines
|
|
||||||
* - short between data lines
|
|
||||||
*/
|
|
||||||
i = 0;
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt; /* pointer arith! */
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *) base;
|
*orx_ptr = orx | ~(size - 1);
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
if ((val = *addr) != 0) {
|
return (size);
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt; /* pointer arith! */
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
/* Write the actual size to ORx
|
|
||||||
*/
|
|
||||||
*orx_ptr = orx | ~(cnt * sizeof (long) - 1);
|
|
||||||
return (cnt * sizeof (long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -42,8 +42,7 @@ static void puma_load (ulong addr, ulong len);
|
||||||
/*
|
/*
|
||||||
* 50 MHz SDRAM access using UPM A
|
* 50 MHz SDRAM access using UPM A
|
||||||
*/
|
*/
|
||||||
const uint sdram_table[] =
|
const uint sdram_table[] = {
|
||||||
{
|
|
||||||
/*
|
/*
|
||||||
* Single Read. (Offset 0 in UPM RAM)
|
* Single Read. (Offset 0 in UPM RAM)
|
||||||
*/
|
*/
|
||||||
|
@ -98,8 +97,7 @@ const uint sdram_table[] =
|
||||||
/*
|
/*
|
||||||
* PUMA access using UPM B
|
* PUMA access using UPM B
|
||||||
*/
|
*/
|
||||||
const uint puma_table[] =
|
const uint puma_table[] = {
|
||||||
{
|
|
||||||
/*
|
/*
|
||||||
* Single Read. (Offset 0 in UPM RAM)
|
* Single Read. (Offset 0 in UPM RAM)
|
||||||
*/
|
*/
|
||||||
|
@ -158,8 +156,7 @@ int checkboard (void)
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
||||||
long int
|
long int initdram (int board_type)
|
||||||
initdram (int board_type)
|
|
||||||
{
|
{
|
||||||
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immr->im_memctl;
|
volatile memctl8xx_t *memctl = &immr->im_memctl;
|
||||||
|
@ -169,7 +166,8 @@ initdram (int board_type)
|
||||||
/*
|
/*
|
||||||
* Configure UPMA for SDRAM
|
* Configure UPMA for SDRAM
|
||||||
*/
|
*/
|
||||||
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
|
upmconfig (UPMA, (uint *) sdram_table,
|
||||||
|
sizeof (sdram_table) / sizeof (uint));
|
||||||
|
|
||||||
memctl->memc_mptpr = CFG_MPTPR;
|
memctl->memc_mptpr = CFG_MPTPR;
|
||||||
|
|
||||||
|
@ -227,9 +225,11 @@ initdram (int board_type)
|
||||||
/* Need at least 10 DRAM accesses to stabilize */
|
/* Need at least 10 DRAM accesses to stabilize */
|
||||||
for (i = 0; i < 10; ++i) {
|
for (i = 0; i < 10; ++i) {
|
||||||
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
#if PCU_E_WITH_SWAPPED_CS /* XXX */
|
||||||
volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE5_PRELIM;
|
volatile unsigned long *addr =
|
||||||
|
(volatile unsigned long *) SDRAM_BASE5_PRELIM;
|
||||||
#else /* XXX */
|
#else /* XXX */
|
||||||
volatile unsigned long *addr = (volatile unsigned long *)SDRAM_BASE2_PRELIM;
|
volatile unsigned long *addr =
|
||||||
|
(volatile unsigned long *) SDRAM_BASE2_PRELIM;
|
||||||
#endif /* XXX */
|
#endif /* XXX */
|
||||||
unsigned long val;
|
unsigned long val;
|
||||||
|
|
||||||
|
@ -264,7 +264,8 @@ initdram (int board_type)
|
||||||
/*
|
/*
|
||||||
* Configure UPMB for PUMA
|
* Configure UPMB for PUMA
|
||||||
*/
|
*/
|
||||||
upmconfig(UPMB, (uint *)puma_table, sizeof(puma_table)/sizeof(uint));
|
upmconfig (UPMB, (uint *) puma_table,
|
||||||
|
sizeof (puma_table) / sizeof (uint));
|
||||||
|
|
||||||
return (size_b0);
|
return (size_b0);
|
||||||
}
|
}
|
||||||
|
@ -279,46 +280,15 @@ initdram (int board_type)
|
||||||
* - short between data lines
|
* - short between data lines
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
|
static long int dram_size (long int mamr_value, long int *base,
|
||||||
|
long int maxsize)
|
||||||
{
|
{
|
||||||
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
volatile immap_t *immr = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immr->im_memctl;
|
volatile memctl8xx_t *memctl = &immr->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size (base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof(long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
@ -432,12 +402,11 @@ int do_puma (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
|
||||||
printf ("Usage:\n%s\n", cmdtp->usage);
|
printf ("Usage:\n%s\n", cmdtp->usage);
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
U_BOOT_CMD(
|
|
||||||
puma, 4, 1, do_puma,
|
U_BOOT_CMD (puma, 4, 1, do_puma,
|
||||||
"puma - access PUMA FPGA\n",
|
"puma - access PUMA FPGA\n",
|
||||||
"status - print PUMA status\n"
|
"status - print PUMA status\n"
|
||||||
"puma load addr len - load PUMA configuration data\n"
|
"puma load addr len - load PUMA configuration data\n");
|
||||||
);
|
|
||||||
|
|
||||||
#endif /* CFG_CMD_BSP */
|
#endif /* CFG_CMD_BSP */
|
||||||
|
|
||||||
|
|
|
@ -37,35 +37,16 @@ int checkboard (void)
|
||||||
long int initdram (int board_type)
|
long int initdram (int board_type)
|
||||||
{
|
{
|
||||||
#ifndef CFG_RAMBOOT
|
#ifndef CFG_RAMBOOT
|
||||||
int i, cnt;
|
long size;
|
||||||
volatile uchar * base= CFG_SDRAM_BASE;
|
long new_bank0_end;
|
||||||
volatile ulong * addr;
|
long mear1;
|
||||||
ulong save[32];
|
long emear1;
|
||||||
ulong val, ret = 0;
|
|
||||||
|
|
||||||
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
|
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
|
||||||
addr = (volatile ulong *)base + cnt;
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *)base;
|
new_bank0_end = size - 1;
|
||||||
save[i] = *addr;
|
mear1 = mpc824x_mpc107_getreg(MEAR1);
|
||||||
*addr = 0;
|
emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
||||||
|
|
||||||
if (*addr != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt < CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *)base + cnt;
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
ulong new_bank0_end = cnt * sizeof(long) - 1;
|
|
||||||
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
|
|
||||||
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
|
||||||
mear1 = (mear1 & 0xFFFFFF00) |
|
mear1 = (mear1 & 0xFFFFFF00) |
|
||||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
||||||
emear1 = (emear1 & 0xFFFFFF00) |
|
emear1 = (emear1 & 0xFFFFFF00) |
|
||||||
|
@ -73,14 +54,7 @@ long int initdram (int board_type)
|
||||||
mpc824x_mpc107_setreg(MEAR1, mear1);
|
mpc824x_mpc107_setreg(MEAR1, mear1);
|
||||||
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
||||||
|
|
||||||
ret = cnt * sizeof(long);
|
return (size);
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = CFG_MAX_RAM_SIZE;
|
|
||||||
Done:
|
|
||||||
return ret;
|
|
||||||
#else
|
#else
|
||||||
return CFG_MAX_RAM_SIZE;
|
return CFG_MAX_RAM_SIZE;
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -222,32 +222,8 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
long int cnt, val;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size(base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; ; cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
val = *addr;
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof(long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* NOTREACHED */
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -229,31 +229,8 @@ static long int dram_size (long int mbmr_value, long int *base, long int maxsize
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
long int cnt, val;
|
|
||||||
|
|
||||||
memctl->memc_mbmr = mbmr_value;
|
memctl->memc_mbmr = mbmr_value;
|
||||||
|
|
||||||
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size(base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; ; cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
val = *addr;
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof(long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* NOTREACHED */
|
|
||||||
}
|
}
|
||||||
|
|
|
@ -34,8 +34,7 @@ static long int dram_size (long int, long int *, long int);
|
||||||
|
|
||||||
#define _NOT_USED_ 0xFFFFFFFF
|
#define _NOT_USED_ 0xFFFFFFFF
|
||||||
|
|
||||||
const uint sharc_table[] =
|
const uint sharc_table[] = {
|
||||||
{
|
|
||||||
/*
|
/*
|
||||||
* Single Read. (Offset 0 in UPM RAM)
|
* Single Read. (Offset 0 in UPM RAM)
|
||||||
*/
|
*/
|
||||||
|
@ -79,8 +78,7 @@ const uint sharc_table[] =
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
const uint sdram_table[] =
|
const uint sdram_table[] = {
|
||||||
{
|
|
||||||
/*
|
/*
|
||||||
* Single Read. (Offset 0 in UPM RAM)
|
* Single Read. (Offset 0 in UPM RAM)
|
||||||
*/
|
*/
|
||||||
|
@ -145,8 +143,7 @@ int checkboard (void)
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
||||||
long int
|
long int initdram (int board_type)
|
||||||
initdram (int board_type)
|
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
|
@ -168,7 +165,8 @@ initdram (int board_type)
|
||||||
|
|
||||||
#if 0
|
#if 0
|
||||||
/* Configure SHARC at UMA */
|
/* Configure SHARC at UMA */
|
||||||
upmconfig(UPMA, (uint *)sharc_table, sizeof(sharc_table)/sizeof(uint));
|
upmconfig (UPMA, (uint *) sharc_table,
|
||||||
|
sizeof (sharc_table) / sizeof (uint));
|
||||||
/* Map controller bank 5 to the SHARC */
|
/* Map controller bank 5 to the SHARC */
|
||||||
memctl->memc_or5 = CFG_OR5;
|
memctl->memc_or5 = CFG_OR5;
|
||||||
memctl->memc_br5 = CFG_BR5;
|
memctl->memc_br5 = CFG_BR5;
|
||||||
|
@ -177,7 +175,8 @@ initdram (int board_type)
|
||||||
memctl->memc_mamr = 0x00001000;
|
memctl->memc_mamr = 0x00001000;
|
||||||
|
|
||||||
/* Configure SDRAM at UMB */
|
/* Configure SDRAM at UMB */
|
||||||
upmconfig(UPMB, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
|
upmconfig (UPMB, (uint *) sdram_table,
|
||||||
|
sizeof (sdram_table) / sizeof (uint));
|
||||||
|
|
||||||
memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
|
memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
|
||||||
|
|
||||||
|
@ -205,7 +204,9 @@ initdram (int board_type)
|
||||||
/*
|
/*
|
||||||
* Check Bank 0 Memory Size for re-configuration
|
* Check Bank 0 Memory Size for re-configuration
|
||||||
*/
|
*/
|
||||||
size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
|
size_b0 =
|
||||||
|
dram_size (CFG_MBMR_8COL, (ulong *) SDRAM_BASE3_PRELIM,
|
||||||
|
SDRAM_MAX_SIZE);
|
||||||
|
|
||||||
memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
|
memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
|
||||||
|
|
||||||
|
@ -222,46 +223,15 @@ initdram (int board_type)
|
||||||
* - short between data lines
|
* - short between data lines
|
||||||
*/
|
*/
|
||||||
|
|
||||||
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
|
static long int dram_size (long int mamr_value, long int *base,
|
||||||
|
long int maxsize)
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
memctl->memc_mbmr = mamr_value;
|
memctl->memc_mbmr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size (base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
return (cnt * sizeof(long));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
|
@ -224,13 +224,10 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
|
||||||
ulong orx, volatile uchar * base)
|
ulong orx, volatile uchar * base)
|
||||||
{
|
{
|
||||||
volatile uchar c = 0xff;
|
volatile uchar c = 0xff;
|
||||||
ulong cnt, val;
|
|
||||||
volatile ulong *addr;
|
|
||||||
volatile uint *sdmr_ptr;
|
volatile uint *sdmr_ptr;
|
||||||
volatile uint *orx_ptr;
|
volatile uint *orx_ptr;
|
||||||
int i;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
ulong maxsize, size;
|
ulong maxsize, size;
|
||||||
|
int i;
|
||||||
|
|
||||||
/* We must be able to test a location outsize the maximum legal size
|
/* We must be able to test a location outsize the maximum legal size
|
||||||
* to find out THAT we are outside; but this address still has to be
|
* to find out THAT we are outside; but this address still has to be
|
||||||
|
@ -280,53 +277,11 @@ static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
|
||||||
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
|
||||||
*base = c;
|
*base = c;
|
||||||
|
|
||||||
/*
|
size = get_ram_size((long *)base, maxsize);
|
||||||
* Check memory range for valid RAM. A simple memory test determines
|
|
||||||
* the actually available RAM size between addresses `base' and
|
|
||||||
* `base + maxsize'. Some (not all) hardware errors are detected:
|
|
||||||
* - short between address lines
|
|
||||||
* - short between data lines
|
|
||||||
*/
|
|
||||||
i = 0;
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt; /* pointer arith! */
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *) base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
/* Restore the original data before leaving the function. */
|
|
||||||
*addr = save[i];
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt;
|
|
||||||
*addr = save[--i];
|
|
||||||
}
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt; /* pointer arith! */
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
size = cnt * sizeof (long);
|
|
||||||
/* Restore the original data before leaving the function. */
|
|
||||||
for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt;
|
|
||||||
*addr = save[--i];
|
|
||||||
}
|
|
||||||
/* Write the actual size to ORx
|
|
||||||
*/
|
|
||||||
*orx_ptr = orx | ~(size - 1);
|
*orx_ptr = orx | ~(size - 1);
|
||||||
|
|
||||||
return (size);
|
return (size);
|
||||||
}
|
}
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
|
||||||
|
|
||||||
long int initdram (int board_type)
|
long int initdram (int board_type)
|
||||||
{
|
{
|
||||||
|
|
|
@ -398,55 +398,10 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize
|
||||||
{
|
{
|
||||||
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
||||||
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
volatile memctl8xx_t *memctl = &immap->im_memctl;
|
||||||
volatile long int *addr;
|
|
||||||
ulong cnt, val, size;
|
|
||||||
ulong save[32]; /* to make test non-destructive */
|
|
||||||
unsigned char i = 0;
|
|
||||||
|
|
||||||
memctl->memc_mamr = mamr_value;
|
memctl->memc_mamr = mamr_value;
|
||||||
|
|
||||||
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
|
return (get_ram_size(base, maxsize));
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
save[i++] = *addr;
|
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* write 0 to base address */
|
|
||||||
addr = base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
/* check at base address */
|
|
||||||
if ((val = *addr) != 0) {
|
|
||||||
/* Restore the original data before leaving the function.
|
|
||||||
*/
|
|
||||||
*addr = save[i];
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt;
|
|
||||||
*addr = save[--i];
|
|
||||||
}
|
|
||||||
return (0);
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = base + cnt; /* pointer arith! */
|
|
||||||
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
|
|
||||||
if (val != (~cnt)) {
|
|
||||||
size = cnt * sizeof (long);
|
|
||||||
/* Restore the original data before returning
|
|
||||||
*/
|
|
||||||
for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *) base + cnt;
|
|
||||||
*addr = save[--i];
|
|
||||||
}
|
|
||||||
return (size);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (maxsize);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/* ------------------------------------------------------------------------- */
|
/* ------------------------------------------------------------------------- */
|
||||||
|
|
|
@ -49,11 +49,10 @@ int checkboard(void)
|
||||||
long int initdram(int board_type)
|
long int initdram(int board_type)
|
||||||
{
|
{
|
||||||
#if 1
|
#if 1
|
||||||
int i, cnt;
|
long size;
|
||||||
volatile uchar *base = CFG_SDRAM_BASE;
|
long new_bank0_end;
|
||||||
volatile ulong *addr;
|
long mear1;
|
||||||
ulong save[SAVE_SZ];
|
long emear1;
|
||||||
ulong val, ret = 0;
|
|
||||||
/*
|
/*
|
||||||
write_bat(IBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP),
|
write_bat(IBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP),
|
||||||
( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE));
|
( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE));
|
||||||
|
@ -61,33 +60,11 @@ long int initdram(int board_type)
|
||||||
write_bat(DBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP),
|
write_bat(DBAT1, ((CFG_MAX_RAM_SIZE/2) | BATU_BL_256M | BATU_VS | BATU_VP),
|
||||||
( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE));
|
( (CFG_MAX_RAM_SIZE/2)| BATL_PP_10 | BATL_MEMCOHERENCE));
|
||||||
*/
|
*/
|
||||||
for (i=0; i<SAVE_SZ; i++) {
|
size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
|
||||||
save[i] = 0; /* clear table */
|
|
||||||
}
|
|
||||||
|
|
||||||
for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
|
new_bank0_end = size - 1;
|
||||||
addr = (volatile ulong *)base + cnt;
|
mear1 = mpc824x_mpc107_getreg(MEAR1);
|
||||||
save[i++] = *addr;
|
emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
||||||
*addr = ~cnt;
|
|
||||||
}
|
|
||||||
|
|
||||||
addr = (volatile ulong *)base;
|
|
||||||
save[i] = *addr;
|
|
||||||
*addr = 0;
|
|
||||||
|
|
||||||
if (*addr != 0) {
|
|
||||||
*addr = save[i];
|
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
|
|
||||||
for (cnt = 1; cnt < CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
|
|
||||||
addr = (volatile ulong *)base + cnt;
|
|
||||||
val = *addr;
|
|
||||||
*addr = save[--i];
|
|
||||||
if (val != ~cnt) {
|
|
||||||
ulong new_bank0_end = cnt * sizeof(long) - 1;
|
|
||||||
ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
|
|
||||||
ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
|
|
||||||
mear1 = (mear1 & 0xFFFFFF00) |
|
mear1 = (mear1 & 0xFFFFFF00) |
|
||||||
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
|
||||||
emear1 = (emear1 & 0xFFFFFF00) |
|
emear1 = (emear1 & 0xFFFFFF00) |
|
||||||
|
@ -95,14 +72,7 @@ long int initdram(int board_type)
|
||||||
mpc824x_mpc107_setreg(MEAR1, mear1);
|
mpc824x_mpc107_setreg(MEAR1, mear1);
|
||||||
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
mpc824x_mpc107_setreg(EMEAR1, emear1);
|
||||||
|
|
||||||
ret = cnt * sizeof(long);
|
return (size);
|
||||||
goto Done;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
ret = CFG_MAX_RAM_SIZE;
|
|
||||||
Done:
|
|
||||||
return ret;
|
|
||||||
#else
|
#else
|
||||||
return (CFG_MAX_RAM_SIZE);
|
return (CFG_MAX_RAM_SIZE);
|
||||||
#endif
|
#endif
|
||||||
|
|
|
@ -140,8 +140,7 @@ int checkboard (void)
|
||||||
(strncmp (vpd.productId, "CMM", 3) == 0))) {
|
(strncmp (vpd.productId, "CMM", 3) == 0))) {
|
||||||
|
|
||||||
/* Output board information on startup */
|
/* Output board information on startup */
|
||||||
printf("\"%s\", revision '%c', serial# %ld, manufacturer %u\n",
|
printf ("\"%s\", revision '%c', serial# %ld, manufacturer %u\n", vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
|
||||||
vpd.productId, vpd.revisionId, vpd.serialNum, vpd.manuID);
|
|
||||||
return (0);
|
return (0);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
@ -192,8 +191,7 @@ int misc_init_f (void)
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
static void
|
static void w7o_env_init (VPD * vpd)
|
||||||
w7o_env_init(VPD *vpd)
|
|
||||||
{
|
{
|
||||||
/*
|
/*
|
||||||
* Read VPD
|
* Read VPD
|
||||||
|
@ -214,16 +212,19 @@ w7o_env_init(VPD *vpd)
|
||||||
|
|
||||||
/* Set 'serial#' envvar if serial# isn't set */
|
/* Set 'serial#' envvar if serial# isn't set */
|
||||||
if (!serial) {
|
if (!serial) {
|
||||||
sprintf(buf, "%s-%ld", vpd->productId, vpd->serialNum);
|
sprintf (buf, "%s-%ld", vpd->productId,
|
||||||
|
vpd->serialNum);
|
||||||
setenv ("serial#", buf);
|
setenv ("serial#", buf);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
|
/* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
|
||||||
eth = vpd->ethAddrs[0];
|
eth = vpd->ethAddrs[0];
|
||||||
if (ethaddr && (strcmp(ethaddr, MK_STR(CONFIG_ETHADDR)) == 0)) {
|
if (ethaddr
|
||||||
|
&& (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) {
|
||||||
/* Now setup ethaddr */
|
/* Now setup ethaddr */
|
||||||
sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
|
sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
|
||||||
eth[0], eth[1], eth[2], eth[3], eth[4], eth[5]);
|
eth[0], eth[1], eth[2], eth[3], eth[4],
|
||||||
|
eth[5]);
|
||||||
setenv ("ethaddr", buf);
|
setenv ("ethaddr", buf);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
|
@ -47,7 +47,7 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o \
|
||||||
hush.o kgdb.o lists.o lynxkdi.o miiphybb.o miiphyutil.o \
|
hush.o kgdb.o lists.o lynxkdi.o miiphybb.o miiphyutil.o \
|
||||||
s_record.o soft_i2c.o soft_spi.o spartan2.o \
|
s_record.o soft_i2c.o soft_spi.o spartan2.o \
|
||||||
usb.o usb_kbd.o usb_storage.o \
|
usb.o usb_kbd.o usb_storage.o \
|
||||||
virtex2.o xilinx.o
|
virtex2.o xilinx.o memsize.o
|
||||||
|
|
||||||
OBJS = $(AOBJS) $(COBJS)
|
OBJS = $(AOBJS) $(COBJS)
|
||||||
|
|
||||||
|
|
77
common/memsize.c
Normal file
77
common/memsize.c
Normal file
|
@ -0,0 +1,77 @@
|
||||||
|
/*
|
||||||
|
* (C) Copyright 2004
|
||||||
|
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||||
|
*
|
||||||
|
* See file CREDITS for list of people who contributed to this
|
||||||
|
* project.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or
|
||||||
|
* modify it under the terms of the GNU General Public License as
|
||||||
|
* published by the Free Software Foundation; either version 2 of
|
||||||
|
* the License, or (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||||
|
* MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Check memory range for valid RAM. A simple memory test determines
|
||||||
|
* the actually available RAM size between addresses `base' and
|
||||||
|
* `base + maxsize'.
|
||||||
|
*/
|
||||||
|
long get_ram_size(volatile long *base, long maxsize)
|
||||||
|
{
|
||||||
|
volatile long *addr;
|
||||||
|
long save[32];
|
||||||
|
long cnt;
|
||||||
|
long val;
|
||||||
|
long size;
|
||||||
|
int i = 0;
|
||||||
|
|
||||||
|
for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) {
|
||||||
|
addr = base + cnt; /* pointer arith! */
|
||||||
|
save[i++] = *addr;
|
||||||
|
*addr = ~cnt;
|
||||||
|
}
|
||||||
|
|
||||||
|
addr = base;
|
||||||
|
save[i] = *addr;
|
||||||
|
*addr = 0;
|
||||||
|
|
||||||
|
if ((val = *addr) != 0) {
|
||||||
|
/* Restore the original data before leaving the function.
|
||||||
|
*/
|
||||||
|
*addr = save[i];
|
||||||
|
for (cnt = 1; cnt < maxsize / sizeof(long); cnt <<= 1) {
|
||||||
|
addr = base + cnt;
|
||||||
|
*addr = save[--i];
|
||||||
|
}
|
||||||
|
return (0);
|
||||||
|
}
|
||||||
|
|
||||||
|
for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
|
||||||
|
addr = base + cnt; /* pointer arith! */
|
||||||
|
val = *addr;
|
||||||
|
*addr = save[--i];
|
||||||
|
if (val != ~cnt) {
|
||||||
|
size = cnt * sizeof (long);
|
||||||
|
/* Restore the original data before leaving the function.
|
||||||
|
*/
|
||||||
|
for (cnt <<= 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
|
||||||
|
addr = base + cnt;
|
||||||
|
*addr = save[--i];
|
||||||
|
}
|
||||||
|
return (size);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return (maxsize);
|
||||||
|
}
|
|
@ -219,6 +219,9 @@ int misc_init_r (void);
|
||||||
/* common/exports.c */
|
/* common/exports.c */
|
||||||
void jumptable_init(void);
|
void jumptable_init(void);
|
||||||
|
|
||||||
|
/* common/memsize.c */
|
||||||
|
int get_ram_size (volatile long *, long);
|
||||||
|
|
||||||
/* $(BOARD)/$(BOARD).c */
|
/* $(BOARD)/$(BOARD).c */
|
||||||
void reset_phy (void);
|
void reset_phy (void);
|
||||||
void fdc_hw_init (void);
|
void fdc_hw_init (void);
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
#ifndef __MON_SYS_CALL_H__
|
#ifndef __EXPORTS_H__
|
||||||
#define __MON_SYS_CALL_H__
|
#define __EXPORTS_H__
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
#ifndef __ASSEMBLY__
|
||||||
|
|
||||||
|
@ -43,4 +43,4 @@ enum {
|
||||||
extern gd_t *global_data;
|
extern gd_t *global_data;
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#endif
|
#endif /* __EXPORTS_H__ */
|
||||||
|
|
|
@ -24,6 +24,6 @@
|
||||||
#ifndef __VERSION_H__
|
#ifndef __VERSION_H__
|
||||||
#define __VERSION_H__
|
#define __VERSION_H__
|
||||||
|
|
||||||
#define U_BOOT_VERSION "U-Boot 1.0.1"
|
#define U_BOOT_VERSION "U-Boot 1.0.2"
|
||||||
|
|
||||||
#endif /* __VERSION_H__ */
|
#endif /* __VERSION_H__ */
|
||||||
|
|
Loading…
Reference in a new issue