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Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig

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This converts the following to Kconfig:
   CONFIG_SYS_BR0_PRELIM
   CONFIG_SYS_OR1_PRELIM
   CONFIG_SYS_BR1_PRELIM
   CONFIG_SYS_OR2_PRELIM
   CONFIG_SYS_BR2_PRELIM
   CONFIG_SYS_OR2_PRELIM
   CONFIG_SYS_BR3_PRELIM
   CONFIG_SYS_OR3_PRELIM
   CONFIG_SYS_BR4_PRELIM
   CONFIG_SYS_OR4_PRELIM
   CONFIG_SYS_BR5_PRELIM
   CONFIG_SYS_OR5_PRELIM
   CONFIG_SYS_BR6_PRELIM
   CONFIG_SYS_OR6_PRELIM
   CONFIG_SYS_BR7_PRELIM
   CONFIG_SYS_OR7_PRELIM

This also introduces CONFIG_SYS_BR0_PRELIM_BOOL as not all platforms
that can set these values do so.  Add the relevant SYS_BRx_PRELIM_BOOL
to platforms that had not been previously migrated.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-11-13 18:10:40 -05:00
parent 970bf8603b
commit c7fad78ec0
66 changed files with 653 additions and 440 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

11
README
View file

@ -2554,17 +2554,6 @@ Low Level (hardware related) configuration options:
- CONFIG_SYS_MAMR_PTA:
periodic timer for refresh
- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
CONFIG_SYS_BR1_PRELIM:
Memory Controller Definitions: BR0/1 and OR0/1 (FLASH)
- SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE,
CONFIG_SYS_OR_TIMING_SDRAM, CONFIG_SYS_OR2_PRELIM, CONFIG_SYS_BR2_PRELIM,
CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
- CONFIG_SYS_SRIO:
Chip has SRIO or not

170
arch/powerpc/cpu/mpc83xx/elbc/elbc.h
View file

@ -1,173 +1,3 @@
#ifdef CONFIG_ELBC_BR0_OR0
#define CONFIG_SYS_BR0_PRELIM (\
CONFIG_BR0_OR0_BASE |\
CONFIG_BR0_PORTSIZE |\
CONFIG_BR0_ERRORCHECKING |\
CONFIG_BR0_WRITE_PROTECT_BIT |\
CONFIG_BR0_MACHINE |\
CONFIG_BR0_ATOMIC |\
CONFIG_BR0_VALID_BIT \
)
#define CONFIG_SYS_OR0_PRELIM (\
CONFIG_OR0_AM |\
CONFIG_OR0_XAM |\
CONFIG_OR0_BCTLD |\
CONFIG_OR0_BI |\
CONFIG_OR0_COLS |\
CONFIG_OR0_ROWS |\
CONFIG_OR0_PMSEL |\
CONFIG_OR0_SCY |\
CONFIG_OR0_PGS |\
CONFIG_OR0_CSCT |\
CONFIG_OR0_CST |\
CONFIG_OR0_CHT |\
CONFIG_OR0_RST |\
CONFIG_OR0_CSNT |\
CONFIG_OR0_ACS |\
CONFIG_OR0_XACS |\
CONFIG_OR0_SETA |\
CONFIG_OR0_TRLX |\
CONFIG_OR0_EHTR |\
CONFIG_OR0_EAD \
)
#endif /* CONFIG_ELBC_BR0_OR0 */
#ifdef CONFIG_ELBC_BR1_OR1
#define CONFIG_SYS_BR1_PRELIM (\
CONFIG_BR1_OR1_BASE |\
CONFIG_BR1_PORTSIZE |\
CONFIG_BR1_ERRORCHECKING |\
CONFIG_BR1_WRITE_PROTECT_BIT |\
CONFIG_BR1_MACHINE |\
CONFIG_BR1_ATOMIC |\
CONFIG_BR1_VALID_BIT \
)
#define CONFIG_SYS_OR1_PRELIM (\
CONFIG_OR1_AM |\
CONFIG_OR1_XAM |\
CONFIG_OR1_BCTLD |\
CONFIG_OR1_BI |\
CONFIG_OR1_COLS |\
CONFIG_OR1_ROWS |\
CONFIG_OR1_PMSEL |\
CONFIG_OR1_SCY |\
CONFIG_OR1_PGS |\
CONFIG_OR1_CSCT |\
CONFIG_OR1_CST |\
CONFIG_OR1_CHT |\
CONFIG_OR1_RST |\
CONFIG_OR1_CSNT |\
CONFIG_OR1_ACS |\
CONFIG_OR1_XACS |\
CONFIG_OR1_SETA |\
CONFIG_OR1_TRLX |\
CONFIG_OR1_EHTR |\
CONFIG_OR1_EAD \
)
#endif /* CONFIG_ELBC_BR1_OR1 */
#ifdef CONFIG_ELBC_BR2_OR2
#define CONFIG_SYS_BR2_PRELIM (\
CONFIG_BR2_OR2_BASE |\
CONFIG_BR2_PORTSIZE |\
CONFIG_BR2_ERRORCHECKING |\
CONFIG_BR2_WRITE_PROTECT_BIT |\
CONFIG_BR2_MACHINE |\
CONFIG_BR2_ATOMIC |\
CONFIG_BR2_VALID_BIT \
)
#define CONFIG_SYS_OR2_PRELIM (\
CONFIG_OR2_AM |\
CONFIG_OR2_XAM |\
CONFIG_OR2_BCTLD |\
CONFIG_OR2_BI |\
CONFIG_OR2_COLS |\
CONFIG_OR2_ROWS |\
CONFIG_OR2_PMSEL |\
CONFIG_OR2_SCY |\
CONFIG_OR2_PGS |\
CONFIG_OR2_CSCT |\
CONFIG_OR2_CST |\
CONFIG_OR2_CHT |\
CONFIG_OR2_RST |\
CONFIG_OR2_CSNT |\
CONFIG_OR2_ACS |\
CONFIG_OR2_XACS |\
CONFIG_OR2_SETA |\
CONFIG_OR2_TRLX |\
CONFIG_OR2_EHTR |\
CONFIG_OR2_EAD \
)
#endif /* CONFIG_ELBC_BR2_OR2 */
#ifdef CONFIG_ELBC_BR3_OR3
#define CONFIG_SYS_BR3_PRELIM (\
CONFIG_BR3_OR3_BASE |\
CONFIG_BR3_PORTSIZE |\
CONFIG_BR3_ERRORCHECKING |\
CONFIG_BR3_WRITE_PROTECT_BIT |\
CONFIG_BR3_MACHINE |\
CONFIG_BR3_ATOMIC |\
CONFIG_BR3_VALID_BIT \
)
#define CONFIG_SYS_OR3_PRELIM (\
CONFIG_OR3_AM |\
CONFIG_OR3_XAM |\
CONFIG_OR3_BCTLD |\
CONFIG_OR3_BI |\
CONFIG_OR3_COLS |\
CONFIG_OR3_ROWS |\
CONFIG_OR3_PMSEL |\
CONFIG_OR3_SCY |\
CONFIG_OR3_PGS |\
CONFIG_OR3_CSCT |\
CONFIG_OR3_CST |\
CONFIG_OR3_CHT |\
CONFIG_OR3_RST |\
CONFIG_OR3_CSNT |\
CONFIG_OR3_ACS |\
CONFIG_OR3_XACS |\
CONFIG_OR3_SETA |\
CONFIG_OR3_TRLX |\
CONFIG_OR3_EHTR |\
CONFIG_OR3_EAD \
)
#endif /* CONFIG_ELBC_BR3_OR3 */
#ifdef CONFIG_ELBC_BR4_OR4
#define CONFIG_SYS_BR4_PRELIM (\
CONFIG_BR4_OR4_BASE |\
CONFIG_BR4_PORTSIZE |\
CONFIG_BR4_ERRORCHECKING |\
CONFIG_BR4_WRITE_PROTECT_BIT |\
CONFIG_BR4_MACHINE |\
CONFIG_BR4_ATOMIC |\
CONFIG_BR4_VALID_BIT \
)
#define CONFIG_SYS_OR4_PRELIM (\
CONFIG_OR4_AM |\
CONFIG_OR4_XAM |\
CONFIG_OR4_BCTLD |\
CONFIG_OR4_BI |\
CONFIG_OR4_COLS |\
CONFIG_OR4_ROWS |\
CONFIG_OR4_PMSEL |\
CONFIG_OR4_SCY |\
CONFIG_OR4_PGS |\
CONFIG_OR4_CSCT |\
CONFIG_OR4_CST |\
CONFIG_OR4_CHT |\
CONFIG_OR4_RST |\
CONFIG_OR4_CSNT |\
CONFIG_OR4_ACS |\
CONFIG_OR4_XACS |\
CONFIG_OR4_SETA |\
CONFIG_OR4_TRLX |\
CONFIG_OR4_EHTR |\
CONFIG_OR4_EAD \
)
#endif /* CONFIG_ELBC_BR4_OR4 */
#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0)
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM

85
arch/powerpc/cpu/mpc8xx/Kconfig
View file

@ -84,91 +84,6 @@ config SYS_DER
help
Debug Event Register (37-47)
comment "Memory mapping"
config SYS_BR0_PRELIM
hex "Preliminary value for BR0"
config SYS_OR0_PRELIM
hex "Preliminary value for OR0"
config SYS_BR1_PRELIM_BOOL
bool "Define Bank 1"
config SYS_BR1_PRELIM
hex "Preliminary value for BR1"
depends on SYS_BR1_PRELIM_BOOL
config SYS_OR1_PRELIM
hex "Preliminary value for OR1"
depends on SYS_BR1_PRELIM_BOOL
config SYS_BR2_PRELIM_BOOL
bool "Define Bank 2"
config SYS_BR2_PRELIM
hex "Preliminary value for BR2"
depends on SYS_BR2_PRELIM_BOOL
config SYS_OR2_PRELIM
hex "Preliminary value for OR2"
depends on SYS_BR2_PRELIM_BOOL
config SYS_BR3_PRELIM_BOOL
bool "Define Bank 3"
config SYS_BR3_PRELIM
hex "Preliminary value for BR3"
depends on SYS_BR3_PRELIM_BOOL
config SYS_OR3_PRELIM
hex "Preliminary value for OR3"
depends on SYS_BR3_PRELIM_BOOL
config SYS_BR4_PRELIM_BOOL
bool "Define Bank 4"
config SYS_BR4_PRELIM
hex "Preliminary value for BR4"
depends on SYS_BR4_PRELIM_BOOL
config SYS_OR4_PRELIM
hex "Preliminary value for OR4"
depends on SYS_BR4_PRELIM_BOOL
config SYS_BR5_PRELIM_BOOL
bool "Define Bank 5"
config SYS_BR5_PRELIM
hex "Preliminary value for BR5"
depends on SYS_BR5_PRELIM_BOOL
config SYS_OR5_PRELIM
hex "Preliminary value for OR5"
depends on SYS_BR5_PRELIM_BOOL
config SYS_BR6_PRELIM_BOOL
bool "Define Bank 6"
config SYS_BR6_PRELIM
hex "Preliminary value for BR6"
depends on SYS_BR6_PRELIM_BOOL
config SYS_OR6_PRELIM
hex "Preliminary value for OR6"
depends on SYS_BR6_PRELIM_BOOL
config SYS_BR7_PRELIM_BOOL
bool "Define Bank 7"
config SYS_BR7_PRELIM
hex "Preliminary value for BR7"
depends on SYS_BR7_PRELIM_BOOL
config SYS_OR7_PRELIM
hex "Preliminary value for OR7"
depends on SYS_BR7_PRELIM_BOOL
config SYS_IMMR
hex "Value for IMMR"

24
configs/M5272C3_defconfig
View file

@ -20,6 +20,30 @@ CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFFE00201
CONFIG_SYS_OR0_PRELIM=0xFFE00014
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0x0
CONFIG_SYS_OR1_PRELIM=0x0
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0x30000001
CONFIG_SYS_OR2_PRELIM=0xFFF80000
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0x0
CONFIG_SYS_OR3_PRELIM=0x0
CONFIG_SYS_BR4_PRELIM_BOOL=y
CONFIG_SYS_BR4_PRELIM=0x0
CONFIG_SYS_OR4_PRELIM=0x0
CONFIG_SYS_BR5_PRELIM_BOOL=y
CONFIG_SYS_BR5_PRELIM=0x0
CONFIG_SYS_OR5_PRELIM=0x0
CONFIG_SYS_BR6_PRELIM_BOOL=y
CONFIG_SYS_BR6_PRELIM=0x0
CONFIG_SYS_OR6_PRELIM=0x0
CONFIG_SYS_BR7_PRELIM_BOOL=y
CONFIG_SYS_BR7_PRELIM=0x701
CONFIG_SYS_OR7_PRELIM=0xFFC0007C
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y

47
configs/MCR3000_defconfig
View file

@ -17,29 +17,6 @@ CONFIG_SYS_PLPRCR=0x00460004
CONFIG_SYS_SCCR=0x00C20000
CONFIG_SYS_SCCR_MASK=0x60000000
CONFIG_SYS_DER=0x2002000F
CONFIG_SYS_BR0_PRELIM=0x04000801
CONFIG_SYS_OR0_PRELIM=0xFFC00926
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0x00000081
CONFIG_SYS_OR1_PRELIM=0xFE000E00
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0x08000801
CONFIG_SYS_OR2_PRELIM=0xFFFF8F2A
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0x0C000401
CONFIG_SYS_OR3_PRELIM=0xFFFF8142
CONFIG_SYS_BR4_PRELIM_BOOL=y
CONFIG_SYS_BR4_PRELIM=0x10000801
CONFIG_SYS_OR4_PRELIM=0xFFFF8D08
CONFIG_SYS_BR5_PRELIM_BOOL=y
CONFIG_SYS_BR5_PRELIM=0x14000801
CONFIG_SYS_OR5_PRELIM=0xFFFF8916
CONFIG_SYS_BR6_PRELIM_BOOL=y
CONFIG_SYS_BR6_PRELIM=0x18000801
CONFIG_SYS_OR6_PRELIM=0xFFFF0908
CONFIG_SYS_BR7_PRELIM_BOOL=y
CONFIG_SYS_BR7_PRELIM=0x1C000001
CONFIG_SYS_OR7_PRELIM=0xFFFF810A
CONFIG_SYS_LOAD_ADDR=0x200000
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
@ -74,6 +51,30 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0x4004000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0x4000801
CONFIG_SYS_OR0_PRELIM=0xFFC00926
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0x81
CONFIG_SYS_OR1_PRELIM=0xFE000E00
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0x8000801
CONFIG_SYS_OR2_PRELIM=0xFFFF8F2A
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xC000401
CONFIG_SYS_OR3_PRELIM=0xFFFF8142
CONFIG_SYS_BR4_PRELIM_BOOL=y
CONFIG_SYS_BR4_PRELIM=0x10000801
CONFIG_SYS_OR4_PRELIM=0xFFFF8D08
CONFIG_SYS_BR5_PRELIM_BOOL=y
CONFIG_SYS_BR5_PRELIM=0x14000801
CONFIG_SYS_OR5_PRELIM=0xFFFF8916
CONFIG_SYS_BR6_PRELIM_BOOL=y
CONFIG_SYS_BR6_PRELIM=0x18000801
CONFIG_SYS_OR6_PRELIM=0xFFFF0908
CONFIG_SYS_BR7_PRELIM_BOOL=y
CONFIG_SYS_BR7_PRELIM=0x1C000001
CONFIG_SYS_OR7_PRELIM=0xFFFF810A
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y

9
configs/MPC837XERDB_defconfig
View file

@ -169,6 +169,15 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_ADDR=0xFE080000
CONFIG_DM=y
CONFIG_FSL_SATA=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFE001001
CONFIG_SYS_OR0_PRELIM=0xFF800193
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE0600C21
CONFIG_SYS_OR1_PRELIM=0xFFFF8396
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xF0000801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000

12
configs/MPC8548CDS_36BIT_defconfig
View file

@ -31,6 +31,18 @@ CONFIG_ENV_ADDR=0xFFF60000
CONFIG_DM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF807001
CONFIG_SYS_OR0_PRELIM=0xFF806E65
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xFF007001
CONFIG_SYS_OR1_PRELIM=0xFF806E65
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xF0007861
CONFIG_SYS_OR2_PRELIM=0xFC006901
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xF8006801
CONFIG_SYS_OR3_PRELIM=0xFFF00FF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

12
configs/MPC8548CDS_defconfig
View file

@ -30,6 +30,18 @@ CONFIG_ENV_ADDR=0xFFF60000
CONFIG_DM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF801001
CONFIG_SYS_OR0_PRELIM=0xFF806E65
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xFF001001
CONFIG_SYS_OR1_PRELIM=0xFF806E65
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xF0001861
CONFIG_SYS_OR2_PRELIM=0xFC006901
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xF8000801
CONFIG_SYS_OR3_PRELIM=0xFFF00FF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

12
configs/MPC8548CDS_legacy_defconfig
View file

@ -30,6 +30,18 @@ CONFIG_ENV_ADDR=0xFFF60000
CONFIG_DM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF801001
CONFIG_SYS_OR0_PRELIM=0xFF806E65
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xFF001001
CONFIG_SYS_OR1_PRELIM=0xFF806E65
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xF0001861
CONFIG_SYS_OR2_PRELIM=0xFC006901
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xF8000801
CONFIG_SYS_OR3_PRELIM=0xFFF00FF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

12
configs/P1020RDB-PC_36BIT_NAND_defconfig
View file

@ -54,6 +54,18 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21
CONFIG_SYS_OR0_PRELIM=0xFFFF8396
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xEF001001
CONFIG_SYS_OR1_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y

9
configs/P1020RDB-PC_36BIT_SDCARD_defconfig
View file

@ -50,6 +50,15 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

9
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
View file

@ -52,6 +52,15 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

9
configs/P1020RDB-PC_36BIT_defconfig
View file

@ -39,6 +39,15 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

12
configs/P1020RDB-PC_NAND_defconfig
View file

@ -53,6 +53,18 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21
CONFIG_SYS_OR0_PRELIM=0xFFFF8396
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xEF001001
CONFIG_SYS_OR1_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y

9
configs/P1020RDB-PC_SDCARD_defconfig
View file

@ -49,6 +49,15 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

9
configs/P1020RDB-PC_SPIFLASH_defconfig
View file

@ -51,6 +51,15 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

9
configs/P1020RDB-PC_defconfig
View file

@ -38,6 +38,15 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

12
configs/P1020RDB-PD_NAND_defconfig
View file

@ -56,6 +56,18 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21
CONFIG_SYS_OR0_PRELIM=0xFFFF8796
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xEC001001
CONFIG_SYS_OR1_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y

9
configs/P1020RDB-PD_SDCARD_defconfig
View file

@ -52,6 +52,15 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEC001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

9
configs/P1020RDB-PD_SPIFLASH_defconfig
View file

@ -54,6 +54,15 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEC001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

9
configs/P1020RDB-PD_defconfig
View file

@ -41,6 +41,15 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEC001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

12
configs/P2020RDB-PC_36BIT_NAND_defconfig
View file

@ -58,6 +58,18 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21
CONFIG_SYS_OR0_PRELIM=0xFFFF8396
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xEF001001
CONFIG_SYS_OR1_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y

9
configs/P2020RDB-PC_36BIT_SDCARD_defconfig
View file

@ -54,6 +54,15 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

9
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
View file

@ -56,6 +56,15 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

9
configs/P2020RDB-PC_36BIT_defconfig
View file

@ -43,6 +43,15 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

12
configs/P2020RDB-PC_NAND_defconfig
View file

@ -57,6 +57,18 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800C21
CONFIG_SYS_OR0_PRELIM=0xFFFF8396
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xEF001001
CONFIG_SYS_OR1_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y

9
configs/P2020RDB-PC_SDCARD_defconfig
View file

@ -53,6 +53,15 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

9
configs/P2020RDB-PC_SPIFLASH_defconfig
View file

@ -55,6 +55,15 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

9
configs/P2020RDB-PC_defconfig
View file

@ -42,6 +42,15 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xEF001001
CONFIG_SYS_OR0_PRELIM=0xFC000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xFFB00801
CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFA00801
CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y

9
configs/P2041RDB_NAND_defconfig
View file

@ -40,6 +40,15 @@ CONFIG_ENV_IS_IN_NAND=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFFA00C21
CONFIG_SYS_OR0_PRELIM=0xFFFC0796
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE8001001
CONFIG_SYS_OR1_PRELIM=0xF8000F85
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFDF0801
CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

6
configs/P2041RDB_SDCARD_defconfig
View file

@ -41,6 +41,12 @@ CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_SYS_OR0_PRELIM=0xF8000F85
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFDF0801
CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

6
configs/P2041RDB_SPIFLASH_defconfig
View file

@ -42,6 +42,12 @@ CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_SYS_OR0_PRELIM=0xF8000F85
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFDF0801
CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

6
configs/P2041RDB_defconfig
View file

@ -37,6 +37,12 @@ CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xEFF20000
CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_SYS_OR0_PRELIM=0xF8000F85
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFDF0801
CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

12
configs/P3041DS_NAND_defconfig
View file

@ -40,6 +40,18 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFFA00C21
CONFIG_SYS_OR0_PRELIM=0xFFFC0796
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE0001001
CONFIG_SYS_OR1_PRELIM=0xF8000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xE8001001
CONFIG_SYS_OR2_PRELIM=0xF8000F85
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFDF0801
CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

9
configs/P3041DS_SDCARD_defconfig
View file

@ -41,6 +41,15 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_SYS_OR0_PRELIM=0xF8000F85
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE0001001
CONFIG_SYS_OR1_PRELIM=0xF8000FF7
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFDF0801
CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

9
configs/P3041DS_SPIFLASH_defconfig
View file

@ -42,6 +42,15 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_SYS_OR0_PRELIM=0xF8000F85
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE0001001
CONFIG_SYS_OR1_PRELIM=0xF8000FF7
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFDF0801
CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

9
configs/P3041DS_defconfig
View file

@ -37,6 +37,15 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_SYS_OR0_PRELIM=0xF8000F85
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE0001001
CONFIG_SYS_OR1_PRELIM=0xF8000FF7
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFDF0801
CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

9
configs/P4080DS_SDCARD_defconfig
View file

@ -41,6 +41,15 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_SYS_OR0_PRELIM=0xF8000F85
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE0001001
CONFIG_SYS_OR1_PRELIM=0xF8000FF7
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFDF0801
CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

9
configs/P4080DS_SPIFLASH_defconfig
View file

@ -42,6 +42,15 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_SYS_OR0_PRELIM=0xF8000F85
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE0001001
CONFIG_SYS_OR1_PRELIM=0xF8000FF7
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFDF0801
CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

9
configs/P4080DS_defconfig
View file

@ -37,6 +37,15 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_SYS_OR0_PRELIM=0xF8000F85
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE0001001
CONFIG_SYS_OR1_PRELIM=0xF8000FF7
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFDF0801
CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

12
configs/P5040DS_NAND_defconfig
View file

@ -41,6 +41,18 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFFA00C21
CONFIG_SYS_OR0_PRELIM=0xFFFC0796
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE0001001
CONFIG_SYS_OR1_PRELIM=0xF8000FF7
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xE8001001
CONFIG_SYS_OR2_PRELIM=0xF8000F85
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFDF0801
CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

9
configs/P5040DS_SDCARD_defconfig
View file

@ -41,6 +41,15 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_SYS_OR0_PRELIM=0xF8000F85
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE0001001
CONFIG_SYS_OR1_PRELIM=0xF8000FF7
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFDF0801
CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

9
configs/P5040DS_SPIFLASH_defconfig
View file

@ -42,6 +42,15 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_SYS_OR0_PRELIM=0xF8000F85
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE0001001
CONFIG_SYS_OR1_PRELIM=0xF8000FF7
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFDF0801
CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

9
configs/P5040DS_defconfig
View file

@ -37,6 +37,15 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xE8001001
CONFIG_SYS_OR0_PRELIM=0xF8000F85
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE0001001
CONFIG_SYS_OR1_PRELIM=0xF8000FF7
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xFFDF0801
CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y

24
configs/cobra5272_defconfig
View file

@ -18,6 +18,30 @@ CONFIG_CMD_IMLS=y
CONFIG_CMD_PING=y
CONFIG_ENV_ADDR=0xFFE04000
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFFE00201
CONFIG_SYS_OR0_PRELIM=0xFFE00014
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0x0
CONFIG_SYS_OR1_PRELIM=0x0
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0x0
CONFIG_SYS_OR2_PRELIM=0x0
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0x0
CONFIG_SYS_OR3_PRELIM=0x0
CONFIG_SYS_BR4_PRELIM_BOOL=y
CONFIG_SYS_BR4_PRELIM=0x0
CONFIG_SYS_OR4_PRELIM=0x0
CONFIG_SYS_BR5_PRELIM_BOOL=y
CONFIG_SYS_BR5_PRELIM=0x0
CONFIG_SYS_OR5_PRELIM=0x0
CONFIG_SYS_BR6_PRELIM_BOOL=y
CONFIG_SYS_BR6_PRELIM=0x0
CONFIG_SYS_OR6_PRELIM=0x0
CONFIG_SYS_BR7_PRELIM_BOOL=y
CONFIG_SYS_BR7_PRELIM=0x701
CONFIG_SYS_OR7_PRELIM=0xFF00007C
CONFIG_MTD_NOR_FLASH=y
CONFIG_DM_ETH=y
CONFIG_MCFFEC=y

9
configs/gazerbeam_defconfig
View file

@ -160,6 +160,15 @@ CONFIG_CLK=y
CONFIG_ICS8N3QV01=y
CONFIG_CPU=y
CONFIG_CPU_MPC83XX=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFE001001
CONFIG_SYS_OR0_PRELIM=0xFF800FF6
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE0601001
CONFIG_SYS_OR1_PRELIM=0xFFF00850
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xE0701001
CONFIG_SYS_OR2_PRELIM=0xFFF00850
CONFIG_DM_PCA953X=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y

12
configs/ids8313_defconfig
View file

@ -158,6 +158,18 @@ CONFIG_ENV_ADDR_REDUND=0xFFFE0000
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_I2C=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFF800801
CONFIG_SYS_OR0_PRELIM=0xFF8008A7
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE1000C21
CONFIG_SYS_OR1_PRELIM=0xFFFF87CE
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xE2000801
CONFIG_SYS_OR2_PRELIM=0xFFFE0C74
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xE3000801
CONFIG_SYS_OR3_PRELIM=0xFFFF8814
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3100

12
configs/kmcoge5ne_defconfig
View file

@ -193,6 +193,18 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xF0001001
CONFIG_SYS_OR0_PRELIM=0xF0000E55
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE8000801
CONFIG_SYS_OR1_PRELIM=0xFC000E25
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xA0000801
CONFIG_SYS_OR3_PRELIM=0xF0000E25
CONFIG_SYS_BR4_PRELIM_BOOL=y
CONFIG_SYS_BR4_PRELIM=0xB0000801
CONFIG_SYS_OR4_PRELIM=0xF0000E25
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000

9
configs/kmeter1_defconfig
View file

@ -163,6 +163,15 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xF0001001
CONFIG_SYS_OR0_PRELIM=0xF0000E55
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE8000801
CONFIG_SYS_OR1_PRELIM=0xFC000E25
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xA0000801
CONFIG_SYS_OR3_PRELIM=0xF0000E25
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000

12
configs/kmopti2_defconfig
View file

@ -174,6 +174,18 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xF0001001
CONFIG_SYS_OR0_PRELIM=0xF0000E55
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE8000801
CONFIG_SYS_OR1_PRELIM=0xF8000E25
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xA0000801
CONFIG_SYS_OR2_PRELIM=0xF0000C25
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xB0001001
CONFIG_SYS_OR3_PRELIM=0xF0000040
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000

9
configs/kmsupx5_defconfig
View file

@ -153,6 +153,15 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xF0001001
CONFIG_SYS_OR0_PRELIM=0xF0000E55
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE8000801
CONFIG_SYS_OR1_PRELIM=0xF8000E25
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xA0000801
CONFIG_SYS_OR2_PRELIM=0xF0000C25
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000

9
configs/kmtegr1_defconfig
View file

@ -155,6 +155,15 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xF0001001
CONFIG_SYS_OR0_PRELIM=0xF0000E55
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE8000801
CONFIG_SYS_OR1_PRELIM=0xF8000E25
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xB0001001
CONFIG_SYS_OR3_PRELIM=0xF0000050
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000

12
configs/kmtepr2_defconfig
View file

@ -173,6 +173,18 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xF0001001
CONFIG_SYS_OR0_PRELIM=0xF0000E55
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE8000801
CONFIG_SYS_OR1_PRELIM=0xF8000E25
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xA0000801
CONFIG_SYS_OR2_PRELIM=0xF0000C25
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xB0001001
CONFIG_SYS_OR3_PRELIM=0xF0000040
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000

12
configs/socrates_defconfig
View file

@ -44,6 +44,18 @@ CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xFFF40000
CONFIG_ENV_ADDR_REDUND=0xFFF20000
CONFIG_DM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xFE001001
CONFIG_SYS_OR0_PRELIM=0xFE000030
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xFC001001
CONFIG_SYS_OR1_PRELIM=0xFE000030
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xC80018A1
CONFIG_SYS_OR2_PRELIM=0xFC000000
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xC0001881
CONFIG_SYS_OR3_PRELIM=0xFFF00000
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
# CONFIG_MMC is not set

9
configs/tuge1_defconfig
View file

@ -153,6 +153,15 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xF0001001
CONFIG_SYS_OR0_PRELIM=0xF0000E55
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE8000801
CONFIG_SYS_OR1_PRELIM=0xF8000E25
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xA0000801
CONFIG_SYS_OR2_PRELIM=0xF0000C25
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000

12
configs/tuxx1_defconfig
View file

@ -175,6 +175,18 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
CONFIG_SYS_BR0_PRELIM_BOOL=y
CONFIG_SYS_BR0_PRELIM=0xF0001001
CONFIG_SYS_OR0_PRELIM=0xF0000E55
CONFIG_SYS_BR1_PRELIM_BOOL=y
CONFIG_SYS_BR1_PRELIM=0xE8000801
CONFIG_SYS_OR1_PRELIM=0xF8000E25
CONFIG_SYS_BR2_PRELIM_BOOL=y
CONFIG_SYS_BR2_PRELIM=0xA0000801
CONFIG_SYS_OR2_PRELIM=0xF0000C25
CONFIG_SYS_BR3_PRELIM_BOOL=y
CONFIG_SYS_BR3_PRELIM=0xB0000801
CONFIG_SYS_OR3_PRELIM=0xF0000E24
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000

92
drivers/ddr/fsl/Kconfig
View file

@ -163,6 +163,98 @@ config ECC_INIT_VIA_DDRCONTROLLER
endif
menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
depends on MCF52x2 || MPC8xx || MPC83xx || MPC85xx
config SYS_BR0_PRELIM_BOOL
bool "Define Bank 0"
config SYS_BR0_PRELIM
hex "Preliminary value for BR0"
depends on SYS_BR0_PRELIM_BOOL
config SYS_OR0_PRELIM
hex "Preliminary value for OR0"
depends on SYS_BR0_PRELIM_BOOL
config SYS_BR1_PRELIM_BOOL
bool "Define Bank 1"
config SYS_BR1_PRELIM
hex "Preliminary value for BR1"
depends on SYS_BR1_PRELIM_BOOL
config SYS_OR1_PRELIM
hex "Preliminary value for OR1"
depends on SYS_BR1_PRELIM_BOOL
config SYS_BR2_PRELIM_BOOL
bool "Define Bank 2"
config SYS_BR2_PRELIM
hex "Preliminary value for BR2"
depends on SYS_BR2_PRELIM_BOOL
config SYS_OR2_PRELIM
hex "Preliminary value for OR2"
depends on SYS_BR2_PRELIM_BOOL
config SYS_BR3_PRELIM_BOOL
bool "Define Bank 3"
config SYS_BR3_PRELIM
hex "Preliminary value for BR3"
depends on SYS_BR3_PRELIM_BOOL
config SYS_OR3_PRELIM
hex "Preliminary value for OR3"
depends on SYS_BR3_PRELIM_BOOL
config SYS_BR4_PRELIM_BOOL
bool "Define Bank 4"
config SYS_BR4_PRELIM
hex "Preliminary value for BR4"
depends on SYS_BR4_PRELIM_BOOL
config SYS_OR4_PRELIM
hex "Preliminary value for OR4"
depends on SYS_BR4_PRELIM_BOOL
config SYS_BR5_PRELIM_BOOL
bool "Define Bank 5"
config SYS_BR5_PRELIM
hex "Preliminary value for BR5"
depends on SYS_BR5_PRELIM_BOOL
config SYS_OR5_PRELIM
hex "Preliminary value for OR5"
depends on SYS_BR5_PRELIM_BOOL
config SYS_BR6_PRELIM_BOOL
bool "Define Bank 6"
config SYS_BR6_PRELIM
hex "Preliminary value for BR6"
depends on SYS_BR6_PRELIM_BOOL
config SYS_OR6_PRELIM
hex "Preliminary value for OR6"
depends on SYS_BR6_PRELIM_BOOL
config SYS_BR7_PRELIM_BOOL
bool "Define Bank 7"
config SYS_BR7_PRELIM
hex "Preliminary value for BR7"
depends on SYS_BR7_PRELIM_BOOL
config SYS_OR7_PRELIM
hex "Preliminary value for OR7"
depends on SYS_BR7_PRELIM_BOOL
endmenu
config SYS_FSL_ERRATUM_A008378
bool

20
include/configs/M5272C3.h
View file

@ -145,26 +145,6 @@
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
/*-----------------------------------------------------------------------
* Memory bank definitions
*/
#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
#define CONFIG_SYS_BR1_PRELIM 0
#define CONFIG_SYS_OR1_PRELIM 0
#define CONFIG_SYS_BR2_PRELIM 0x30000001
#define CONFIG_SYS_OR2_PRELIM 0xFFF80000
#define CONFIG_SYS_BR3_PRELIM 0
#define CONFIG_SYS_OR3_PRELIM 0
#define CONFIG_SYS_BR4_PRELIM 0
#define CONFIG_SYS_OR4_PRELIM 0
#define CONFIG_SYS_BR5_PRELIM 0
#define CONFIG_SYS_OR5_PRELIM 0
#define CONFIG_SYS_BR6_PRELIM 0
#define CONFIG_SYS_OR6_PRELIM 0
#define CONFIG_SYS_BR7_PRELIM 0x00000701
#define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
/*-----------------------------------------------------------------------
* Port configuration
*/

8
include/configs/MPC8540ADS.h
View file

@ -90,9 +90,7 @@
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
@ -131,8 +129,6 @@
* FIXME: the top 17 bits of BR2.
*/
#define CONFIG_SYS_BR2_PRELIM 0xf0001861
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
@ -147,8 +143,6 @@
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
#define CONFIG_SYS_OR2_PRELIM 0xfc006901
#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
@ -176,8 +170,6 @@
/*
* 32KB, 8-bit wide for ADS config reg
*/
#define CONFIG_SYS_BR4_PRELIM 0xf8000801
#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
#define CONFIG_SYS_INIT_RAM_LOCK 1

17
include/configs/MPC8548CDS.h
View file

@ -134,14 +134,6 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#endif
#define CONFIG_SYS_BR0_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
#define CONFIG_SYS_BR1_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
#define CONFIG_SYS_OR0_PRELIM 0xff806e65
#define CONFIG_SYS_OR1_PRELIM 0xff806e65
#define CONFIG_SYS_FLASH_BANKS_LIST \
{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
@ -185,10 +177,6 @@ extern unsigned long get_clock_freq(void);
* FIXME: the top 17 bits of BR2.
*/
#define CONFIG_SYS_BR2_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
| BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
@ -203,8 +191,6 @@ extern unsigned long get_clock_freq(void);
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
#define CONFIG_SYS_OR2_PRELIM 0xfc006901
#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
@ -263,9 +249,6 @@ extern unsigned long get_clock_freq(void);
#else
#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
#endif
#define CONFIG_SYS_BR3_PRELIM \
(BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */

8
include/configs/MPC8560ADS.h
View file

@ -90,9 +90,7 @@
#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
@ -131,8 +129,6 @@
* FIXME: the top 17 bits of BR2.
*/
#define CONFIG_SYS_BR2_PRELIM 0xf0001861
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
@ -147,8 +143,6 @@
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
#define CONFIG_SYS_OR2_PRELIM 0xfc006901
#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
@ -176,8 +170,6 @@
/*
* 32KB, 8-bit wide for ADS config reg
*/
#define CONFIG_SYS_BR4_PRELIM 0xf8000801
#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
#define CONFIG_SYS_INIT_RAM_LOCK 1

18
include/configs/P2041RDB.h
View file

@ -137,9 +137,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
#define CPLD_BASE_PHYS CPLD_BASE
#endif
#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
#define PIXIS_LBMAP_SWITCH 7
#define PIXIS_LBMAP_MASK 0xf0
#define PIXIS_LBMAP_SHIFT 4
@ -185,21 +182,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#endif
#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
#endif /* CONFIG_NAND_FSL_ELBC */
#define CONFIG_SYS_FLASH_EMPTY_INFO

30
include/configs/cobra5272.h
View file

@ -245,36 +245,6 @@ enter a valid image address in flash */
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
/*-----------------------------------------------------------------------
* Memory bank definitions
*
* Please refer also to Motorola Coldfire user manual - Chapter XXX
* <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
*/
#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
#define CONFIG_SYS_BR1_PRELIM 0
#define CONFIG_SYS_OR1_PRELIM 0
#define CONFIG_SYS_BR2_PRELIM 0
#define CONFIG_SYS_OR2_PRELIM 0
#define CONFIG_SYS_BR3_PRELIM 0
#define CONFIG_SYS_OR3_PRELIM 0
#define CONFIG_SYS_BR4_PRELIM 0
#define CONFIG_SYS_OR4_PRELIM 0
#define CONFIG_SYS_BR5_PRELIM 0
#define CONFIG_SYS_OR5_PRELIM 0
#define CONFIG_SYS_BR6_PRELIM 0
#define CONFIG_SYS_OR6_PRELIM 0
#define CONFIG_SYS_BR7_PRELIM 0x00000701
#define CONFIG_SYS_OR7_PRELIM 0xFF00007C
/*-----------------------------------------------------------------------
* LED config
*/

22
include/configs/corenet_ds.h
View file

@ -128,10 +128,6 @@
#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
#define CONFIG_SYS_BR1_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
#ifdef CONFIG_PHYS_64BIT
#define PIXIS_BASE_PHYS 0xfffdf0000ull
@ -139,9 +135,6 @@
#define PIXIS_BASE_PHYS PIXIS_BASE
#endif
#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
#define PIXIS_LBMAP_SWITCH 7
#define PIXIS_LBMAP_MASK 0xf0
#define PIXIS_LBMAP_SHIFT 4
@ -187,21 +180,6 @@
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#endif
#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
#endif /* CONFIG_NAND_FSL_ELBC */
#define CONFIG_SYS_FLASH_EMPTY_INFO

19
include/configs/p1_p2_rdb_pc.h
View file

@ -352,22 +352,6 @@
OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
OR_GPCM_EAD)
#ifdef CONFIG_MTD_RAW_NAND
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#ifdef CONFIG_NAND_FSL_ELBC
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#endif
#endif
#define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
#define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
/* Vsc7385 switch */
#ifdef CONFIG_VSC7385_ENET
#define __VSCFW_ADDR "vscfw_addr=ef000000"
@ -385,9 +369,6 @@
OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
/* The size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE_SIZE 8192
#endif

9
include/configs/socrates.h
View file

@ -97,11 +97,6 @@
#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
@ -128,8 +123,6 @@
#define CONFIG_SYS_FPGA_BASE 0xc0000000
#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
#define CONFIG_SYS_HMI_BASE 0xc0010000
#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
@ -137,8 +130,6 @@
/* LIME GDC */
#define CONFIG_SYS_LIME_BASE 0xc8000000
#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
#define CONFIG_SYS_SPD_BUS_NUM 0