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board: axs10x: Flush entire cache after programming reset vector

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Now when we have support of IOC (IO-Coherency block) cahce operations
on regions are tuned to not be dummy stubs if IOC was found and enabled
in the core. That makes flush_dcache_range() useless for our purposes
here. And since we do need to flush modified reset vector to at least L2
cache (AKA SLC) so other cores will see it via its L1 instruction cache
we're using always functional flush_dcache_all() here.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Marek Vasut <marex@denx.de>
This commit is contained in:
Alexey Brodkin 2016-06-08 08:19:33 +03:00
parent a4a43fcf9c
commit c7d8db66ff
1 changed files with 1 additions and 1 deletions
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board/synopsys/axs101/axs101.c
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@ -54,7 +54,7 @@ void smp_set_core_boot_addr(unsigned long addr, int corenr)
writel(addr, (void __iomem *)RESET_VECTOR_ADDR); writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
/* Make sure other cores see written value in memory */ /* Make sure other cores see written value in memory */
flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int)); flush_dcache_all();
} }
void smp_kick_all_cpus(void) void smp_kick_all_cpus(void)